mediatek: mt8183: support CPU hotplug
- Add DCM driver - Add SPMC driver - Implement core and cluster power on/off handlers Change-Id: I902002f8ea6f98fd73bf259188162b10d3939c72 Signed-off-by: kenny liang <kenny.liang@mediatek.com>
This commit is contained in:
kenny liang
parent
f992b960f9
commit
7352f329e8
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@ -73,4 +73,11 @@
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******************************************************************************/
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#define CORTEX_A53_L2MERRSR_EL1 S3_1_C15_C2_3
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/*******************************************************************************
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* Helper function to access a53_cpuectlr_el1 register on Cortex-A53 CPUs
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******************************************************************************/
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#ifndef __ASSEMBLY__
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DEFINE_RENAME_SYSREG_RW_FUNCS(a53_cpuectlr_el1, CORTEX_A53_ECTLR_EL1)
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#endif
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#endif /* CORTEX_A53_H */
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@ -35,4 +35,11 @@
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#define CORTEX_A73_IMP_DEF_REG2 S3_0_C15_C0_2
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/*******************************************************************************
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* Helper function to access a73_cpuectlr_el1 register on Cortex-A73 CPUs
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******************************************************************************/
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#ifndef __ASSEMBLY__
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DEFINE_RENAME_SYSREG_RW_FUNCS(a73_cpuectlr_el1, CORTEX_A73_CPUECTLR_EL1)
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#endif
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#endif /* CORTEX_A73_H */
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2019, MediaTek Inc. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -16,6 +16,7 @@
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#include <mt_gic_v3.h>
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#include <lib/mmio.h>
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#include <mtk_plat_common.h>
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#include <mtspmc.h>
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#include <plat_debug.h>
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#include <plat_private.h>
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#include <platform_def.h>
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@ -95,6 +96,10 @@ void bl31_platform_setup(void)
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/* Init mcsi SF */
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plat_mtk_cci_init_sf();
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#if SPMC_MODE == 1
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spmc_init();
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#endif
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}
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/*******************************************************************************
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@ -0,0 +1,366 @@
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/*
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* Copyright (c) 2019, MediaTek Inc. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <arch_helpers.h>
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#include <cortex_a53.h>
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#include <cortex_a73.h>
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#include <common/debug.h>
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#include <lib/mmio.h>
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#include <platform_def.h>
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#include <mcucfg.h>
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#include <spm.h>
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#include <drivers/delay_timer.h>
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#include <mtspmc.h>
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#include "mtspmc_private.h"
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static void set_retention(int cluster, int tick)
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{
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uint64_t cpuectlr;
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if (cluster)
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cpuectlr = read_a73_cpuectlr_el1();
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else
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cpuectlr = read_a53_cpuectlr_el1();
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cpuectlr &= ~0x7ULL;
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cpuectlr |= tick & 0x7;
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if (cluster)
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write_a73_cpuectlr_el1(cpuectlr);
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else
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write_a53_cpuectlr_el1(cpuectlr);
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}
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void spm_enable_cpu_auto_off(int cluster, int cpu)
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{
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uintptr_t reg = per_cpu(cluster, cpu, MCUCFG_SPARK);
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set_retention(cluster, 1);
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mmio_clrbits_32(reg, SW_NO_WAIT_Q);
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}
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void spm_disable_cpu_auto_off(int cluster, int cpu)
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{
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uintptr_t reg = per_cpu(cluster, cpu, MCUCFG_SPARK);
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mmio_setbits_32(reg, SW_NO_WAIT_Q);
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set_retention(cluster, 0);
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}
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void spm_set_cpu_power_off(int cluster, int cpu)
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{
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mmio_clrbits_32(per_cpu(cluster, cpu, SPM_CPU_PWR), PWRCTRL_PWR_ON);
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}
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void spm_enable_cluster_auto_off(int cluster)
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{
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assert(cluster);
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mmio_clrbits_32(MCUCFG_MP2_SPMC, SW_NO_WAIT_Q);
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mmio_clrbits_32(MCUCFG_MP2_COQ, BIT(0));
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mmio_clrbits_32(SPM_SPMC_DORMANT_ENABLE, MP1_SPMC_SRAM_DORMANT_EN);
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mmio_clrbits_32(per_cluster(cluster, SPM_CLUSTER_PWR), PWRCTRL_PWR_ON);
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}
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void mcucfg_set_bootaddr(int cluster, int cpu, uintptr_t bootaddr)
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{
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uintptr_t reg;
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const uintptr_t mp2_bootreg[] = {
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MCUCFG_MP2_RVADDR0, MCUCFG_MP2_RVADDR1,
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MCUCFG_MP2_RVADDR2, MCUCFG_MP2_RVADDR3 };
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if (cluster) {
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assert(cpu >= 0 && cpu < 4);
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reg = mp2_bootreg[cpu];
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} else {
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reg = per_cpu(cluster, cpu, MCUCFG_BOOTADDR);
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}
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mmio_write_32(reg, bootaddr);
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}
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uintptr_t mcucfg_get_bootaddr(int cluster, int cpu)
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{
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uintptr_t reg;
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const uintptr_t mp2_bootreg[] = {
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MCUCFG_MP2_RVADDR0, MCUCFG_MP2_RVADDR1,
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MCUCFG_MP2_RVADDR2, MCUCFG_MP2_RVADDR3 };
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if (cluster) {
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assert(cpu >= 0 && cpu < 4);
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reg = mp2_bootreg[cpu];
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} else {
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reg = per_cpu(cluster, cpu, MCUCFG_BOOTADDR);
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}
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return mmio_read_32(reg);
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}
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void mcucfg_init_archstate(int cluster, int cpu, int arm64)
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{
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uintptr_t reg;
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int i;
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reg = per_cluster(cluster, MCUCFG_INITARCH);
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i = cluster ? 16 : 12;
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mmio_setbits_32(reg, (arm64 & 1) << (i + cpu));
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}
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/**
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* Return power state of specified subsystem
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*
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* @mask: mask to SPM_PWR_STATUS to query the power state
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* of one subsystem.
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* RETURNS:
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* 0 (the subsys was powered off)
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* 1 (the subsys was powered on)
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*/
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int spm_get_powerstate(uint32_t mask)
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{
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return mmio_read_32(SPM_PWR_STATUS) & mask;
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}
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int spm_get_cluster_powerstate(int cluster)
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{
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uint32_t mask;
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mask = cluster ? PWR_STATUS_MP1_CPUTOP : PWR_STATUS_MP0_CPUTOP;
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return spm_get_powerstate(mask);
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}
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int spm_get_cpu_powerstate(int cluster, int cpu)
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{
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uint32_t i;
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/*
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* a quick way to specify the mask of cpu[0-3]/cpu[4-7] in PWR_STATUS
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* register which are the BITS[9:12](MP0_CPU0~3) and
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* BITS[16:19](MP1_CPU0~3)
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*/
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i = (cluster) ? 16 : 9;
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i = 1 << (i + cpu);
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return spm_get_powerstate(i);
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}
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int spmc_init(void)
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{
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/* enable SPM register control */
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mmio_write_32(SPM_POWERON_CONFIG_EN,
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PROJECT_CODE | MD_BCLK_CG_EN | BCLK_CG_EN);
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#if SPMC_MODE == 1
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INFO("SPM: enable SPMC mode\n");
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/* 0: SPMC mode 1: Legacy mode */
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mmio_write_32(SPM_BYPASS_SPMC, 0);
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mmio_clrbits_32(per_cluster(0, SPM_CLUSTER_PWR), PWRCTRL_PWR_ON_2ND);
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mmio_clrbits_32(per_cpu(0, 0, SPM_CPU_PWR), PWRCTRL_PWR_ON_2ND);
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mmio_clrbits_32(per_cpu(0, 1, SPM_CPU_PWR), PWRCTRL_PWR_ON_2ND);
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mmio_clrbits_32(per_cpu(0, 2, SPM_CPU_PWR), PWRCTRL_PWR_ON_2ND);
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mmio_clrbits_32(per_cpu(0, 3, SPM_CPU_PWR), PWRCTRL_PWR_ON_2ND);
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mmio_setbits_32(per_cpu(0, 1, SPM_CPU_PWR), PWRCTRL_PWR_RST_B);
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mmio_setbits_32(per_cpu(0, 2, SPM_CPU_PWR), PWRCTRL_PWR_RST_B);
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mmio_setbits_32(per_cpu(0, 3, SPM_CPU_PWR), PWRCTRL_PWR_RST_B);
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#endif
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mmio_clrbits_32(per_cluster(1, SPM_CLUSTER_PWR), PWRCTRL_PWR_ON_2ND);
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mmio_setbits_32(per_cluster(1, SPM_CLUSTER_PWR), PWRCTRL_PWR_RST_B);
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mmio_clrbits_32(per_cluster(1, SPM_CLUSTER_PWR), PWRCTRL_PWR_CLK_DIS);
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mmio_clrbits_32(per_cpu(1, 0, SPM_CPU_PWR), PWRCTRL_PWR_ON_2ND);
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mmio_clrbits_32(per_cpu(1, 1, SPM_CPU_PWR), PWRCTRL_PWR_ON_2ND);
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mmio_clrbits_32(per_cpu(1, 2, SPM_CPU_PWR), PWRCTRL_PWR_ON_2ND);
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mmio_clrbits_32(per_cpu(1, 3, SPM_CPU_PWR), PWRCTRL_PWR_ON_2ND);
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mmio_setbits_32(per_cpu(1, 0, SPM_CPU_PWR), PWRCTRL_PWR_RST_B);
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mmio_setbits_32(per_cpu(1, 1, SPM_CPU_PWR), PWRCTRL_PWR_RST_B);
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mmio_setbits_32(per_cpu(1, 2, SPM_CPU_PWR), PWRCTRL_PWR_RST_B);
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mmio_setbits_32(per_cpu(1, 3, SPM_CPU_PWR), PWRCTRL_PWR_RST_B);
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return 0;
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}
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/**
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* Power on a core with specified cluster and core index
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*
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* @cluster: the cluster ID of the CPU which to be powered on
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* @cpu: the CPU ID of the CPU which to be powered on
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*/
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void spm_poweron_cpu(int cluster, int cpu)
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{
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INFO("spmc: power on core %d.%d\n", cluster, cpu);
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/* STA_POWER_ON */
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/* Start to turn on MP0_CPU0 */
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/* Set PWR_RST_B = 1 */
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mmio_setbits_32(per_cpu(cluster, cpu, SPM_CPU_PWR), PWRCTRL_PWR_RST_B);
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/* Set PWR_ON = 1 */
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mmio_setbits_32(per_cpu(cluster, cpu, SPM_CPU_PWR), PWRCTRL_PWR_ON);
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/* Wait until MP0_CPU0_PWR_STA_MASK = 1 */
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while (!spm_get_cpu_powerstate(cluster, cpu))
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;
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/* Finish to turn on MP0_CPU0 */
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INFO("spmc: power on core %d.%d successfully\n", cluster, cpu);
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}
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/**
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* Power off a core with specified cluster and core index
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*
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* @cluster: the cluster ID of the CPU which to be powered off
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* @cpu: the CPU ID of the CPU which to be powered off
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*/
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void spm_poweroff_cpu(int cluster, int cpu)
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{
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INFO("spmc: power off core %d.%d\n", cluster, cpu);
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/* Start to turn off MP0_CPU0 */
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/* Set PWR_ON_2ND = 0 */
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mmio_clrbits_32(per_cpu(cluster, cpu, SPM_CPU_PWR), PWRCTRL_PWR_ON_2ND);
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/* Set PWR_ON = 0 */
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mmio_clrbits_32(per_cpu(cluster, cpu, SPM_CPU_PWR), PWRCTRL_PWR_ON);
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/* Wait until MP0_CPU0_PWR_STA_MASK = 0 */
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while (spm_get_cpu_powerstate(cluster, cpu))
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;
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/* Set PWR_RST_B = 0 */
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mmio_clrbits_32(per_cpu(cluster, cpu, SPM_CPU_PWR), PWRCTRL_PWR_RST_B);
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/* Finish to turn off MP0_CPU0 */
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INFO("spmc: power off core %d.%d successfully\n", cluster, cpu);
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}
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/**
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* Power off a cluster with specified index
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*
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* @cluster: the cluster index which to be powered off
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*/
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void spm_poweroff_cluster(int cluster)
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{
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uint32_t mask;
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uint32_t pwr_rst_ctl;
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INFO("spmc: power off cluster %d\n", cluster);
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/* Start to turn off MP0_CPUTOP */
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/* Set bus protect - step1 : 0 */
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mask = (cluster) ? MP1_CPUTOP_PROT_STEP1_0_MASK :
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MP0_CPUTOP_PROT_STEP1_0_MASK;
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mmio_write_32(INFRA_TOPAXI_PROTECTEN_1_SET, mask);
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while ((mmio_read_32(INFRA_TOPAXI_PROTECTEN_STA1_1) & mask) != mask)
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;
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/* Set PWR_ON_2ND = 0 */
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mmio_clrbits_32(per_cluster(cluster, SPM_CLUSTER_PWR),
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PWRCTRL_PWR_ON_2ND);
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/* SPMC_DORMANT_ENABLE[0]=0 */
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mask = (cluster) ? MP1_SPMC_SRAM_DORMANT_EN : MP0_SPMC_SRAM_DORMANT_EN;
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mmio_clrbits_32(SPM_SPMC_DORMANT_ENABLE, mask);
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/* Set PWR_ON = 0" */
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mmio_clrbits_32(per_cluster(cluster, SPM_CLUSTER_PWR), PWRCTRL_PWR_ON);
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/* Wait until MP0_CPUTOP_PWR_STA_MASK = 0 */
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while (spm_get_cluster_powerstate(cluster))
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;
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/* NOTE
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* Following flow only for BIG core cluster. It was from
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* application note but not covered in mtcmos_ctrl.c
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*/
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if (cluster) {
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pwr_rst_ctl = mmio_read_32(MCUCFG_MP2_PWR_RST_CTL);
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mmio_write_32(MCUCFG_MP2_PWR_RST_CTL,
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(pwr_rst_ctl & ~SW_RST_B) | TOPAON_APB_MASK);
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}
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/* CPU_EXT_BUCK_ISO[0]=1 */
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if (cluster)
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mmio_setbits_32(SPM_CPU_EXT_BUCK_ISO, MP1_EXT_BUCK_ISO);
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/* Finish to turn off MP0_CPUTOP */
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INFO("spmc: power off cluster %d successfully\n", cluster);
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}
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/**
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* Power on a cluster with specified index
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*
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* @cluster: the cluster index which to be powered on
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*/
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void spm_poweron_cluster(int cluster)
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{
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uint32_t mask;
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uint32_t pwr_rst_ctl;
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INFO("spmc: power on cluster %d\n", cluster);
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/* Start to turn on MP1_CPUTOP */
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/* NOTE
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* Following flow only for BIG core cluster. It was from
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* application note but not covered in mtcmos_ctrl.c
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*/
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if (cluster) {
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mmio_clrbits_32(MCUCFG_MP2_PWR_RST_CTL, SW_RST_B);
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/* CPU_EXT_BUCK_ISO[1]=0 */
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/* Set mp<n>_vproc_ext_off to 0 to release vproc isolation control */
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mmio_clrbits_32(SPM_CPU_EXT_BUCK_ISO, MP1_EXT_BUCK_ISO);
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/* NOTE
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* Following flow only for BIG core cluster. It was from
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* application note but not covered in mtcmos_ctrl.c
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*/
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pwr_rst_ctl = mmio_read_32(MCUCFG_MP2_PWR_RST_CTL);
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mmio_write_32(MCUCFG_MP2_PWR_RST_CTL,
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(pwr_rst_ctl | SW_RST_B) & ~TOPAON_APB_MASK);
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}
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/* Set PWR_ON_2ND = 0 */
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mmio_clrbits_32(per_cluster(cluster, SPM_CLUSTER_PWR),
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PWRCTRL_PWR_ON_2ND);
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/* Set PWR_RST_B = 1 */
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mmio_setbits_32(per_cluster(cluster, SPM_CLUSTER_PWR),
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PWRCTRL_PWR_RST_B);
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/* Set PWR_CLK_DIS = 0 */
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mmio_clrbits_32(per_cluster(cluster, SPM_CLUSTER_PWR),
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PWRCTRL_PWR_CLK_DIS);
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/* Set PWR_ON = 1 */
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mmio_setbits_32(per_cluster(cluster, SPM_CLUSTER_PWR), PWRCTRL_PWR_ON);
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/* Wait until MP1_CPUTOP_PWR_STA_MASK = 1 */
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while (!spm_get_cluster_powerstate(cluster))
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;
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/* Release bus protect - step1 : 0 */
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mask = (cluster) ? MP1_CPUTOP_PROT_STEP1_0_MASK :
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MP0_CPUTOP_PROT_STEP1_0_MASK;
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mmio_write_32(INFRA_TOPAXI_PROTECTEN_1_CLR, mask);
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/* Finish to turn on MP1_CPUTOP */
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INFO("spmc: power on cluster %d successfully\n", cluster);
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}
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@ -0,0 +1,42 @@
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/*
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* Copyright (c) 2019, MediaTek Inc. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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|
||||
#ifndef MTSPMC_H
|
||||
#define MTSPMC_H
|
||||
|
||||
/*
|
||||
* CONFIG_SPMC_MODE: Select CPU power control mode.
|
||||
*
|
||||
* 0: Legacy
|
||||
* Control power flow from SW through SPM register (MP*_PWR_CON).
|
||||
* 1: HW
|
||||
* Control power flow from SPMC. Most control flow and timing are handled
|
||||
* by SPMC.
|
||||
*/
|
||||
#define SPMC_MODE 1
|
||||
|
||||
int spmc_init(void);
|
||||
|
||||
void spm_poweron_cpu(int cluster, int cpu);
|
||||
void spm_poweroff_cpu(int cluster, int cpu);
|
||||
|
||||
void spm_poweroff_cluster(int cluster);
|
||||
void spm_poweron_cluster(int cluster);
|
||||
|
||||
int spm_get_cpu_powerstate(int cluster, int cpu);
|
||||
int spm_get_cluster_powerstate(int cluster);
|
||||
int spm_get_powerstate(uint32_t mask);
|
||||
|
||||
void spm_enable_cpu_auto_off(int cluster, int cpu);
|
||||
void spm_disable_cpu_auto_off(int cluster, int cpu);
|
||||
void spm_set_cpu_power_off(int cluster, int cpu);
|
||||
void spm_enable_cluster_auto_off(int cluster);
|
||||
|
||||
void mcucfg_init_archstate(int cluster, int cpu, int arm64);
|
||||
void mcucfg_set_bootaddr(int cluster, int cpu, uintptr_t bootaddr);
|
||||
uintptr_t mcucfg_get_bootaddr(int cluster, int cpu);
|
||||
|
||||
#endif /* MTSPMC_H */
|
||||
|
|
@ -0,0 +1,239 @@
|
|||
/*
|
||||
* Copyright (c) 2019, MediaTek Inc. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef MTSPMC_PRIVATE_H
|
||||
#define MTSPMC_PRIVATE_H
|
||||
|
||||
/*
|
||||
* per_cpu/cluster helper
|
||||
*/
|
||||
struct per_cpu_reg {
|
||||
int cluster_addr;
|
||||
int cpu_stride;
|
||||
};
|
||||
|
||||
#define per_cpu(cluster, cpu, reg) (reg[cluster].cluster_addr + \
|
||||
(cpu << reg[cluster].cpu_stride))
|
||||
#define per_cluster(cluster, reg) (reg[cluster].cluster_addr)
|
||||
|
||||
/* SPMC related registers */
|
||||
#define SPM_POWERON_CONFIG_EN (SPM_BASE + 0x000)
|
||||
/* bit-fields of SPM_POWERON_CONFIG_EN */
|
||||
#define BCLK_CG_EN (1 << 0)
|
||||
#define MD_BCLK_CG_EN (1 << 1)
|
||||
#define PROJECT_CODE (0xb16 << 16)
|
||||
|
||||
#define SPM_PWR_STATUS (SPM_BASE + 0x180)
|
||||
#define SPM_PWR_STATUS_2ND (SPM_BASE + 0x184)
|
||||
|
||||
#define SPM_BYPASS_SPMC (SPM_BASE + 0x2b4)
|
||||
#define SPM_SPMC_DORMANT_ENABLE (SPM_BASE + 0x2b8)
|
||||
|
||||
#define SPM_MP0_CPUTOP_PWR_CON (SPM_BASE + 0x204)
|
||||
#define SPM_MP0_CPU0_PWR_CON (SPM_BASE + 0x208)
|
||||
#define SPM_MP0_CPU1_PWR_CON (SPM_BASE + 0x20C)
|
||||
#define SPM_MP0_CPU2_PWR_CON (SPM_BASE + 0x210)
|
||||
#define SPM_MP0_CPU3_PWR_CON (SPM_BASE + 0x214)
|
||||
#define SPM_MP1_CPUTOP_PWR_CON (SPM_BASE + 0x218)
|
||||
#define SPM_MP1_CPU0_PWR_CON (SPM_BASE + 0x21C)
|
||||
#define SPM_MP1_CPU1_PWR_CON (SPM_BASE + 0x220)
|
||||
#define SPM_MP1_CPU2_PWR_CON (SPM_BASE + 0x224)
|
||||
#define SPM_MP1_CPU3_PWR_CON (SPM_BASE + 0x228)
|
||||
#define SPM_MP0_CPUTOP_L2_PDN (SPM_BASE + 0x240)
|
||||
#define SPM_MP0_CPUTOP_L2_SLEEP_B (SPM_BASE + 0x244)
|
||||
#define SPM_MP0_CPU0_L1_PDN (SPM_BASE + 0x248)
|
||||
#define SPM_MP0_CPU1_L1_PDN (SPM_BASE + 0x24C)
|
||||
#define SPM_MP0_CPU2_L1_PDN (SPM_BASE + 0x250)
|
||||
#define SPM_MP0_CPU3_L1_PDN (SPM_BASE + 0x254)
|
||||
#define SPM_MP1_CPUTOP_L2_PDN (SPM_BASE + 0x258)
|
||||
#define SPM_MP1_CPUTOP_L2_SLEEP_B (SPM_BASE + 0x25C)
|
||||
#define SPM_MP1_CPU0_L1_PDN (SPM_BASE + 0x260)
|
||||
#define SPM_MP1_CPU1_L1_PDN (SPM_BASE + 0x264)
|
||||
#define SPM_MP1_CPU2_L1_PDN (SPM_BASE + 0x268)
|
||||
#define SPM_MP1_CPU3_L1_PDN (SPM_BASE + 0x26C)
|
||||
|
||||
#define SPM_CPU_EXT_BUCK_ISO (SPM_BASE + 0x290)
|
||||
/* bit-fields of SPM_CPU_EXT_BUCK_ISO */
|
||||
#define MP0_EXT_BUCK_ISO (1 << 0)
|
||||
#define MP1_EXT_BUCK_ISO (1 << 1)
|
||||
#define MP_EXT_BUCK_ISO (1 << 2)
|
||||
|
||||
/* bit-fields of SPM_PWR_STATUS */
|
||||
#define PWR_STATUS_MD (1 << 0)
|
||||
#define PWR_STATUS_CONN (1 << 1)
|
||||
#define PWR_STATUS_DDRPHY (1 << 2)
|
||||
#define PWR_STATUS_DISP (1 << 3)
|
||||
#define PWR_STATUS_MFG (1 << 4)
|
||||
#define PWR_STATUS_ISP (1 << 5)
|
||||
#define PWR_STATUS_INFRA (1 << 6)
|
||||
#define PWR_STATUS_VDEC (1 << 7)
|
||||
#define PWR_STATUS_MP0_CPUTOP (1 << 8)
|
||||
#define PWR_STATUS_MP0_CPU0 (1 << 9)
|
||||
#define PWR_STATUS_MP0_CPU1 (1 << 10)
|
||||
#define PWR_STATUS_MP0_CPU2 (1 << 11)
|
||||
#define PWR_STATUS_MP0_CPU3 (1 << 12)
|
||||
#define PWR_STATUS_MCUSYS (1 << 14)
|
||||
#define PWR_STATUS_MP1_CPUTOP (1 << 15)
|
||||
#define PWR_STATUS_MP1_CPU0 (1 << 16)
|
||||
#define PWR_STATUS_MP1_CPU1 (1 << 17)
|
||||
#define PWR_STATUS_MP1_CPU2 (1 << 18)
|
||||
#define PWR_STATUS_MP1_CPU3 (1 << 19)
|
||||
#define PWR_STATUS_VEN (1 << 21)
|
||||
#define PWR_STATUS_MFG_ASYNC (1 << 23)
|
||||
#define PWR_STATUS_AUDIO (1 << 24)
|
||||
#define PWR_STATUS_C2K (1 << 28)
|
||||
#define PWR_STATUS_MD_INFRA (1 << 29)
|
||||
|
||||
|
||||
/* bit-fields of SPM_*_PWR_CON */
|
||||
#define PWRCTRL_PWR_RST_B (1 << 0)
|
||||
#define PWRCTRL_PWR_ISO (1 << 1)
|
||||
#define PWRCTRL_PWR_ON (1 << 2)
|
||||
#define PWRCTRL_PWR_ON_2ND (1 << 3)
|
||||
#define PWRCTRL_PWR_CLK_DIS (1 << 4)
|
||||
#define PWRCTRL_PWR_SRAM_CKISO (1 << 5)
|
||||
#define PWRCTRL_PWR_SRAM_ISOINT_B (1 << 6)
|
||||
#define PWRCTRL_PWR_SRAM_PD_SLPB_CLAMP (1 << 7)
|
||||
#define PWRCTRL_PWR_SRAM_PDN (1 << 8)
|
||||
#define PWRCTRL_PWR_SRAM_SLEEP_B (1 << 12)
|
||||
#define PWRCTRL_PWR_SRAM_PDN_ACK (1 << 24)
|
||||
#define PWRCTRL_PWR_SRAM_SLEEP_B_ACK (1 << 28)
|
||||
|
||||
/* per_cpu registers for SPM_MP?_CPU?_PWR_CON */
|
||||
static const struct per_cpu_reg SPM_CPU_PWR[] = {
|
||||
[0] = { .cluster_addr = SPM_MP0_CPU0_PWR_CON, .cpu_stride = 2 },
|
||||
[1] = { .cluster_addr = SPM_MP1_CPU0_PWR_CON, .cpu_stride = 2 },
|
||||
};
|
||||
|
||||
/* per_cluster registers for SPM_MP?_CPUTOP_PWR_CON */
|
||||
static const struct per_cpu_reg SPM_CLUSTER_PWR[] = {
|
||||
[0] = { .cluster_addr = SPM_MP0_CPUTOP_PWR_CON },
|
||||
[1] = { .cluster_addr = SPM_MP1_CPUTOP_PWR_CON },
|
||||
};
|
||||
|
||||
/* APB Module infracfg_ao */
|
||||
#define INFRA_TOPAXI_PROTECTEN_1 (INFRACFG_AO_BASE + 0x250)
|
||||
#define INFRA_TOPAXI_PROTECTEN_STA1_1 (INFRACFG_AO_BASE + 0x258)
|
||||
#define INFRA_TOPAXI_PROTECTEN_1_SET (INFRACFG_AO_BASE + 0x2A8)
|
||||
#define INFRA_TOPAXI_PROTECTEN_1_CLR (INFRACFG_AO_BASE + 0x2AC)
|
||||
|
||||
/* bit-fields of INFRA_TOPAXI_PROTECTEN_1_SET */
|
||||
#define MP0_CPUTOP_PROT_STEP1_0_MASK ((1 << 10)|(1 << 12)| \
|
||||
(1 << 13)|(1 << 26))
|
||||
#define MP1_CPUTOP_PROT_STEP1_0_MASK ((1 << 11)|(1 << 14)| \
|
||||
(1 << 15)|(1 << 27))
|
||||
|
||||
/* bit-fields of INFRA_TOPAXI_PROTECTEN_STA1_1 */
|
||||
#define MP0_CPUTOP_PROT_STEP1_0_ACK_MASK ((1 << 10)|(1 << 12)| \
|
||||
(1 << 13)|(1 << 26))
|
||||
#define MP1_CPUTOP_PROT_STEP1_0_ACK_MASK ((1 << 11)|(1 << 14)| \
|
||||
(1 << 15)|(1 << 27))
|
||||
|
||||
|
||||
/*
|
||||
* MCU configuration registers
|
||||
*/
|
||||
#define MCUCFG_MP0_AXI_CONFIG ((uintptr_t)&mt8183_mcucfg->mp0_axi_config)
|
||||
#define MCUCFG_MP1_AXI_CONFIG ((uintptr_t)&mt8183_mcucfg->mp1_axi_config)
|
||||
/* bit-fields of MCUCFG_MP?_AXI_CONFIG */
|
||||
#define MCUCFG_AXI_CONFIG_BROADCASTINNER (1 << 0)
|
||||
#define MCUCFG_AXI_CONFIG_BROADCASTOUTER (1 << 1)
|
||||
#define MCUCFG_AXI_CONFIG_BROADCASTCACHEMAINT (1 << 2)
|
||||
#define MCUCFG_AXI_CONFIG_SYSBARDISABLE (1 << 3)
|
||||
#define MCUCFG_AXI_CONFIG_ACINACTM (1 << 4)
|
||||
#define MCUCFG_AXI_CONFIG_AINACTS (1 << 5)
|
||||
|
||||
/* per_cpu registers for MCUCFG_MP?_AXI_CONFIG */
|
||||
static const struct per_cpu_reg MCUCFG_SCUCTRL[] = {
|
||||
[0] = { .cluster_addr = MCUCFG_MP0_AXI_CONFIG },
|
||||
[1] = { .cluster_addr = MCUCFG_MP1_AXI_CONFIG },
|
||||
};
|
||||
|
||||
#define MCUCFG_MP0_MISC_CONFIG2 ((uintptr_t)&mt8183_mcucfg->mp0_misc_config[2])
|
||||
#define MCUCFG_MP0_MISC_CONFIG3 ((uintptr_t)&mt8183_mcucfg->mp0_misc_config[3])
|
||||
#define MCUCFG_MP1_MISC_CONFIG2 ((uintptr_t)&mt8183_mcucfg->mp1_misc_config[2])
|
||||
#define MCUCFG_MP1_MISC_CONFIG3 ((uintptr_t)&mt8183_mcucfg->mp1_misc_config[3])
|
||||
|
||||
#define MCUCFG_CPUSYS0_SPARKVRETCNTRL (MCUCFG_BASE + 0x1c00)
|
||||
/* bit-fields of MCUCFG_CPUSYS0_SPARKVRETCNTRL */
|
||||
#define CPU0_SPARK_VRET_CTRL (0x3f << 0)
|
||||
#define CPU1_SPARK_VRET_CTRL (0x3f << 8)
|
||||
#define CPU2_SPARK_VRET_CTRL (0x3f << 16)
|
||||
#define CPU3_SPARK_VRET_CTRL (0x3f << 24)
|
||||
|
||||
/* SPARK control in little cores */
|
||||
#define MCUCFG_CPUSYS0_CPU0_SPMC_CTL (MCUCFG_BASE + 0x1c30)
|
||||
#define MCUCFG_CPUSYS0_CPU1_SPMC_CTL (MCUCFG_BASE + 0x1c34)
|
||||
#define MCUCFG_CPUSYS0_CPU2_SPMC_CTL (MCUCFG_BASE + 0x1c38)
|
||||
#define MCUCFG_CPUSYS0_CPU3_SPMC_CTL (MCUCFG_BASE + 0x1c3c)
|
||||
/* bit-fields of MCUCFG_CPUSYS0_CPU?_SPMC_CTL */
|
||||
#define SW_SPARK_EN (1 << 0)
|
||||
#define SW_NO_WAIT_Q (1 << 1)
|
||||
|
||||
/* the MCUCFG which BIG cores used is at (MCUCFG_BASE + 0x2000) */
|
||||
#define MCUCFG_MP2_BASE (MCUCFG_BASE + 0x2000)
|
||||
#define MCUCFG_MP2_PWR_RST_CTL (MCUCFG_MP2_BASE + 0x8)
|
||||
/* bit-fields of MCUCFG_MP2_PWR_RST_CTL */
|
||||
#define SW_RST_B (1 << 0)
|
||||
#define TOPAON_APB_MASK (1 << 1)
|
||||
|
||||
#define MCUCFG_MP2_CPUCFG (MCUCFG_MP2_BASE + 0x208)
|
||||
|
||||
#define MCUCFG_MP2_RVADDR0 (MCUCFG_MP2_BASE + 0x290)
|
||||
#define MCUCFG_MP2_RVADDR1 (MCUCFG_MP2_BASE + 0x298)
|
||||
#define MCUCFG_MP2_RVADDR2 (MCUCFG_MP2_BASE + 0x2c0)
|
||||
#define MCUCFG_MP2_RVADDR3 (MCUCFG_MP2_BASE + 0x2c8)
|
||||
|
||||
/* SPMC control */
|
||||
#define MCUCFG_MP0_SPMC (MCUCFG_BASE + 0x788)
|
||||
#define MCUCFG_MP2_SPMC (MCUCFG_MP2_BASE + 0x2a0)
|
||||
#define MCUCFG_MP2_COQ (MCUCFG_MP2_BASE + 0x2bC)
|
||||
|
||||
/* per_cpu registers for MCUCFG_MP?_MISC_CONFIG2 */
|
||||
static const struct per_cpu_reg MCUCFG_BOOTADDR[] = {
|
||||
[0] = { .cluster_addr = MCUCFG_MP0_MISC_CONFIG2, .cpu_stride = 3 },
|
||||
};
|
||||
|
||||
/* per_cpu registers for MCUCFG_MP?_MISC_CONFIG3 */
|
||||
static const struct per_cpu_reg MCUCFG_INITARCH[] = {
|
||||
[0] = { .cluster_addr = MCUCFG_MP0_MISC_CONFIG3 },
|
||||
[1] = { .cluster_addr = MCUCFG_MP2_CPUCFG },
|
||||
};
|
||||
|
||||
/* SPARK control in BIG cores */
|
||||
#define MCUCFG_MP2_PTP3_CPU0_SPMC0 (MCUCFG_MP2_BASE + 0x430)
|
||||
#define MCUCFG_MP2_PTP3_CPU0_SPMC1 (MCUCFG_MP2_BASE + 0x434)
|
||||
#define MCUCFG_MP2_PTP3_CPU1_SPMC0 (MCUCFG_MP2_BASE + 0x438)
|
||||
#define MCUCFG_MP2_PTP3_CPU1_SPMC1 (MCUCFG_MP2_BASE + 0x43c)
|
||||
#define MCUCFG_MP2_PTP3_CPU2_SPMC0 (MCUCFG_MP2_BASE + 0x440)
|
||||
#define MCUCFG_MP2_PTP3_CPU2_SPMC1 (MCUCFG_MP2_BASE + 0x444)
|
||||
#define MCUCFG_MP2_PTP3_CPU3_SPMC0 (MCUCFG_MP2_BASE + 0x448)
|
||||
#define MCUCFG_MP2_PTP3_CPU3_SPMC1 (MCUCFG_MP2_BASE + 0x44c)
|
||||
/* bit-fields of MCUCFG_MP2_PTP3_CPU?_SPMC? */
|
||||
#define SW_SPARK_EN (1 << 0)
|
||||
#define SW_NO_WAIT_Q (1 << 1)
|
||||
|
||||
#define MCUCFG_MP2_SPARK2LDO (MCUCFG_MP2_BASE + 0x700)
|
||||
/* bit-fields of MCUCFG_MP2_SPARK2LDO */
|
||||
#define SPARK_VRET_CTRL (0x3f << 0)
|
||||
#define CPU0_SPARK_LDO_AMUXSEL (0xf << 6)
|
||||
#define CPU1_SPARK_LDO_AMUXSEL (0xf << 10)
|
||||
#define CPU2_SPARK_LDO_AMUXSEL (0xf << 14)
|
||||
#define CPU3_SPARK_LDO_AMUXSEL (0xf << 18)
|
||||
|
||||
/* per_cpu registers for SPARK */
|
||||
static const struct per_cpu_reg MCUCFG_SPARK[] = {
|
||||
[0] = { .cluster_addr = MCUCFG_CPUSYS0_CPU0_SPMC_CTL, .cpu_stride = 2 },
|
||||
[1] = { .cluster_addr = MCUCFG_MP2_PTP3_CPU0_SPMC0, .cpu_stride = 3 },
|
||||
};
|
||||
|
||||
/* per_cpu registers for SPARK2LDO */
|
||||
static const struct per_cpu_reg MCUCFG_SPARK2LDO[] = {
|
||||
[0] = { .cluster_addr = MCUCFG_CPUSYS0_SPARKVRETCNTRL },
|
||||
[1] = { .cluster_addr = MCUCFG_MP2_SPARK2LDO },
|
||||
};
|
||||
|
||||
#endif /* MTSPMC_PRIVATE_H */
|
||||
|
|
@ -0,0 +1,53 @@
|
|||
/*
|
||||
* Copyright (c) 2019, MediaTek Inc. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef PLAT_DCM_H
|
||||
#define PLAT_DCM_H
|
||||
|
||||
#define MP2_SYNC_DCM (MCUCFG_BASE + 0x2274)
|
||||
#define MP2_SYNC_DCM_MASK (0x1 << 0)
|
||||
#define MP2_SYNC_DCM_ON (0x1 << 0)
|
||||
#define MP2_SYNC_DCM_OFF (0x0 << 0)
|
||||
|
||||
extern uint64_t plat_dcm_mcsi_a_addr;
|
||||
extern uint32_t plat_dcm_mcsi_a_val;
|
||||
extern int plat_dcm_initiated;
|
||||
|
||||
extern void plat_dcm_mcsi_a_backup(void);
|
||||
extern void plat_dcm_mcsi_a_restore(void);
|
||||
extern void plat_dcm_rgu_enable(void);
|
||||
extern void plat_dcm_restore_cluster_on(unsigned long mpidr);
|
||||
extern void plat_dcm_msg_handler(uint64_t x1);
|
||||
extern unsigned long plat_dcm_get_enabled_cnt(uint64_t type);
|
||||
extern void plat_dcm_init(void);
|
||||
|
||||
#define ALL_DCM_TYPE (ARMCORE_DCM_TYPE | MCUSYS_DCM_TYPE \
|
||||
| STALL_DCM_TYPE | BIG_CORE_DCM_TYPE \
|
||||
| GIC_SYNC_DCM_TYPE | RGU_DCM_TYPE \
|
||||
| INFRA_DCM_TYPE \
|
||||
| DDRPHY_DCM_TYPE | EMI_DCM_TYPE | DRAMC_DCM_TYPE \
|
||||
| MCSI_DCM_TYPE)
|
||||
|
||||
enum {
|
||||
ARMCORE_DCM_TYPE = (1U << 0),
|
||||
MCUSYS_DCM_TYPE = (1U << 1),
|
||||
INFRA_DCM_TYPE = (1U << 2),
|
||||
PERI_DCM_TYPE = (1U << 3),
|
||||
EMI_DCM_TYPE = (1U << 4),
|
||||
DRAMC_DCM_TYPE = (1U << 5),
|
||||
DDRPHY_DCM_TYPE = (1U << 6),
|
||||
STALL_DCM_TYPE = (1U << 7),
|
||||
BIG_CORE_DCM_TYPE = (1U << 8),
|
||||
GIC_SYNC_DCM_TYPE = (1U << 9),
|
||||
LAST_CORE_DCM_TYPE = (1U << 10),
|
||||
RGU_DCM_TYPE = (1U << 11),
|
||||
TOPCKG_DCM_TYPE = (1U << 12),
|
||||
LPDMA_DCM_TYPE = (1U << 13),
|
||||
MCSI_DCM_TYPE = (1U << 14),
|
||||
NR_DCM_TYPE = 15,
|
||||
};
|
||||
|
||||
#endif /* PLAT_DCM_H */
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,112 @@
|
|||
/*
|
||||
* Copyright (c) 2019, MediaTek Inc. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <arch.h>
|
||||
#include <lib/bakery_lock.h>
|
||||
#include <drivers/console.h>
|
||||
#include <common/debug.h>
|
||||
#include <lib/mmio.h>
|
||||
#include <plat_dcm.h>
|
||||
#include <plat_private.h>
|
||||
#include <plat_dcm.h>
|
||||
#include <plat/common/platform.h>
|
||||
#include <platform_def.h>
|
||||
#include <mtk_plat_common.h>
|
||||
|
||||
#define PWR_STATUS (SPM_BASE + 0x180)
|
||||
|
||||
uint64_t plat_dcm_mcsi_a_addr;
|
||||
uint32_t plat_dcm_mcsi_a_val;
|
||||
static int plat_dcm_init_type;
|
||||
static unsigned int dcm_big_core_cnt;
|
||||
int plat_dcm_initiated;
|
||||
|
||||
#define PWR_STA_BIG_MP_MASK (0x1 << 15)
|
||||
|
||||
DEFINE_BAKERY_LOCK(dcm_lock);
|
||||
|
||||
void dcm_lock_init(void)
|
||||
{
|
||||
bakery_lock_init(&dcm_lock);
|
||||
}
|
||||
|
||||
void dcm_lock_get(void)
|
||||
{
|
||||
bakery_lock_get(&dcm_lock);
|
||||
}
|
||||
|
||||
void dcm_lock_release(void)
|
||||
{
|
||||
bakery_lock_release(&dcm_lock);
|
||||
}
|
||||
|
||||
void plat_dcm_mcsi_a_backup(void)
|
||||
{
|
||||
}
|
||||
|
||||
void plat_dcm_mcsi_a_restore(void)
|
||||
{
|
||||
}
|
||||
|
||||
void plat_dcm_rgu_enable(void)
|
||||
{
|
||||
}
|
||||
|
||||
void plat_dcm_big_core_sync(short on)
|
||||
{
|
||||
/* Check if Big cluster power is existed */
|
||||
if (!(mmio_read_32(PWR_STATUS) & PWR_STA_BIG_MP_MASK))
|
||||
return;
|
||||
|
||||
if (on) {
|
||||
mmio_write_32(MP2_SYNC_DCM,
|
||||
(mmio_read_32(MP2_SYNC_DCM) & ~MP2_SYNC_DCM_MASK)
|
||||
| MP2_SYNC_DCM_ON);
|
||||
dcm_big_core_cnt++;
|
||||
} else
|
||||
mmio_write_32(MP2_SYNC_DCM,
|
||||
(mmio_read_32(MP2_SYNC_DCM) & ~MP2_SYNC_DCM_MASK)
|
||||
| MP2_SYNC_DCM_OFF);
|
||||
}
|
||||
|
||||
void plat_dcm_restore_cluster_on(unsigned long mpidr)
|
||||
{
|
||||
unsigned long cluster_id =
|
||||
(mpidr & MPIDR_CLUSTER_MASK) >> MPIDR_AFFINITY_BITS;
|
||||
|
||||
switch (cluster_id) {
|
||||
case 0x1:
|
||||
dcm_lock_get();
|
||||
if (plat_dcm_init_type & BIG_CORE_DCM_TYPE)
|
||||
plat_dcm_big_core_sync(1);
|
||||
else
|
||||
plat_dcm_big_core_sync(0);
|
||||
dcm_lock_release();
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
void plat_dcm_msg_handler(uint64_t x1)
|
||||
{
|
||||
plat_dcm_init_type = x1 & ALL_DCM_TYPE;
|
||||
}
|
||||
|
||||
unsigned long plat_dcm_get_enabled_cnt(uint64_t type)
|
||||
{
|
||||
switch (type) {
|
||||
case BIG_CORE_DCM_TYPE:
|
||||
return dcm_big_core_cnt;
|
||||
default:
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
|
||||
void plat_dcm_init(void)
|
||||
{
|
||||
dcm_lock_init();
|
||||
}
|
||||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
|
||||
* Copyright (c) 2019, MediaTek Inc. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
|
@ -15,21 +15,114 @@
|
|||
/* mediatek platform specific headers */
|
||||
#include <platform_def.h>
|
||||
#include <scu.h>
|
||||
#include <mt_gic_v3.h>
|
||||
#include <mtk_plat_common.h>
|
||||
#include <mtspmc.h>
|
||||
#include <power_tracer.h>
|
||||
#include <plat_dcm.h>
|
||||
#include <plat_debug.h>
|
||||
#include <plat_private.h>
|
||||
|
||||
#define MTK_LOCAL_STATE_OFF 2
|
||||
|
||||
static uintptr_t secure_entrypoint;
|
||||
|
||||
static void mp1_L2_desel_config(void)
|
||||
{
|
||||
mmio_write_64(MCUCFG_BASE + 0x2200, 0x2092c820);
|
||||
|
||||
dsb();
|
||||
}
|
||||
|
||||
static int plat_mtk_power_domain_on(unsigned long mpidr)
|
||||
{
|
||||
int cpu = MPIDR_AFFLVL0_VAL(mpidr);
|
||||
int cluster = MPIDR_AFFLVL1_VAL(mpidr);
|
||||
|
||||
INFO("%s():%d: mpidr: %lx, c.c: %d.%d\n",
|
||||
__func__, __LINE__, mpidr, cluster, cpu);
|
||||
|
||||
/* power on cluster */
|
||||
if (!spm_get_cluster_powerstate(cluster)) {
|
||||
spm_poweron_cluster(cluster);
|
||||
if (cluster == 1) {
|
||||
l2c_parity_check_setup();
|
||||
circular_buffer_setup();
|
||||
mp1_L2_desel_config();
|
||||
mt_gic_sync_dcm_disable();
|
||||
}
|
||||
}
|
||||
|
||||
/* init cpu reset arch as AARCH64 */
|
||||
mcucfg_init_archstate(cluster, cpu, 1);
|
||||
mcucfg_set_bootaddr(cluster, cpu, secure_entrypoint);
|
||||
|
||||
spm_poweron_cpu(cluster, cpu);
|
||||
|
||||
return PSCI_E_SUCCESS;
|
||||
}
|
||||
|
||||
static void plat_mtk_power_domain_off(const psci_power_state_t *state)
|
||||
{
|
||||
uint64_t mpidr = read_mpidr();
|
||||
int cpu = MPIDR_AFFLVL0_VAL(mpidr);
|
||||
int cluster = MPIDR_AFFLVL1_VAL(mpidr);
|
||||
|
||||
INFO("%s():%d: c.c: %d.%d\n", __func__, __LINE__, cluster, cpu);
|
||||
|
||||
/* Prevent interrupts from spuriously waking up this cpu */
|
||||
mt_gic_cpuif_disable();
|
||||
|
||||
spm_enable_cpu_auto_off(cluster, cpu);
|
||||
|
||||
if (state->pwr_domain_state[MPIDR_AFFLVL1] == MTK_LOCAL_STATE_OFF) {
|
||||
if (cluster == 1)
|
||||
mt_gic_sync_dcm_enable();
|
||||
|
||||
plat_mtk_cci_disable();
|
||||
spm_enable_cluster_auto_off(cluster);
|
||||
}
|
||||
|
||||
spm_set_cpu_power_off(cluster, cpu);
|
||||
}
|
||||
|
||||
static void plat_mtk_power_domain_on_finish(const psci_power_state_t *state)
|
||||
{
|
||||
uint64_t mpidr = read_mpidr();
|
||||
int cpu = MPIDR_AFFLVL0_VAL(mpidr);
|
||||
int cluster = MPIDR_AFFLVL1_VAL(mpidr);
|
||||
|
||||
INFO("%s():%d: c.c: %d.%d\n", __func__, __LINE__, cluster, cpu);
|
||||
|
||||
assert(state->pwr_domain_state[MPIDR_AFFLVL0] == MTK_LOCAL_STATE_OFF);
|
||||
|
||||
if (state->pwr_domain_state[MPIDR_AFFLVL1] == MTK_LOCAL_STATE_OFF) {
|
||||
enable_scu(mpidr);
|
||||
|
||||
/* Enable coherency if this cluster was off */
|
||||
plat_mtk_cci_enable();
|
||||
/* Enable big core dcm if this cluster was on */
|
||||
plat_dcm_restore_cluster_on(mpidr);
|
||||
/* Enable rgu dcm if this cluster was off */
|
||||
plat_dcm_rgu_enable();
|
||||
}
|
||||
|
||||
spm_disable_cpu_auto_off(cluster, cpu);
|
||||
|
||||
/* Enable the gic cpu interface */
|
||||
mt_gic_pcpu_init();
|
||||
mt_gic_cpuif_enable();
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* MTK_platform handler called when an affinity instance is about to be turned
|
||||
* on. The level and mpidr determine the affinity instance.
|
||||
******************************************************************************/
|
||||
static uintptr_t secure_entrypoint;
|
||||
|
||||
static const plat_psci_ops_t plat_plat_pm_ops = {
|
||||
.cpu_standby = NULL,
|
||||
.pwr_domain_on = NULL,
|
||||
.pwr_domain_on_finish = NULL,
|
||||
.pwr_domain_off = NULL,
|
||||
.pwr_domain_on = plat_mtk_power_domain_on,
|
||||
.pwr_domain_on_finish = plat_mtk_power_domain_on_finish,
|
||||
.pwr_domain_off = plat_mtk_power_domain_off,
|
||||
.pwr_domain_suspend = NULL,
|
||||
.pwr_domain_suspend_finish = NULL,
|
||||
.system_off = NULL,
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
#
|
||||
# Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
|
||||
# Copyright (c) 2019, MediaTek Inc. All rights reserved.
|
||||
#
|
||||
# SPDX-License-Identifier: BSD-3-Clause
|
||||
#
|
||||
|
|
@ -9,6 +9,7 @@ MTK_PLAT_SOC := ${MTK_PLAT}/${PLAT}
|
|||
|
||||
PLAT_INCLUDES := -I${MTK_PLAT}/common/ \
|
||||
-I${MTK_PLAT_SOC}/drivers/ \
|
||||
-I${MTK_PLAT_SOC}/drivers/spmc/ \
|
||||
-I${MTK_PLAT_SOC}/include/
|
||||
|
||||
PLAT_BL_COMMON_SOURCES := lib/xlat_tables/aarch64/xlat_tables.c \
|
||||
|
|
@ -35,9 +36,11 @@ BL31_SOURCES += common/desc_image_load.c \
|
|||
${MTK_PLAT_SOC}/aarch64/plat_helpers.S \
|
||||
${MTK_PLAT_SOC}/aarch64/platform_common.c \
|
||||
${MTK_PLAT_SOC}/drivers/mcsi/mcsi.c \
|
||||
${MTK_PLAT_SOC}/drivers/spmc/mtspmc.c \
|
||||
${MTK_PLAT_SOC}/plat_pm.c \
|
||||
${MTK_PLAT_SOC}/plat_topology.c \
|
||||
${MTK_PLAT_SOC}/plat_mt_gic.c \
|
||||
${MTK_PLAT_SOC}/plat_dcm.c \
|
||||
${MTK_PLAT_SOC}/bl31_plat_setup.c \
|
||||
${MTK_PLAT_SOC}/plat_debug.c \
|
||||
${MTK_PLAT_SOC}/scu.c
|
||||
|
|
|
|||
Loading…
Reference in New Issue