SPM: Use generic MMU setup functions
Instead of having a different initialization routine than the rest of the codebase, use the common implementation. Change-Id: I27c03b9905f3cf0af8810aad9e43092005387a1a Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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@ -107,38 +107,22 @@ void spm_sp_setup(sp_context_t *sp_ctx)
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* MMU-related registers
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* MMU-related registers
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* ---------------------
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* ---------------------
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*/
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*/
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xlat_ctx_t *xlat_ctx = sp_ctx->xlat_ctx_handle;
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/* Set attributes in the right indices of the MAIR */
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uint64_t mmu_cfg_params[MMU_CFG_PARAM_MAX];
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u_register_t mair_el1 =
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MAIR_ATTR_SET(ATTR_DEVICE, ATTR_DEVICE_INDEX) |
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MAIR_ATTR_SET(ATTR_IWBWA_OWBWA_NTR, ATTR_IWBWA_OWBWA_NTR_INDEX) |
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MAIR_ATTR_SET(ATTR_NON_CACHEABLE, ATTR_NON_CACHEABLE_INDEX);
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write_ctx_reg(get_sysregs_ctx(ctx), CTX_MAIR_EL1, mair_el1);
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setup_mmu_cfg((uint64_t *)&mmu_cfg_params, 0, xlat_ctx->base_table,
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xlat_ctx->pa_max_address, xlat_ctx->va_max_address,
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EL1_EL0_REGIME);
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/* Setup TCR_EL1. */
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write_ctx_reg(get_sysregs_ctx(ctx), CTX_MAIR_EL1,
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u_register_t tcr_ps_bits = tcr_physical_addr_size_bits(PLAT_PHY_ADDR_SPACE_SIZE);
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mmu_cfg_params[MMU_CFG_MAIR]);
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u_register_t tcr_el1 =
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write_ctx_reg(get_sysregs_ctx(ctx), CTX_TCR_EL1,
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/* Size of region addressed by TTBR0_EL1 = 2^(64-T0SZ) bytes. */
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mmu_cfg_params[MMU_CFG_TCR]);
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(64 - __builtin_ctzl(PLAT_VIRT_ADDR_SPACE_SIZE)) |
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/* Inner and outer WBWA, shareable. */
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TCR_SH_INNER_SHAREABLE | TCR_RGN_OUTER_WBA | TCR_RGN_INNER_WBA |
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/* Set the granularity to 4KB. */
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TCR_TG0_4K |
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/* Limit Intermediate Physical Address Size. */
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tcr_ps_bits << TCR_EL1_IPS_SHIFT |
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/* Disable translations using TBBR1_EL1. */
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TCR_EPD1_BIT
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/* The remaining fields related to TBBR1_EL1 are left as zero. */
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;
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tcr_el1 &= ~(
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write_ctx_reg(get_sysregs_ctx(ctx), CTX_TTBR0_EL1,
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/* Enable translations using TBBR0_EL1 */
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mmu_cfg_params[MMU_CFG_TTBR0]);
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TCR_EPD0_BIT
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);
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write_ctx_reg(get_sysregs_ctx(ctx), CTX_TCR_EL1, tcr_el1);
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/* Setup SCTLR_EL1 */
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/* Setup SCTLR_EL1 */
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u_register_t sctlr_el1 = read_ctx_reg(get_sysregs_ctx(ctx), CTX_SCTLR_EL1);
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u_register_t sctlr_el1 = read_ctx_reg(get_sysregs_ctx(ctx), CTX_SCTLR_EL1);
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@ -174,13 +158,6 @@ void spm_sp_setup(sp_context_t *sp_ctx)
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write_ctx_reg(get_sysregs_ctx(ctx), CTX_SCTLR_EL1, sctlr_el1);
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write_ctx_reg(get_sysregs_ctx(ctx), CTX_SCTLR_EL1, sctlr_el1);
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uint64_t *xlat_base =
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((xlat_ctx_t *)sp_ctx->xlat_ctx_handle)->base_table;
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/* Point TTBR0_EL1 at the tables of the context created for the SP. */
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write_ctx_reg(get_sysregs_ctx(ctx), CTX_TTBR0_EL1,
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(u_register_t)xlat_base);
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/*
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/*
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* Setup other system registers
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* Setup other system registers
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* ----------------------------
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* ----------------------------
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