juno: Implement PM ops to power on CPUs
Signed-off-by: Jon Medhurst <tixy@linaro.org>
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dbf5789ea6
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7441ac3a24
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@ -28,6 +28,7 @@
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* POSSIBILITY OF SUCH DAMAGE.
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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*/
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#include <mhu.h>
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#include <platform.h>
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#include <platform.h>
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#include <assert.h>
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#include <assert.h>
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#include <arch_helpers.h>
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#include <arch_helpers.h>
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@ -115,6 +116,9 @@ void bl31_early_platform_setup(bl31_args *from_bl2,
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void bl31_platform_setup(void)
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void bl31_platform_setup(void)
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{
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{
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unsigned int counter_base_frequency;
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unsigned int counter_base_frequency;
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mhu_secure_init();
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/* Initialize the gic cpu and distributor interfaces */
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/* Initialize the gic cpu and distributor interfaces */
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gic_setup();
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gic_setup();
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@ -28,14 +28,77 @@
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* POSSIBILITY OF SUCH DAMAGE.
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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*/
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#include <stdint.h>
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#include <arch_helpers.h>
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#include <cci400.h>
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#include <platform.h>
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#include <psci.h>
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#include <psci.h>
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#include <scpi.h>
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int pm_on(unsigned long mpidr,
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unsigned long sec_entrypoint,
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unsigned long ns_entrypoint,
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unsigned int afflvl,
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unsigned int state)
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{
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/*
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* SCP takes care of powering up higher affinity levels so we
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* only need to care about level 0
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*/
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if (afflvl != MPIDR_AFFLVL0)
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return PSCI_E_SUCCESS;
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/*
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* Setup mailbox with address for CPU entrypoint when it next powers up
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*/
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unsigned long *mbox = (unsigned long *)(unsigned long)(
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TRUSTED_MAILBOXES_BASE +
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(platform_get_core_pos(mpidr) << TRUSTED_MAILBOX_SHIFT)
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);
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*mbox = sec_entrypoint;
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flush_dcache_range((unsigned long)mbox, sizeof(*mbox));
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scpi_set_css_power_state(mpidr, scpi_power_on, scpi_power_on,
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scpi_power_on);
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return PSCI_E_SUCCESS;
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}
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int pm_on_finish(unsigned long mpidr, unsigned int afflvl, unsigned int state)
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{
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switch (afflvl) {
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case MPIDR_AFFLVL1:
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/* Enable coherency if this cluster was off */
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if (state == PSCI_STATE_OFF)
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cci_enable_coherency(mpidr);
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break;
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case MPIDR_AFFLVL0:
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/*
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* Ignore the state passed for a cpu. It could only have
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* been off if we are here.
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*/
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/* Turn on intra-cluster coherency. */
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write_cpuectlr(read_cpuectlr() | CPUECTLR_SMP_BIT);
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/* Enable the gic cpu interface */
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gic_cpuif_setup(GICC_BASE);
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/* Juno todo: Is this setup only needed after a cold boot? */
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gic_pcpu_distif_setup(GICD_BASE);
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break;
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}
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return PSCI_E_SUCCESS;
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}
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/*******************************************************************************
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/*******************************************************************************
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* Export the platform handlers to enable psci to invoke them
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* Export the platform handlers to enable psci to invoke them
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******************************************************************************/
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******************************************************************************/
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static plat_pm_ops pm_ops = {
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static plat_pm_ops pm_ops = {
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0
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.affinst_on = pm_on,
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.affinst_on_finish = pm_on_finish
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};
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};
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/*******************************************************************************
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/*******************************************************************************
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@ -77,16 +77,22 @@ BL1_SOURCES += bl1_plat_setup.c \
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plat_common.c \
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plat_common.c \
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cci400.c
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cci400.c
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BL2_SOURCES += bl2_plat_setup.c \
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BL2_SOURCES += bakery_lock.c \
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bl2_plat_setup.c \
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mhu.c \
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plat_helpers.S \
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plat_helpers.S \
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plat_common.c
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plat_common.c \
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scp_bootloader.c \
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scpi.c
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BL31_SOURCES += bl31_plat_setup.c \
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BL31_SOURCES += bl31_plat_setup.c \
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mhu.c \
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plat_helpers.S \
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plat_helpers.S \
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plat_common.c \
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plat_common.c \
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plat_pm.c \
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plat_pm.c \
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plat_topology.c \
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plat_topology.c \
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plat_gic.c \
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plat_gic.c \
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scpi.c \
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cci400.c \
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cci400.c \
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gic_v2.c \
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gic_v2.c \
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gic_v3.c
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gic_v3.c
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