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Merge pull request #1399 from danielboulby-arm/db/MISRA 

MISRA 5.1, 5.3 & 5.7 compliance changes
This commit is contained in:
Dimitris Papastamos 2018-06-13 13:32:14 +01:00 committed by GitHub
parent e109b0ffea 776ff52a8d
commit 74a44dca29
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
23 changed files with 159 additions and 159 deletions
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2
common/bl_common.c
View File

@ -184,7 +184,7 @@ static void dump_load_info(uintptr_t image_load_addr,
#endif /* LOAD_IMAGE_V2 */
/* Generic function to return the size of an image */
size_t image_size(unsigned int image_id)
size_t get_image_size(unsigned int image_id)
{
uintptr_t dev_handle;
uintptr_t image_handle;

12
common/tf_printf.c
View File

@ -15,13 +15,13 @@
* The tf_printf implementation for all BL stages
***********************************************************/
#define get_num_va_args(args, lcount) \
(((lcount) > 1) ? va_arg(args, long long int) : \
((lcount) ? va_arg(args, long int) : va_arg(args, int)))
#define get_num_va_args(_args, _lcount) \
(((_lcount) > 1) ? va_arg(_args, long long int) : \
((_lcount) ? va_arg(_args, long int) : va_arg(_args, int)))
#define get_unum_va_args(args, lcount) \
(((lcount) > 1) ? va_arg(args, unsigned long long int) : \
((lcount) ? va_arg(args, unsigned long int) : va_arg(args, unsigned int)))
#define get_unum_va_args(_args, _lcount) \
(((_lcount) > 1) ? va_arg(_args, unsigned long long int) : \
((_lcount) ? va_arg(_args, unsigned long int) : va_arg(_args, unsigned int)))
void tf_string_print(const char *str)
{

12
drivers/arm/gic/v3/gicv3_helpers.c
View File

@ -342,7 +342,7 @@ void gicv3_rdistif_base_addrs_probe(uintptr_t *rdistif_base_addrs,
/*******************************************************************************
* Helper function to configure the default attributes of SPIs.
******************************************************************************/
void gicv3_spis_configure_defaults(uintptr_t gicd_base)
void gicv3_spis_config_defaults(uintptr_t gicd_base)
{
unsigned int index, num_ints;
@ -375,7 +375,7 @@ void gicv3_spis_configure_defaults(uintptr_t gicd_base)
/*******************************************************************************
* Helper function to configure secure G0 and G1S SPIs.
******************************************************************************/
void gicv3_secure_spis_configure(uintptr_t gicd_base,
void gicv3_secure_spis_config(uintptr_t gicd_base,
unsigned int num_ints,
const unsigned int *sec_intr_list,
unsigned int int_grp)
@ -423,7 +423,7 @@ void gicv3_secure_spis_configure(uintptr_t gicd_base,
/*******************************************************************************
* Helper function to configure properties of secure SPIs
******************************************************************************/
unsigned int gicv3_secure_spis_configure_props(uintptr_t gicd_base,
unsigned int gicv3_secure_spis_config_props(uintptr_t gicd_base,
const interrupt_prop_t *interrupt_props,
unsigned int interrupt_props_num)
{
@ -478,7 +478,7 @@ unsigned int gicv3_secure_spis_configure_props(uintptr_t gicd_base,
/*******************************************************************************
* Helper function to configure the default attributes of SPIs.
******************************************************************************/
void gicv3_ppi_sgi_configure_defaults(uintptr_t gicr_base)
void gicv3_ppi_sgi_config_defaults(uintptr_t gicr_base)
{
unsigned int index;
@ -507,7 +507,7 @@ void gicv3_ppi_sgi_configure_defaults(uintptr_t gicr_base)
/*******************************************************************************
* Helper function to configure secure G0 and G1S SPIs.
******************************************************************************/
void gicv3_secure_ppi_sgi_configure(uintptr_t gicr_base,
void gicv3_secure_ppi_sgi_config(uintptr_t gicr_base,
unsigned int num_ints,
const unsigned int *sec_intr_list,
unsigned int int_grp)
@ -546,7 +546,7 @@ void gicv3_secure_ppi_sgi_configure(uintptr_t gicr_base,
/*******************************************************************************
* Helper function to configure properties of secure G0 and G1S PPIs and SGIs.
******************************************************************************/
unsigned int gicv3_secure_ppi_sgi_configure_props(uintptr_t gicr_base,
unsigned int gicv3_secure_ppi_sgi_config_props(uintptr_t gicr_base,
const interrupt_prop_t *interrupt_props,
unsigned int interrupt_props_num)
{

16
drivers/arm/gic/v3/gicv3_main.c
View File

@ -190,12 +190,12 @@ void gicv3_distif_init(void)
CTLR_ARE_S_BIT | CTLR_ARE_NS_BIT, RWP_TRUE);
/* Set the default attribute of all SPIs */
gicv3_spis_configure_defaults(gicv3_driver_data->gicd_base);
gicv3_spis_config_defaults(gicv3_driver_data->gicd_base);
#if !ERROR_DEPRECATED
if (gicv3_driver_data->interrupt_props != NULL) {
#endif
bitmap = gicv3_secure_spis_configure_props(
bitmap = gicv3_secure_spis_config_props(
gicv3_driver_data->gicd_base,
gicv3_driver_data->interrupt_props,
gicv3_driver_data->interrupt_props_num);
@ -213,7 +213,7 @@ void gicv3_distif_init(void)
/* Configure the G1S SPIs */
if (gicv3_driver_data->g1s_interrupt_array) {
gicv3_secure_spis_configure(gicv3_driver_data->gicd_base,
gicv3_secure_spis_config(gicv3_driver_data->gicd_base,
gicv3_driver_data->g1s_interrupt_num,
gicv3_driver_data->g1s_interrupt_array,
INTR_GROUP1S);
@ -222,7 +222,7 @@ void gicv3_distif_init(void)
/* Configure the G0 SPIs */
if (gicv3_driver_data->g0_interrupt_array) {
gicv3_secure_spis_configure(gicv3_driver_data->gicd_base,
gicv3_secure_spis_config(gicv3_driver_data->gicd_base,
gicv3_driver_data->g0_interrupt_num,
gicv3_driver_data->g0_interrupt_array,
INTR_GROUP0);
@ -263,12 +263,12 @@ void gicv3_rdistif_init(unsigned int proc_num)
gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num];
/* Set the default attribute of all SGIs and PPIs */
gicv3_ppi_sgi_configure_defaults(gicr_base);
gicv3_ppi_sgi_config_defaults(gicr_base);
#if !ERROR_DEPRECATED
if (gicv3_driver_data->interrupt_props != NULL) {
#endif
bitmap = gicv3_secure_ppi_sgi_configure_props(gicr_base,
bitmap = gicv3_secure_ppi_sgi_config_props(gicr_base,
gicv3_driver_data->interrupt_props,
gicv3_driver_data->interrupt_props_num);
#if !ERROR_DEPRECATED
@ -285,7 +285,7 @@ void gicv3_rdistif_init(unsigned int proc_num)
/* Configure the G1S SGIs/PPIs */
if (gicv3_driver_data->g1s_interrupt_array) {
gicv3_secure_ppi_sgi_configure(gicr_base,
gicv3_secure_ppi_sgi_config(gicr_base,
gicv3_driver_data->g1s_interrupt_num,
gicv3_driver_data->g1s_interrupt_array,
INTR_GROUP1S);
@ -294,7 +294,7 @@ void gicv3_rdistif_init(unsigned int proc_num)
/* Configure the G0 SGIs/PPIs */
if (gicv3_driver_data->g0_interrupt_array) {
gicv3_secure_ppi_sgi_configure(gicr_base,
gicv3_secure_ppi_sgi_config(gicr_base,
gicv3_driver_data->g0_interrupt_num,
gicv3_driver_data->g0_interrupt_array,
INTR_GROUP0);

26
drivers/arm/gic/v3/gicv3_private.h
View File

@ -27,20 +27,20 @@
* GICD_IROUTER. Bits[31:24] in the MPIDR are cleared as they are not relevant
* to GICv3.
*/
#define gicd_irouter_val_from_mpidr(mpidr, irm) \
((mpidr & ~(0xff << 24)) | \
(irm & IROUTER_IRM_MASK) << IROUTER_IRM_SHIFT)
#define gicd_irouter_val_from_mpidr(_mpidr, _irm) \
((_mpidr & ~(0xff << 24)) | \
(_irm & IROUTER_IRM_MASK) << IROUTER_IRM_SHIFT)
/*
* Macro to convert a GICR_TYPER affinity value into a MPIDR value. Bits[31:24]
* are zeroes.
*/
#ifdef AARCH32
#define mpidr_from_gicr_typer(typer_val) (((typer_val) >> 32) & 0xffffff)
#define mpidr_from_gicr_typer(_typer_val) (((_typer_val) >> 32) & 0xffffff)
#else
#define mpidr_from_gicr_typer(typer_val) \
(((((typer_val) >> 56) & MPIDR_AFFLVL_MASK) << MPIDR_AFF3_SHIFT) | \
(((typer_val) >> 32) & 0xffffff))
#define mpidr_from_gicr_typer(_typer_val) \
(((((_typer_val) >> 56) & MPIDR_AFFLVL_MASK) << MPIDR_AFF3_SHIFT) | \
(((_typer_val) >> 32) & 0xffffff))
#endif
/*******************************************************************************
@ -85,22 +85,22 @@ void gicr_set_icfgr1(uintptr_t base, unsigned int id, unsigned int cfg);
/*******************************************************************************
* Private GICv3 helper function prototypes
******************************************************************************/
void gicv3_spis_configure_defaults(uintptr_t gicd_base);
void gicv3_ppi_sgi_configure_defaults(uintptr_t gicr_base);
void gicv3_spis_config_defaults(uintptr_t gicd_base);
void gicv3_ppi_sgi_config_defaults(uintptr_t gicr_base);
#if !ERROR_DEPRECATED
void gicv3_secure_spis_configure(uintptr_t gicd_base,
void gicv3_secure_spis_config(uintptr_t gicd_base,
unsigned int num_ints,
const unsigned int *sec_intr_list,
unsigned int int_grp);
void gicv3_secure_ppi_sgi_configure(uintptr_t gicr_base,
void gicv3_secure_ppi_sgi_config(uintptr_t gicr_base,
unsigned int num_ints,
const unsigned int *sec_intr_list,
unsigned int int_grp);
#endif
unsigned int gicv3_secure_ppi_sgi_configure_props(uintptr_t gicr_base,
unsigned int gicv3_secure_ppi_sgi_config_props(uintptr_t gicr_base,
const interrupt_prop_t *interrupt_props,
unsigned int interrupt_props_num);
unsigned int gicv3_secure_spis_configure_props(uintptr_t gicd_base,
unsigned int gicv3_secure_spis_config_props(uintptr_t gicd_base,
const interrupt_prop_t *interrupt_props,
unsigned int interrupt_props_num);
void gicv3_rdistif_base_addrs_probe(uintptr_t *rdistif_base_addrs,

4
drivers/arm/smmu/smmu_v3.c
View File

@ -8,8 +8,8 @@
#include <smmu_v3.h>
/* Test for pending invalidate */
#define INVAL_PENDING(base) \
smmuv3_read_s_init(base) & SMMU_S_INIT_INV_ALL_MASK
#define INVAL_PENDING(_base) \
smmuv3_read_s_init(_base) & SMMU_S_INIT_INV_ALL_MASK
static inline uint32_t smmuv3_read_s_idr1(uintptr_t base)
{

2
drivers/arm/tzc/tzc400.c
View File

@ -54,7 +54,7 @@ static inline void _tzc400_write_gate_keeper(uintptr_t base, unsigned int val)
/*
* Get the open status information for all filter units.
*/
#define get_gate_keeper_os(base) ((_tzc400_read_gate_keeper(base) >> \
#define get_gate_keeper_os(_base) ((_tzc400_read_gate_keeper(_base) >> \
GATE_KEEPER_OS_SHIFT) & \
GATE_KEEPER_OS_MASK)

2
include/common/bl_common.h
View File

@ -207,7 +207,7 @@ typedef struct bl31_params {
/*******************************************************************************
* Function & variable prototypes
******************************************************************************/
size_t image_size(unsigned int image_id);
size_t get_image_size(unsigned int image_id);
int is_mem_free(uintptr_t free_base, size_t free_size,
uintptr_t addr, size_t size);

6
include/lib/xlat_tables/aarch32/xlat_tables_aarch32.h
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -66,7 +66,7 @@
* valid. Therefore, the caller is expected to check it is the case using the
* CHECK_VIRT_ADDR_SPACE_SIZE() macro first.
*/
#define GET_XLAT_TABLE_LEVEL_BASE(virt_addr_space_size) \
(((virt_addr_space_size) > (ULL(1) << L1_XLAT_ADDRESS_SHIFT)) ? 1 : 2)
#define GET_XLAT_TABLE_LEVEL_BASE(_virt_addr_space_size) \
(((_virt_addr_space_size) > (ULL(1) << L1_XLAT_ADDRESS_SHIFT)) ? 1 : 2)
#endif /* __XLAT_TABLES_AARCH32_H__ */

8
include/lib/xlat_tables/aarch64/xlat_tables_aarch64.h
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -74,10 +74,10 @@ unsigned long long tcr_physical_addr_size_bits(unsigned long long max_addr);
* valid. Therefore, the caller is expected to check it is the case using the
* CHECK_VIRT_ADDR_SPACE_SIZE() macro first.
*/
#define GET_XLAT_TABLE_LEVEL_BASE(virt_addr_space_size) \
(((virt_addr_space_size) > (ULL(1) << L0_XLAT_ADDRESS_SHIFT)) \
#define GET_XLAT_TABLE_LEVEL_BASE(_virt_addr_space_size) \
(((_virt_addr_space_size) > (ULL(1) << L0_XLAT_ADDRESS_SHIFT)) \
? 0 \
: (((virt_addr_space_size) > (ULL(1) << L1_XLAT_ADDRESS_SHIFT)) \
: (((_virt_addr_space_size) > (ULL(1) << L1_XLAT_ADDRESS_SHIFT)) \
? 1 : 2))
#endif /* __XLAT_TABLES_AARCH64_H__ */

8
lib/cpus/aarch64/cpuamu.c
View File

@ -10,12 +10,12 @@
#define CPUAMU_NR_COUNTERS 5U
struct amu_ctx {
struct cpuamu_ctx {
uint64_t cnts[CPUAMU_NR_COUNTERS];
unsigned int mask;
};
static struct amu_ctx amu_ctxs[PLATFORM_CORE_COUNT];
static struct cpuamu_ctx cpuamu_ctxs[PLATFORM_CORE_COUNT];
int midr_match(unsigned int cpu_midr)
{
@ -29,7 +29,7 @@ int midr_match(unsigned int cpu_midr)
void cpuamu_context_save(unsigned int nr_counters)
{
struct amu_ctx *ctx = &amu_ctxs[plat_my_core_pos()];
struct cpuamu_ctx *ctx = &cpuamu_ctxs[plat_my_core_pos()];
unsigned int i;
assert(nr_counters <= CPUAMU_NR_COUNTERS);
@ -48,7 +48,7 @@ void cpuamu_context_save(unsigned int nr_counters)
void cpuamu_context_restore(unsigned int nr_counters)
{
struct amu_ctx *ctx = &amu_ctxs[plat_my_core_pos()];
struct cpuamu_ctx *ctx = &cpuamu_ctxs[plat_my_core_pos()];
unsigned int i;
assert(nr_counters <= CPUAMU_NR_COUNTERS);

6
lib/locks/bakery/bakery_lock_coherent.c
View File

@ -34,9 +34,9 @@
* accesses regardless of status of address translation.
*/
#define assert_bakery_entry_valid(entry, bakery) do { \
assert(bakery); \
assert(entry < BAKERY_LOCK_MAX_CPUS); \
#define assert_bakery_entry_valid(_entry, _bakery) do { \
assert(_bakery); \
assert(_entry < BAKERY_LOCK_MAX_CPUS); \
} while (0)
/* Obtain a ticket for a given CPU */

14
lib/locks/bakery/bakery_lock_normal.c
View File

@ -53,18 +53,18 @@ CASSERT((PLAT_PERCPU_BAKERY_LOCK_SIZE & (CACHE_WRITEBACK_GRANULE - 1)) == 0, \
IMPORT_SYM(uintptr_t, __PERCPU_BAKERY_LOCK_SIZE__, PERCPU_BAKERY_LOCK_SIZE);
#endif
#define get_bakery_info(cpu_ix, lock) \
(bakery_info_t *)((uintptr_t)lock + cpu_ix * PERCPU_BAKERY_LOCK_SIZE)
#define get_bakery_info(_cpu_ix, _lock) \
(bakery_info_t *)((uintptr_t)_lock + _cpu_ix * PERCPU_BAKERY_LOCK_SIZE)
#define write_cache_op(addr, cached) \
#define write_cache_op(_addr, _cached) \
do { \
(cached ? dccvac((uintptr_t)addr) :\
dcivac((uintptr_t)addr));\
(_cached ? dccvac((uintptr_t)_addr) :\
dcivac((uintptr_t)_addr));\
dsbish();\
} while (0)
#define read_cache_op(addr, cached) if (cached) \
dccivac((uintptr_t)addr)
#define read_cache_op(_addr, _cached) if (_cached) \
dccivac((uintptr_t)_addr)
/* Helper function to check if the lock is acquired */
static inline int is_lock_acquired(const bakery_info_t *my_bakery_info,

48
lib/optee/optee_utils.c
View File

@ -43,7 +43,7 @@ typedef struct optee_header {
uint8_t arch;
uint16_t flags;
uint32_t nb_images;
optee_image_t optee_image[];
optee_image_t optee_image_list[];
} optee_header_t;
/*******************************************************************************
@ -51,11 +51,11 @@ typedef struct optee_header {
* Return 1 if valid
* Return 0 if invalid
******************************************************************************/
static inline int tee_validate_header(optee_header_t *optee_header)
static inline int tee_validate_header(optee_header_t *header)
{
if ((optee_header->magic == TEE_MAGIC_NUM_OPTEE) &&
(optee_header->version == 2) &&
(optee_header->nb_images <= OPTEE_MAX_IMAGE_NUM)) {
if ((header->magic == TEE_MAGIC_NUM_OPTEE) &&
(header->version == 2) &&
(header->nb_images <= OPTEE_MAX_IMAGE_NUM)) {
return 1;
}
@ -68,14 +68,14 @@ static inline int tee_validate_header(optee_header_t *optee_header)
* Return 0 on success or a negative error code otherwise.
******************************************************************************/
static int parse_optee_image(image_info_t *image_info,
optee_image_t *optee_image)
optee_image_t *image)
{
uintptr_t init_load_addr, free_end, requested_end;
size_t init_size;
init_load_addr = ((uint64_t)optee_image->load_addr_hi << 32) |
optee_image->load_addr_lo;
init_size = optee_image->size;
init_load_addr = ((uint64_t)image->load_addr_hi << 32) |
image->load_addr_lo;
init_size = image->size;
/*
* -1 indicates loader decided address; take our pre-mapped area
@ -133,21 +133,21 @@ int parse_optee_header(entry_point_info_t *header_ep,
image_info_t *paged_image_info)
{
optee_header_t *optee_header;
optee_header_t *header;
int num, ret;
assert(header_ep);
optee_header = (optee_header_t *)header_ep->pc;
assert(optee_header);
header = (optee_header_t *)header_ep->pc;
assert(header);
/* Print the OPTEE header information */
INFO("OPTEE ep=0x%x\n", (unsigned int)header_ep->pc);
INFO("OPTEE header info:\n");
INFO(" magic=0x%x\n", optee_header->magic);
INFO(" version=0x%x\n", optee_header->version);
INFO(" arch=0x%x\n", optee_header->arch);
INFO(" flags=0x%x\n", optee_header->flags);
INFO(" nb_images=0x%x\n", optee_header->nb_images);
INFO(" magic=0x%x\n", header->magic);
INFO(" version=0x%x\n", header->version);
INFO(" arch=0x%x\n", header->arch);
INFO(" flags=0x%x\n", header->flags);
INFO(" nb_images=0x%x\n", header->nb_images);
/*
* OPTEE image has 3 types:
@ -166,7 +166,7 @@ int parse_optee_header(entry_point_info_t *header_ep,
* pager and pageable. Remove skip attr for BL32_EXTRA1_IMAGE_ID
* and BL32_EXTRA2_IMAGE_ID to load pager and paged bin.
*/
if (!tee_validate_header(optee_header)) {
if (!tee_validate_header(header)) {
INFO("Invalid OPTEE header, set legacy mode.\n");
#ifdef AARCH64
header_ep->args.arg0 = MODE_RW_64;
@ -177,15 +177,15 @@ int parse_optee_header(entry_point_info_t *header_ep,
}
/* Parse OPTEE image */
for (num = 0; num < optee_header->nb_images; num++) {
if (optee_header->optee_image[num].image_id ==
for (num = 0; num < header->nb_images; num++) {
if (header->optee_image_list[num].image_id ==
OPTEE_PAGER_IMAGE_ID) {
ret = parse_optee_image(pager_image_info,
&optee_header->optee_image[num]);
} else if (optee_header->optee_image[num].image_id ==
&header->optee_image_list[num]);
} else if (header->optee_image_list[num].image_id ==
OPTEE_PAGED_IMAGE_ID) {
ret = parse_optee_image(paged_image_info,
&optee_header->optee_image[num]);
&header->optee_image_list[num]);
} else {
ERROR("Parse optee image failed.\n");
return -1;
@ -211,7 +211,7 @@ int parse_optee_header(entry_point_info_t *header_ep,
header_ep->args.arg2 = paged_image_info->image_size;
/* Set OPTEE runtime arch - aarch32/aarch64 */
if (optee_header->arch == 0) {
if (header->arch == 0) {
header_ep->args.arg0 = MODE_RW_32;
} else {
#ifdef AARCH64

38
lib/psci/psci_private.h
View File

@ -65,8 +65,8 @@
#endif
#define psci_lock_init(non_cpu_pd_node, idx) \
((non_cpu_pd_node)[(idx)].lock_index = (idx))
#define psci_lock_init(_non_cpu_pd_node, _idx) \
((_non_cpu_pd_node)[(_idx)].lock_index = (_idx))
/*
* The PSCI capability which are provided by the generic code but does not
@ -96,35 +96,35 @@
/*
* Helper macros to get/set the fields of PSCI per-cpu data.
*/
#define psci_set_aff_info_state(aff_state) \
set_cpu_data(psci_svc_cpu_data.aff_info_state, aff_state)
#define psci_set_aff_info_state(_aff_state) \
set_cpu_data(psci_svc_cpu_data.aff_info_state, _aff_state)
#define psci_get_aff_info_state() \
get_cpu_data(psci_svc_cpu_data.aff_info_state)
#define psci_get_aff_info_state_by_idx(idx) \
get_cpu_data_by_index(idx, psci_svc_cpu_data.aff_info_state)
#define psci_set_aff_info_state_by_idx(idx, aff_state) \
set_cpu_data_by_index(idx, psci_svc_cpu_data.aff_info_state,\
aff_state)
#define psci_get_aff_info_state_by_idx(_idx) \
get_cpu_data_by_index(_idx, psci_svc_cpu_data.aff_info_state)
#define psci_set_aff_info_state_by_idx(_idx, _aff_state) \
set_cpu_data_by_index(_idx, psci_svc_cpu_data.aff_info_state,\
_aff_state)
#define psci_get_suspend_pwrlvl() \
get_cpu_data(psci_svc_cpu_data.target_pwrlvl)
#define psci_set_suspend_pwrlvl(target_lvl) \
set_cpu_data(psci_svc_cpu_data.target_pwrlvl, target_lvl)
#define psci_set_cpu_local_state(state) \
set_cpu_data(psci_svc_cpu_data.local_state, state)
#define psci_set_suspend_pwrlvl(_target_lvl) \
set_cpu_data(psci_svc_cpu_data.target_pwrlvl, _target_lvl)
#define psci_set_cpu_local_state(_state) \
set_cpu_data(psci_svc_cpu_data.local_state, _state)
#define psci_get_cpu_local_state() \
get_cpu_data(psci_svc_cpu_data.local_state)
#define psci_get_cpu_local_state_by_idx(idx) \
get_cpu_data_by_index(idx, psci_svc_cpu_data.local_state)
#define psci_get_cpu_local_state_by_idx(_idx) \
get_cpu_data_by_index(_idx, psci_svc_cpu_data.local_state)
/*
* Helper macros for the CPU level spinlocks
*/
#define psci_spin_lock_cpu(idx) spin_lock(&psci_cpu_pd_nodes[idx].cpu_lock)
#define psci_spin_unlock_cpu(idx) spin_unlock(&psci_cpu_pd_nodes[idx].cpu_lock)
#define psci_spin_lock_cpu(_idx) spin_lock(&psci_cpu_pd_nodes[_idx].cpu_lock)
#define psci_spin_unlock_cpu(_idx) spin_unlock(&psci_cpu_pd_nodes[_idx].cpu_lock)
/* Helper macro to identify a CPU standby request in PSCI Suspend call */
#define is_cpu_standby_req(is_power_down_state, retn_lvl) \
(((!(is_power_down_state)) && ((retn_lvl) == 0)) ? 1 : 0)
#define is_cpu_standby_req(_is_power_down_state, _retn_lvl) \
(((!(_is_power_down_state)) && ((_retn_lvl) == 0)) ? 1 : 0)
/*******************************************************************************
* The following two data structures implement the power domain tree. The tree

4
plat/arm/css/drivers/mhu/css_mhu_doorbell.h
View File

@ -18,8 +18,8 @@
#define MHU_V2_ACCESS_REQ_OFFSET 0xF88
#define MHU_V2_ACCESS_READY_OFFSET 0xF8C
#define SENDER_REG_STAT(CHANNEL) (0x20 * (CHANNEL))
#define SENDER_REG_SET(CHANNEL) (0x20 * (CHANNEL)) + 0xC
#define SENDER_REG_STAT(_channel) (0x20 * (_channel))
#define SENDER_REG_SET(_channel) ((0x20 * (_channel)) + 0xC)
/* Helper macro to ring doorbell */
#define MHU_RING_DOORBELL(addr, modify_mask, preserve_mask) do { \

12
plat/arm/css/drivers/scmi/scmi_private.h
View File

@ -60,14 +60,14 @@
* Helper macro to create an SCMI message header given protocol, message id
* and token.
*/
#define SCMI_MSG_CREATE(protocol, msg_id, token) \
((((protocol) & SCMI_MSG_PROTO_ID_MASK) << SCMI_MSG_PROTO_ID_SHIFT) | \
(((msg_id) & SCMI_MSG_ID_MASK) << SCMI_MSG_ID_SHIFT) | \
(((token) & SCMI_MSG_TOKEN_MASK) << SCMI_MSG_TOKEN_SHIFT))
#define SCMI_MSG_CREATE(_protocol, _msg_id, _token) \
((((_protocol) & SCMI_MSG_PROTO_ID_MASK) << SCMI_MSG_PROTO_ID_SHIFT) | \
(((_msg_id) & SCMI_MSG_ID_MASK) << SCMI_MSG_ID_SHIFT) | \
(((_token) & SCMI_MSG_TOKEN_MASK) << SCMI_MSG_TOKEN_SHIFT))
/* Helper macro to get the token from a SCMI message header */
#define SCMI_MSG_GET_TOKEN(msg) \
(((msg) >> SCMI_MSG_TOKEN_SHIFT) & SCMI_MSG_TOKEN_MASK)
#define SCMI_MSG_GET_TOKEN(_msg) \
(((_msg) >> SCMI_MSG_TOKEN_SHIFT) & SCMI_MSG_TOKEN_MASK)
/* SCMI Channel Status bit fields */
#define SCMI_CH_STATUS_RES0_MASK 0xFFFFFFFE

26
plat/arm/css/drivers/scp/css_pm_scmi.c
View File

@ -36,21 +36,21 @@
#define SCMI_PWR_STATE_MAX_PWR_LVL_WIDTH 4
#define SCMI_PWR_STATE_MAX_PWR_LVL_MASK \
((1 << SCMI_PWR_STATE_MAX_PWR_LVL_WIDTH) - 1)
#define SCMI_SET_PWR_STATE_MAX_PWR_LVL(pwr_state, max_lvl) \
(pwr_state) |= ((max_lvl) & SCMI_PWR_STATE_MAX_PWR_LVL_MASK) \
#define SCMI_SET_PWR_STATE_MAX_PWR_LVL(_power_state, _max_level) \
(_power_state) |= ((_max_level) & SCMI_PWR_STATE_MAX_PWR_LVL_MASK)\
<< SCMI_PWR_STATE_MAX_PWR_LVL_SHIFT
#define SCMI_GET_PWR_STATE_MAX_PWR_LVL(pwr_state) \
(((pwr_state) >> SCMI_PWR_STATE_MAX_PWR_LVL_SHIFT) \
#define SCMI_GET_PWR_STATE_MAX_PWR_LVL(_power_state) \
(((_power_state) >> SCMI_PWR_STATE_MAX_PWR_LVL_SHIFT) \
& SCMI_PWR_STATE_MAX_PWR_LVL_MASK)
#define SCMI_PWR_STATE_LVL_WIDTH 4
#define SCMI_PWR_STATE_LVL_MASK \
((1 << SCMI_PWR_STATE_LVL_WIDTH) - 1)
#define SCMI_SET_PWR_STATE_LVL(pwr_state, lvl, lvl_state) \
(pwr_state) |= ((lvl_state) & SCMI_PWR_STATE_LVL_MASK) \
<< (SCMI_PWR_STATE_LVL_WIDTH * (lvl))
#define SCMI_GET_PWR_STATE_LVL(pwr_state, lvl) \
(((pwr_state) >> (SCMI_PWR_STATE_LVL_WIDTH * (lvl))) & \
#define SCMI_SET_PWR_STATE_LVL(_power_state, _level, _level_state) \
(_power_state) |= ((_level_state) & SCMI_PWR_STATE_LVL_MASK) \
<< (SCMI_PWR_STATE_LVL_WIDTH * (_level))
#define SCMI_GET_PWR_STATE_LVL(_power_state, _level) \
(((_power_state) >> (SCMI_PWR_STATE_LVL_WIDTH * (_level))) & \
SCMI_PWR_STATE_LVL_MASK)
/*
@ -69,7 +69,7 @@ typedef enum {
static void *scmi_handle;
/* The SCMI channel global object */
static scmi_channel_t scmi_channel;
static scmi_channel_t channel;
ARM_INSTANTIATE_LOCK;
@ -308,9 +308,9 @@ scmi_channel_plat_info_t plat_css_scmi_plat_info = {
void plat_arm_pwrc_setup(void)
{
scmi_channel.info = &plat_css_scmi_plat_info;
scmi_channel.lock = ARM_LOCK_GET_INSTANCE;
scmi_handle = scmi_init(&scmi_channel);
channel.info = &plat_css_scmi_plat_info;
channel.lock = ARM_LOCK_GET_INSTANCE;
scmi_handle = scmi_init(&channel);
if (scmi_handle == NULL) {
ERROR("SCMI Initialization failed\n");
panic();

20
plat/arm/css/drivers/sds/sds_private.h
View File

@ -67,18 +67,18 @@ typedef struct structure_header {
uint32_t reg[2];
} struct_header_t;
#define GET_SDS_HEADER_ID(header) \
((((struct_header_t *)(header))->reg[0]) & SDS_HEADER_ID_MASK)
#define GET_SDS_HEADER_VERSION(header) \
(((((struct_header_t *)(header))->reg[0]) >> SDS_HEADER_MINOR_VERSION_SHIFT)\
#define GET_SDS_HEADER_ID(_header) \
((((struct_header_t *)(_header))->reg[0]) & SDS_HEADER_ID_MASK)
#define GET_SDS_HEADER_VERSION(_header) \
(((((struct_header_t *)(_header))->reg[0]) >> SDS_HEADER_MINOR_VERSION_SHIFT)\
& SDS_HEADER_VERSION_MASK)
#define GET_SDS_HEADER_STRUCT_SIZE(header) \
(((((struct_header_t *)(header))->reg[1]) >> SDS_HEADER_STRUCT_SIZE_SHIFT)\
#define GET_SDS_HEADER_STRUCT_SIZE(_header) \
(((((struct_header_t *)(_header))->reg[1]) >> SDS_HEADER_STRUCT_SIZE_SHIFT)\
& SDS_HEADER_STRUCT_SIZE_MASK)
#define IS_SDS_HEADER_VALID(header) \
((((struct_header_t *)(header))->reg[1]) & SDS_HEADER_VALID_MASK)
#define GET_SDS_STRUCT_FIELD(header, field_offset) \
((((uint8_t *)(header)) + sizeof(struct_header_t)) + (field_offset))
#define IS_SDS_HEADER_VALID(_header) \
((((struct_header_t *)(_header))->reg[1]) & SDS_HEADER_VALID_MASK)
#define GET_SDS_STRUCT_FIELD(_header, _field_offset) \
((((uint8_t *)(_header)) + sizeof(struct_header_t)) + (_field_offset))
/* Region Descriptor describing the SDS Memory Region */
typedef struct region_descriptor {

14
services/spd/opteed/opteed_main.c
View File

@ -34,7 +34,7 @@
* Address of the entrypoint vector table in OPTEE. It is
* initialised once on the primary core after a cold boot.
******************************************************************************/
optee_vectors_t *optee_vectors;
optee_vectors_t *optee_vector_table;
/*******************************************************************************
* Array to keep track of per-cpu OPTEE state
@ -71,7 +71,7 @@ static uint64_t opteed_sel1_interrupt_handler(uint32_t id,
optee_ctx = &opteed_sp_context[linear_id];
assert(&optee_ctx->cpu_ctx == cm_get_context(SECURE));
cm_set_elr_el3(SECURE, (uint64_t)&optee_vectors->fiq_entry);
cm_set_elr_el3(SECURE, (uint64_t)&optee_vector_table->fiq_entry);
cm_el1_sysregs_context_restore(SECURE);
cm_set_next_eret_context(SECURE);
@ -236,10 +236,10 @@ static uintptr_t opteed_smc_handler(uint32_t smc_fid,
*/
if (GET_SMC_TYPE(smc_fid) == SMC_TYPE_FAST) {
cm_set_elr_el3(SECURE, (uint64_t)
&optee_vectors->fast_smc_entry);
&optee_vector_table->fast_smc_entry);
} else {
cm_set_elr_el3(SECURE, (uint64_t)
&optee_vectors->yield_smc_entry);
&optee_vector_table->yield_smc_entry);
}
cm_el1_sysregs_context_restore(SECURE);
@ -279,10 +279,10 @@ static uintptr_t opteed_smc_handler(uint32_t smc_fid,
* Stash the OPTEE entry points information. This is done
* only once on the primary cpu
*/
assert(optee_vectors == NULL);
optee_vectors = (optee_vectors_t *) x1;
assert(optee_vector_table == NULL);
optee_vector_table = (optee_vectors_t *) x1;
if (optee_vectors) {
if (optee_vector_table) {
set_optee_pstate(optee_ctx->state, OPTEE_PSTATE_ON);
/*

24
services/spd/opteed/opteed_pm.c
View File

@ -30,11 +30,11 @@ static int32_t opteed_cpu_off_handler(u_register_t unused)
uint32_t linear_id = plat_my_core_pos();
optee_context_t *optee_ctx = &opteed_sp_context[linear_id];
assert(optee_vectors);
assert(optee_vector_table);
assert(get_optee_pstate(optee_ctx->state) == OPTEE_PSTATE_ON);
/* Program the entry point and enter OPTEE */
cm_set_elr_el3(SECURE, (uint64_t) &optee_vectors->cpu_off_entry);
cm_set_elr_el3(SECURE, (uint64_t) &optee_vector_table->cpu_off_entry);
rc = opteed_synchronous_sp_entry(optee_ctx);
/*
@ -63,11 +63,11 @@ static void opteed_cpu_suspend_handler(u_register_t max_off_pwrlvl)
uint32_t linear_id = plat_my_core_pos();
optee_context_t *optee_ctx = &opteed_sp_context[linear_id];
assert(optee_vectors);
assert(optee_vector_table);
assert(get_optee_pstate(optee_ctx->state) == OPTEE_PSTATE_ON);
/* Program the entry point and enter OPTEE */
cm_set_elr_el3(SECURE, (uint64_t) &optee_vectors->cpu_suspend_entry);
cm_set_elr_el3(SECURE, (uint64_t) &optee_vector_table->cpu_suspend_entry);
rc = opteed_synchronous_sp_entry(optee_ctx);
/*
@ -94,11 +94,11 @@ static void opteed_cpu_on_finish_handler(u_register_t unused)
optee_context_t *optee_ctx = &opteed_sp_context[linear_id];
entry_point_info_t optee_on_entrypoint;
assert(optee_vectors);
assert(optee_vector_table);
assert(get_optee_pstate(optee_ctx->state) == OPTEE_PSTATE_OFF);
opteed_init_optee_ep_state(&optee_on_entrypoint, opteed_rw,
(uint64_t)&optee_vectors->cpu_on_entry,
(uint64_t)&optee_vector_table->cpu_on_entry,
0, 0, 0, optee_ctx);
/* Initialise this cpu's secure context */
@ -129,14 +129,14 @@ static void opteed_cpu_suspend_finish_handler(u_register_t max_off_pwrlvl)
uint32_t linear_id = plat_my_core_pos();
optee_context_t *optee_ctx = &opteed_sp_context[linear_id];
assert(optee_vectors);
assert(optee_vector_table);
assert(get_optee_pstate(optee_ctx->state) == OPTEE_PSTATE_SUSPEND);
/* Program the entry point, max_off_pwrlvl and enter the SP */
write_ctx_reg(get_gpregs_ctx(&optee_ctx->cpu_ctx),
CTX_GPREG_X0,
max_off_pwrlvl);
cm_set_elr_el3(SECURE, (uint64_t) &optee_vectors->cpu_resume_entry);
cm_set_elr_el3(SECURE, (uint64_t) &optee_vector_table->cpu_resume_entry);
rc = opteed_synchronous_sp_entry(optee_ctx);
/*
@ -168,11 +168,11 @@ static void opteed_system_off(void)
uint32_t linear_id = plat_my_core_pos();
optee_context_t *optee_ctx = &opteed_sp_context[linear_id];
assert(optee_vectors);
assert(optee_vector_table);
assert(get_optee_pstate(optee_ctx->state) == OPTEE_PSTATE_ON);
/* Program the entry point */
cm_set_elr_el3(SECURE, (uint64_t) &optee_vectors->system_off_entry);
cm_set_elr_el3(SECURE, (uint64_t) &optee_vector_table->system_off_entry);
/* Enter OPTEE. We do not care about the return value because we
* must continue the shutdown anyway */
@ -188,11 +188,11 @@ static void opteed_system_reset(void)
uint32_t linear_id = plat_my_core_pos();
optee_context_t *optee_ctx = &opteed_sp_context[linear_id];
assert(optee_vectors);
assert(optee_vector_table);
assert(get_optee_pstate(optee_ctx->state) == OPTEE_PSTATE_ON);
/* Program the entry point */
cm_set_elr_el3(SECURE, (uint64_t) &optee_vectors->system_reset_entry);
cm_set_elr_el3(SECURE, (uint64_t) &optee_vector_table->system_reset_entry);
/* Enter OPTEE. We do not care about the return value because we
* must continue the reset anyway */

2
services/spd/opteed/opteed_private.h
View File

@ -154,7 +154,7 @@ void opteed_init_optee_ep_state(struct entry_point_info *optee_ep,
extern optee_context_t opteed_sp_context[OPTEED_CORE_COUNT];
extern uint32_t opteed_rw;
extern struct optee_vectors *optee_vectors;
extern struct optee_vectors *optee_vector_table;
#endif /*__ASSEMBLY__*/
#endif /* __OPTEED_PRIVATE_H__ */

12
services/spd/tspd/tspd_private.h
View File

@ -190,14 +190,14 @@ typedef struct tsp_context {
} tsp_context_t;
/* Helper macros to store and retrieve tsp args from tsp_context */
#define store_tsp_args(tsp_ctx, x1, x2) do {\
tsp_ctx->saved_tsp_args[0] = x1;\
tsp_ctx->saved_tsp_args[1] = x2;\
#define store_tsp_args(_tsp_ctx, _x1, _x2) do {\
_tsp_ctx->saved_tsp_args[0] = _x1;\
_tsp_ctx->saved_tsp_args[1] = _x2;\
} while (0)
#define get_tsp_args(tsp_ctx, x1, x2) do {\
x1 = tsp_ctx->saved_tsp_args[0];\
x2 = tsp_ctx->saved_tsp_args[1];\
#define get_tsp_args(_tsp_ctx, _x1, _x2) do {\
_x1 = _tsp_ctx->saved_tsp_args[0];\
_x2 = _tsp_ctx->saved_tsp_args[1];\
} while (0)
/* TSPD power management handlers */