From 74cf2158ca6195cb8f9fa4a784e60b95935291a1 Mon Sep 17 00:00:00 2001 From: Rajan Vaja Date: Fri, 15 Mar 2019 14:19:26 +0530 Subject: [PATCH] zynqmp: pm: clock: Move custom flags to typeflags Linux expects custom flags in type flags. So move custom flags to type flags instead of providing them to clock core flags. Signed-off-by: Rajan Vaja Signed-off-by: Jolly Shah Change-Id: I668a8084d966815a9d9e86c2b18ecb5b18cb6b78 --- plat/xilinx/zynqmp/pm_service/pm_api_clock.c | 15 ++++++++------- plat/xilinx/zynqmp/pm_service/pm_api_clock.h | 2 +- 2 files changed, 9 insertions(+), 8 deletions(-) diff --git a/plat/xilinx/zynqmp/pm_service/pm_api_clock.c b/plat/xilinx/zynqmp/pm_service/pm_api_clock.c index d57def823..0ba8e34bc 100644 --- a/plat/xilinx/zynqmp/pm_service/pm_api_clock.c +++ b/plat/xilinx/zynqmp/pm_service/pm_api_clock.c @@ -368,9 +368,8 @@ static struct pm_clock_node dp_audio_video_ref_nodes[] = { .offset = PERIPH_MUX_SHIFT, .width = PERIPH_MUX_WIDTH, .clkflags = CLK_SET_RATE_NO_REPARENT | - CLK_SET_RATE_PARENT | - CLK_FRAC | CLK_IS_BASIC, - .typeflags = NA_TYPE_FLAGS, + CLK_SET_RATE_PARENT | CLK_IS_BASIC, + .typeflags = CLK_FRAC, .mult = NA_MULT, .div = NA_DIV, }, @@ -379,8 +378,9 @@ static struct pm_clock_node dp_audio_video_ref_nodes[] = { .offset = PERIPH_DIV1_SHIFT, .width = PERIPH_DIV1_WIDTH, .clkflags = CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT | - CLK_FRAC | CLK_IS_BASIC, - .typeflags = CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, + CLK_IS_BASIC, + .typeflags = CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO | + CLK_FRAC, .mult = NA_MULT, .div = NA_DIV, }, @@ -389,8 +389,9 @@ static struct pm_clock_node dp_audio_video_ref_nodes[] = { .offset = PERIPH_DIV2_SHIFT, .width = PERIPH_DIV2_WIDTH, .clkflags = CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT | - CLK_FRAC | CLK_IS_BASIC, - .typeflags = CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, + CLK_IS_BASIC, + .typeflags = CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO | + CLK_FRAC, .mult = NA_MULT, .div = NA_DIV, }, diff --git a/plat/xilinx/zynqmp/pm_service/pm_api_clock.h b/plat/xilinx/zynqmp/pm_service/pm_api_clock.h index 5bed5a617..48f5a5ec4 100644 --- a/plat/xilinx/zynqmp/pm_service/pm_api_clock.h +++ b/plat/xilinx/zynqmp/pm_service/pm_api_clock.h @@ -43,7 +43,6 @@ #define CLK_IS_CRITICAL BIT(11) /* do not gate, ever */ /* parents need enable during gate/ungate, set rate and re-parent */ #define CLK_OPS_PARENT_ENABLE BIT(12) -#define CLK_FRAC BIT(13) #define CLK_DIVIDER_ONE_BASED BIT(0) #define CLK_DIVIDER_POWER_OF_TWO BIT(1) @@ -52,6 +51,7 @@ #define CLK_DIVIDER_ROUND_CLOSEST BIT(4) #define CLK_DIVIDER_READ_ONLY BIT(5) #define CLK_DIVIDER_MAX_AT_ZERO BIT(6) +#define CLK_FRAC BIT(8) #define END_OF_CLK "END_OF_CLK"