Merge "FVP: Remove GIC initialisation from secondary core cold boot" into integration
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commit
74eaf2666d
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -16,14 +16,6 @@
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.globl plat_is_my_cpu_primary
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.globl plat_arm_calc_core_pos
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.macro fvp_choose_gicmmap param1, param2, x_tmp, w_tmp, res
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mov_imm \x_tmp, V2M_SYSREGS_BASE + V2M_SYS_ID
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ldr \w_tmp, [\x_tmp]
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ubfx \w_tmp, \w_tmp, #V2M_SYS_ID_BLD_SHIFT, #V2M_SYS_ID_BLD_LENGTH
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cmp \w_tmp, #BLD_GIC_VE_MMAP
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csel \res, \param1, \param2, eq
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.endm
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/* -----------------------------------------------------
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* void plat_secondary_cold_boot_setup (void);
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*
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@ -49,35 +41,6 @@ func plat_secondary_cold_boot_setup
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mov_imm x1, PWRC_BASE
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str w0, [x1, #PPOFFR_OFF]
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/* ---------------------------------------------
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* Disable GIC bypass as well
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* ---------------------------------------------
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*/
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/* Check for GICv3 system register access */
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mrs x0, id_aa64pfr0_el1
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ubfx x0, x0, #ID_AA64PFR0_GIC_SHIFT, #ID_AA64PFR0_GIC_WIDTH
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cmp x0, #1
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b.ne gicv2_bypass_disable
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/* Check for SRE enable */
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mrs x1, ICC_SRE_EL3
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tst x1, #ICC_SRE_SRE_BIT
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b.eq gicv2_bypass_disable
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mrs x2, ICC_SRE_EL3
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orr x2, x2, #(ICC_SRE_DIB_BIT | ICC_SRE_DFB_BIT)
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msr ICC_SRE_EL3, x2
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b secondary_cold_boot_wait
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gicv2_bypass_disable:
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mov_imm x0, VE_GICC_BASE
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mov_imm x1, BASE_GICC_BASE
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fvp_choose_gicmmap x0, x1, x2, w2, x1
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mov w0, #(IRQ_BYP_DIS_GRP1 | FIQ_BYP_DIS_GRP1)
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orr w0, w0, #(IRQ_BYP_DIS_GRP0 | FIQ_BYP_DIS_GRP0)
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str w0, [x1, #GICC_CTLR]
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secondary_cold_boot_wait:
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/* ---------------------------------------------
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* There is no sane reason to come out of this
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* wfi so panic if we do. This cpu will be pow-
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