From c4187c9c4b352f48252afe0ee30fa93d84e692a5 Mon Sep 17 00:00:00 2001
From: John Tsichritzis <john.tsichritzis@arm.com>
Date: Fri, 15 Mar 2019 15:40:27 +0000
Subject: [PATCH] Fix wrong MIDR_EL1 value for Neoverse E1

Change-Id: I75ee39d78c81ecb528a671c0cfadfc2fe7b5d818
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
---
 include/lib/cpus/aarch64/neoverse_e1.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/include/lib/cpus/aarch64/neoverse_e1.h b/include/lib/cpus/aarch64/neoverse_e1.h
index 708460480..96b4661db 100644
--- a/include/lib/cpus/aarch64/neoverse_e1.h
+++ b/include/lib/cpus/aarch64/neoverse_e1.h
@@ -9,7 +9,7 @@
 
 #include <lib/utils_def.h>
 
-#define NEOVERSE_E1_MIDR		U(0x410FD060)
+#define NEOVERSE_E1_MIDR		U(0x410FD4A0)
 
 /*******************************************************************************
  * CPU Extended Control register specific definitions.