Tegra: read-modify-write ACTLR_ELx registers
This patch changes direct writes to ACTLR_ELx registers to use read-modify-write instead. Change-Id: I6e0eaa6974583f3035cb3724088f3f1c849da229 Signed-off-by: Steven Kao <skao@nvidia.com>
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@ -18,16 +18,21 @@
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/*******************************************************************************
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* Implementation defined ACTLR_EL3 bit definitions
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******************************************************************************/
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#define ACTLR_EL3_L2ACTLR_BIT (1 << 6)
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#define ACTLR_EL3_L2ECTLR_BIT (1 << 5)
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#define ACTLR_EL3_L2CTLR_BIT (1 << 4)
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#define ACTLR_EL3_CPUECTLR_BIT (1 << 1)
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#define ACTLR_EL3_CPUACTLR_BIT (1 << 0)
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#define ACTLR_EL3_L2ACTLR_BIT (U(1) << 6)
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#define ACTLR_EL3_L2ECTLR_BIT (U(1) << 5)
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#define ACTLR_EL3_L2CTLR_BIT (U(1) << 4)
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#define ACTLR_EL3_CPUECTLR_BIT (U(1) << 1)
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#define ACTLR_EL3_CPUACTLR_BIT (U(1) << 0)
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#define ACTLR_EL3_ENABLE_ALL_MASK (ACTLR_EL3_L2ACTLR_BIT | \
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ACTLR_EL3_L2ECTLR_BIT | \
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ACTLR_EL3_L2CTLR_BIT | \
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ACTLR_EL3_CPUECTLR_BIT | \
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ACTLR_EL3_CPUACTLR_BIT)
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#define ACTLR_EL3_ENABLE_ALL_ACCESS (ACTLR_EL3_L2ACTLR_BIT | \
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ACTLR_EL3_L2ECTLR_BIT | \
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ACTLR_EL3_L2CTLR_BIT | \
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ACTLR_EL3_CPUECTLR_BIT | \
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ACTLR_EL3_CPUACTLR_BIT)
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ACTLR_EL3_L2ECTLR_BIT | \
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ACTLR_EL3_L2CTLR_BIT | \
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ACTLR_EL3_CPUECTLR_BIT | \
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ACTLR_EL3_CPUACTLR_BIT)
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/* Global functions */
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.globl plat_is_my_cpu_primary
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@ -87,8 +92,17 @@
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* Enable L2 and CPU ECTLR RW access from non-secure world
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* -------------------------------------------------------
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*/
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mov x0, #ACTLR_EL3_ENABLE_ALL_ACCESS
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mrs x0, actlr_el3
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mov x1, #ACTLR_EL3_ENABLE_ALL_MASK
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bic x0, x0, x1
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mov x1, #ACTLR_EL3_ENABLE_ALL_ACCESS
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orr x0, x0, x1
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msr actlr_el3, x0
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mrs x0, actlr_el2
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mov x1, #ACTLR_EL3_ENABLE_ALL_MASK
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bic x0, x0, x1
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mov x1, #ACTLR_EL3_ENABLE_ALL_ACCESS
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orr x0, x0, x1
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msr actlr_el2, x0
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isb
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@ -22,6 +22,16 @@
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#define TEGRA_DRAM_BASE ULL(0x80000000)
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#define TEGRA_DRAM_END ULL(0x27FFFFFFF)
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/*******************************************************************************
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* Implementation defined ACTLR_EL1 bit definitions
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******************************************************************************/
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#define ACTLR_EL1_PMSTATE_MASK (ULL(0xF) << 0)
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/*******************************************************************************
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* Implementation defined ACTLR_EL2 bit definitions
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******************************************************************************/
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#define ACTLR_EL2_PMSTATE_MASK (ULL(0xF) << 0)
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/*******************************************************************************
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* Struct for parameters received from BL2
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******************************************************************************/
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@ -98,19 +98,24 @@ int tegra_soc_pwr_domain_on_finish(const psci_power_state_t *target_state)
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int tegra_soc_pwr_domain_off(const psci_power_state_t *target_state)
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{
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uint64_t val;
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tegra_fc_cpu_off(read_mpidr() & MPIDR_CPU_MASK);
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/* Disable DCO operations */
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denver_disable_dco();
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/* Power down the CPU */
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write_actlr_el1(DENVER_CPU_STATE_POWER_DOWN);
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val = read_actlr_el1() & ~ACTLR_EL1_PMSTATE_MASK;
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write_actlr_el1(val | DENVER_CPU_STATE_POWER_DOWN);
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return PSCI_E_SUCCESS;
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}
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int tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state)
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{
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uint64_t val;
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#if ENABLE_ASSERTIONS
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int cpu = read_mpidr() & MPIDR_CPU_MASK;
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@ -128,7 +133,8 @@ int tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state)
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denver_disable_dco();
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/* Program the suspend state ID */
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write_actlr_el1(target_state->pwr_domain_state[PLAT_MAX_PWR_LVL]);
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val = read_actlr_el1() & ~ACTLR_EL1_PMSTATE_MASK;
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write_actlr_el1(val | target_state->pwr_domain_state[PLAT_MAX_PWR_LVL]);
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return PSCI_E_SUCCESS;
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}
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@ -14,10 +14,12 @@
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#include <mce_private.h>
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#include <t18x_ari.h>
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#include <tegra_private.h>
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int32_t nvg_enter_cstate(uint32_t ari_base, uint32_t state, uint32_t wake_time)
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{
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int32_t ret = 0;
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uint64_t val = 0ULL;
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(void)ari_base;
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@ -31,7 +33,8 @@ int32_t nvg_enter_cstate(uint32_t ari_base, uint32_t state, uint32_t wake_time)
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nvg_set_request_data(TEGRA_NVG_CHANNEL_WAKE_TIME, wake_time);
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/* set the core cstate */
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write_actlr_el1(state);
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val = read_actlr_el1() & ~ACTLR_EL1_PMSTATE_MASK;
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write_actlr_el1(val | (uint64_t)state);
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}
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return ret;
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