Merge changes from topic "a5ds-multicore" into integration
* changes: a5ds: add multicore support a5ds: Hold the secondary cpus in pen rather than panic
This commit is contained in:
Soby Mathew
TrustedFirmware Code Review
commit
757d904b2f
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@ -12,14 +12,40 @@
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interrupt-parent = <&gic>;
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#address-cells = <1>;
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#size-cells = <1>;
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psci {
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compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci";
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method = "smc";
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cpu_on = <0x84000003>;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a5";
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enable-method = "psci";
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reg = <0>;
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};
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cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a5";
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enable-method = "psci";
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reg = <1>;
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};
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cpu@2 {
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device_type = "cpu";
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compatible = "arm,cortex-a5";
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enable-method = "psci";
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reg = <2>;
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};
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cpu@3 {
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device_type = "cpu";
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compatible = "arm,cortex-a5";
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enable-method = "psci";
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reg = <3>;
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};
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};
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memory@80000000 {
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@ -6,6 +6,38 @@
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#include <lib/psci/psci.h>
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#include <plat/arm/common/plat_arm.h>
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#include <plat/common/platform.h>
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#include <drivers/arm/gicv2.h>
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/*******************************************************************************
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* Platform handler called when a power domain is about to be turned on. The
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* mpidr determines the CPU to be turned on.
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******************************************************************************/
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static int a5ds_pwr_domain_on(u_register_t mpidr)
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{
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unsigned int pos = plat_core_pos_by_mpidr(mpidr);
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uint64_t *hold_base = (uint64_t *)A5DS_HOLD_BASE;
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hold_base[pos] = A5DS_HOLD_STATE_GO;
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dsbish();
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sev();
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return PSCI_E_SUCCESS;
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}
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/*******************************************************************************
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* Platform handler called when a power domain has just been powered on after
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* being turned off earlier. The target_state encodes the low power state that
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* each level has woken up from.
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******************************************************************************/
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void a5ds_pwr_domain_on_finish(const psci_power_state_t *target_state)
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{
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/* TODO: This setup is needed only after a cold boot*/
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gicv2_pcpu_distif_init();
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/* Enable the gic cpu interface */
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gicv2_cpuif_enable();
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}
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/*******************************************************************************
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* Export the platform handlers via a5ds_psci_pm_ops. The ARM Standard
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@ -14,11 +46,16 @@
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plat_psci_ops_t a5ds_psci_pm_ops = {
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/* dummy struct */
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.validate_ns_entrypoint = NULL,
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.pwr_domain_on = a5ds_pwr_domain_on,
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.pwr_domain_on_finish = a5ds_pwr_domain_on_finish
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};
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int __init plat_setup_psci_ops(uintptr_t sec_entrypoint,
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const plat_psci_ops_t **psci_ops)
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{
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uintptr_t *mailbox = (void *)A5DS_TRUSTED_MAILBOX_BASE;
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*mailbox = sec_entrypoint;
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*psci_ops = &a5ds_psci_pm_ops;
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return 0;
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@ -12,17 +12,36 @@
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.globl plat_get_my_entrypoint
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.globl plat_is_my_cpu_primary
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/* --------------------------------------------------------------------
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/* -----------------------------------------------------
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* void plat_secondary_cold_boot_setup (void);
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*
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* For AArch32, cold-booting secondary CPUs is not yet
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* implemented and they panic.
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* --------------------------------------------------------------------
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* This function performs any platform specific actions
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* needed for a secondary cpu after a cold reset e.g
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* mark the cpu's presence, mechanism to place it in a
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* holding pen etc.
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* -----------------------------------------------------
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*/
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func plat_secondary_cold_boot_setup
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cb_panic:
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wfi
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b cb_panic
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/* Calculate address of our hold entry */
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bl plat_my_core_pos
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lsl r0, r0, #A5DS_HOLD_ENTRY_SHIFT
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mov_imm r2, A5DS_HOLD_BASE
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/* Clear the value stored in the hold address for the specific core */
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mov_imm r3, A5DS_HOLD_STATE_WAIT
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str r3, [r2, r0]
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dmb ish
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/* Wait until we have a go */
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poll_mailbox:
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ldr r1, [r2, r0]
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cmp r1, #A5DS_HOLD_STATE_WAIT
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beq 1f
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mov_imm r0, A5DS_TRUSTED_MAILBOX_BASE
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ldr r1, [r0]
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bx r1
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1:
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wfe
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b poll_mailbox
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endfunc plat_secondary_cold_boot_setup
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/* ---------------------------------------------------------------------
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@ -56,3 +75,52 @@ func plat_is_my_cpu_primary
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movne r0, #0
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bx lr
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endfunc plat_is_my_cpu_primary
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/* ---------------------------------------------------------------------
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* Loads MPIDR in r0 and calls plat_arm_calc_core_pos
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* ---------------------------------------------------------------------
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*/
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func plat_my_core_pos
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ldcopr r0, MPIDR
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b plat_arm_calc_core_pos
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endfunc plat_my_core_pos
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/* ---------------------------------------------------------------------
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* unsigned int plat_arm_calc_core_pos(u_register_t mpidr)
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*
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* Function to calculate the core position on A5DS.
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*
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* (ClusterId * A5DS_MAX_CPUS_PER_CLUSTER * A5DS_MAX_PE_PER_CPU) +
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* (CPUId * A5DS_MAX_PE_PER_CPU) +
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* ThreadId
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*
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* which can be simplified as:
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*
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* ((ClusterId * A5DS_MAX_CPUS_PER_CLUSTER + CPUId) * A5DS_MAX_PE_PER_CPU)
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* + ThreadId
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* ---------------------------------------------------------------------
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*/
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func plat_arm_calc_core_pos
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mov r3, r0
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/*
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* Check for MT bit in MPIDR. If not set, shift MPIDR to left to make it
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* look as if in a multi-threaded implementation
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*/
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tst r0, #MPIDR_MT_MASK
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lsleq r3, r0, #MPIDR_AFFINITY_BITS
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/* Extract individual affinity fields from MPIDR */
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ubfx r0, r3, #MPIDR_AFF0_SHIFT, #MPIDR_AFFINITY_BITS
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ubfx r1, r3, #MPIDR_AFF1_SHIFT, #MPIDR_AFFINITY_BITS
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ubfx r2, r3, #MPIDR_AFF2_SHIFT, #MPIDR_AFFINITY_BITS
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/* Compute linear position */
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mov r3, #A5DS_MAX_CPUS_PER_CLUSTER
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mla r1, r2, r3, r1
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mov r3, #A5DS_MAX_PE_PER_CPU
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mla r0, r1, r3, r0
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bx lr
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endfunc plat_arm_calc_core_pos
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@ -97,9 +97,9 @@
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/* Default number of threads per CPU on A5DS */
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#define A5DS_MAX_PE_PER_CPU 1
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#define A5DS_CORE_COUNT 1
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#define A5DS_CORE_COUNT 4
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#define A5DS_PRIMARY_CPU 0x0
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#define A5DS_PRIMARY_CPU 0x0
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#define FLASH1_BASE UL(0x8000000)
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#define FLASH1_SIZE UL(0x2800000)
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@ -229,11 +229,11 @@
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#define BL32_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE)
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/* Required platform porting definitions */
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#define PLATFORM_CORE_COUNT 1
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#define PLAT_NUM_PWR_DOMAINS (A5DS_CLUSTER_COUNT + \
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#define PLATFORM_CORE_COUNT A5DS_CORE_COUNT
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#define PLAT_NUM_PWR_DOMAINS (A5DS_CLUSTER_COUNT + \
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PLATFORM_CORE_COUNT) + 1
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#define PLAT_MAX_PWR_LVL 2
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#define PLAT_MAX_PWR_LVL 2
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/*
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* Other platform porting definitions are provided by included headers
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@ -325,6 +325,14 @@
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/* Mailbox base address */
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#define A5DS_TRUSTED_MAILBOX_BASE A5DS_SHARED_RAM_BASE
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#define A5DS_TRUSTED_MAILBOX_SIZE (8 + A5DS_HOLD_SIZE)
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#define A5DS_HOLD_BASE (A5DS_TRUSTED_MAILBOX_BASE + 8)
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#define A5DS_HOLD_SIZE (PLATFORM_CORE_COUNT * \
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A5DS_HOLD_ENTRY_SIZE)
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#define A5DS_HOLD_ENTRY_SHIFT 3
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#define A5DS_HOLD_ENTRY_SIZE (1 << A5DS_HOLD_ENTRY_SHIFT)
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#define A5DS_HOLD_STATE_WAIT 0
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#define A5DS_HOLD_STATE_GO 1
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/*
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* GIC related constants to cater for GICv2
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