feat(plat/imx/imx8m/imx8mp): add in BL2 with FIP
Adds bl2 with FIP to the build required for mbed Linux booting where we do: BootROM -> SPL -> BL2 -> OPTEE -> u-boot If NEED_BL2 is specified then BL2 will be built and BL31 will have its address range modified upwards to accommodate. BL31 must be loaded from a FIP in this case. If NEED_BL2 is not specified then the current BL31 boot flow is unaffected and u-boot SPL will load and execute BL31 directly. Signed-off-by: Ying-Chun Liu (PaulLiu) <paulliu@debian.org> Change-Id: I78914d6002755f733ea866127cb47982a00f9700
This commit is contained in:
Ying-Chun Liu (PaulLiu)
parent
ce0bec6587
commit
75fbf5546b
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@ -0,0 +1,117 @@
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/*
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* Copyright 2021 NXP
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <stdbool.h>
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#include <arch_helpers.h>
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#include <common/bl_common.h>
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#include <common/debug.h>
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#include <common/desc_image_load.h>
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#include <common/tbbr/tbbr_img_def.h>
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#include <context.h>
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#include <drivers/arm/tzc380.h>
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#include <drivers/console.h>
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#include <drivers/generic_delay_timer.h>
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#include <drivers/mmc.h>
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#include <lib/el3_runtime/context_mgmt.h>
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#include <lib/mmio.h>
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#include <lib/optee_utils.h>
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#include <lib/xlat_tables/xlat_tables_v2.h>
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#include <imx8m_caam.h>
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#include "imx8mp_private.h"
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#include <imx_aipstz.h>
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#include <imx_rdc.h>
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#include <imx_uart.h>
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#include <plat/common/platform.h>
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#include <plat_imx8.h>
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#include <platform_def.h>
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static const struct aipstz_cfg aipstz[] = {
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{IMX_AIPSTZ1, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, },
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{IMX_AIPSTZ2, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, },
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{IMX_AIPSTZ3, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, },
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{IMX_AIPSTZ4, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, },
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{0},
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};
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void bl2_el3_early_platform_setup(u_register_t arg0, u_register_t arg1,
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u_register_t arg2, u_register_t arg3)
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{
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static console_t console;
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unsigned int i;
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/* Enable CSU NS access permission */
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for (i = 0U; i < 64; i++) {
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mmio_write_32(IMX_CSU_BASE + i * 4, 0x00ff00ff);
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}
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imx_aipstz_init(aipstz);
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console_imx_uart_register(IMX_BOOT_UART_BASE, IMX_BOOT_UART_CLK_IN_HZ,
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IMX_CONSOLE_BAUDRATE, &console);
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generic_delay_timer_init();
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/* select the CKIL source to 32K OSC */
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mmio_write_32(IMX_ANAMIX_BASE + ANAMIX_MISC_CTL, 0x1);
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/* Open handles to a FIP image */
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plat_imx_io_setup();
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}
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void bl2_el3_plat_arch_setup(void)
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{
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}
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void bl2_platform_setup(void)
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{
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}
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int bl2_plat_handle_post_image_load(unsigned int image_id)
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{
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int err = 0;
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bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id);
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bl_mem_params_node_t *pager_mem_params = NULL;
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bl_mem_params_node_t *paged_mem_params = NULL;
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assert(bl_mem_params);
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switch (image_id) {
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case BL32_IMAGE_ID:
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pager_mem_params = get_bl_mem_params_node(BL32_EXTRA1_IMAGE_ID);
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assert(pager_mem_params);
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paged_mem_params = get_bl_mem_params_node(BL32_EXTRA2_IMAGE_ID);
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assert(paged_mem_params);
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err = parse_optee_header(&bl_mem_params->ep_info,
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&pager_mem_params->image_info,
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&paged_mem_params->image_info);
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if (err != 0) {
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WARN("OPTEE header parse error.\n");
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}
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break;
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default:
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/* Do nothing in default case */
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break;
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}
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return err;
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}
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unsigned int plat_get_syscnt_freq2(void)
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{
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return COUNTER_FREQUENCY;
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}
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void bl2_plat_runtime_setup(void)
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{
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return;
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}
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@ -0,0 +1,94 @@
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/*
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* Copyright (c) 2021, Arm Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <common/desc_image_load.h>
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#include <plat/common/platform.h>
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#include <platform_def.h>
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static bl_mem_params_node_t bl2_mem_params_descs[] = {
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{
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.image_id = BL31_IMAGE_ID,
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SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, VERSION_2,
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entry_point_info_t,
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SECURE | EXECUTABLE | EP_FIRST_EXE),
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.ep_info.pc = BL31_BASE,
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.ep_info.spsr = SPSR_64(MODE_EL3, MODE_SP_ELX,
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DISABLE_ALL_EXCEPTIONS),
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SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, VERSION_2, image_info_t,
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IMAGE_ATTRIB_PLAT_SETUP),
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.image_info.image_base = BL31_BASE,
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.image_info.image_max_size = BL31_LIMIT - BL31_BASE,
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.next_handoff_image_id = INVALID_IMAGE_ID,
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},
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{
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.image_id = BL32_IMAGE_ID,
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SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, VERSION_2,
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entry_point_info_t,
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SECURE | EXECUTABLE),
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.ep_info.pc = BL32_BASE,
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SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, VERSION_2,
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image_info_t, 0),
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.image_info.image_base = BL32_BASE,
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.image_info.image_max_size = BL32_SIZE,
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.next_handoff_image_id = BL33_IMAGE_ID,
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},
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{
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.image_id = BL32_EXTRA1_IMAGE_ID,
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SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, VERSION_2,
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entry_point_info_t,
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SECURE | NON_EXECUTABLE),
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SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, VERSION_2,
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image_info_t, IMAGE_ATTRIB_SKIP_LOADING),
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.image_info.image_base = BL32_BASE,
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.image_info.image_max_size = BL32_SIZE,
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.next_handoff_image_id = INVALID_IMAGE_ID,
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},
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{
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/* This is a zero sized image so we don't set base or size */
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.image_id = BL32_EXTRA2_IMAGE_ID,
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SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
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VERSION_2, entry_point_info_t,
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SECURE | NON_EXECUTABLE),
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SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
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VERSION_2, image_info_t,
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IMAGE_ATTRIB_SKIP_LOADING),
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.next_handoff_image_id = INVALID_IMAGE_ID,
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},
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{
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.image_id = BL33_IMAGE_ID,
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SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, VERSION_2,
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entry_point_info_t,
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NON_SECURE | EXECUTABLE),
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# ifdef PRELOADED_BL33_BASE
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.ep_info.pc = PLAT_NS_IMAGE_OFFSET,
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SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
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VERSION_2, image_info_t,
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IMAGE_ATTRIB_SKIP_LOADING),
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# else
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.ep_info.pc = PLAT_NS_IMAGE_OFFSET,
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SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
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VERSION_2, image_info_t, 0),
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.image_info.image_base = PLAT_NS_IMAGE_OFFSET,
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.image_info.image_max_size = PLAT_NS_IMAGE_SIZE,
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# endif /* PRELOADED_BL33_BASE */
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.next_handoff_image_id = INVALID_IMAGE_ID,
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}
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};
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REGISTER_BL_IMAGE_DESCS(bl2_mem_params_descs);
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@ -6,7 +6,9 @@
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PLAT_INCLUDES := -Iplat/imx/common/include \
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-Iplat/imx/imx8m/include \
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-Iplat/imx/imx8m/imx8mp/include
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-Iplat/imx/imx8m/imx8mp/include \
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-Idrivers/imx/usdhc \
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-Iinclude/common/tbbr
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# Translation tables library
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include lib/xlat_tables_v2/xlat_tables.mk
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@ -40,6 +42,58 @@ BL31_SOURCES += plat/imx/common/imx8_helpers.S \
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${IMX_GIC_SOURCES} \
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${XLAT_TABLES_LIB_SRCS}
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ifeq (${NEED_BL2},yes)
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BL2_SOURCES += common/desc_image_load.c \
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plat/imx/common/imx8_helpers.S \
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plat/imx/common/imx_uart_console.S \
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plat/imx/imx8m/imx8mp/imx8mp_bl2_el3_setup.c \
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plat/imx/imx8m/imx8mp/gpc.c \
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plat/imx/imx8m/imx_aipstz.c \
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plat/imx/imx8m/imx_rdc.c \
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plat/imx/imx8m/imx8m_caam.c \
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plat/common/plat_psci_common.c \
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lib/cpus/aarch64/cortex_a53.S \
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drivers/arm/tzc/tzc380.c \
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drivers/delay_timer/delay_timer.c \
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drivers/delay_timer/generic_delay_timer.c \
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${PLAT_GIC_SOURCES} \
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${PLAT_DRAM_SOURCES} \
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${XLAT_TABLES_LIB_SRCS} \
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drivers/mmc/mmc.c \
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drivers/io/io_block.c \
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drivers/io/io_fip.c \
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drivers/io/io_memmap.c \
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drivers/io/io_storage.c \
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drivers/imx/usdhc/imx_usdhc.c \
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plat/imx/imx8m/imx8mp/imx8mp_bl2_mem_params_desc.c \
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plat/imx/common/imx_io_storage.c \
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plat/imx/imx8m/imx8m_image_load.c \
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lib/optee/optee_utils.c
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endif
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# Add the build options to pack BLx images and kernel device tree
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# in the FIP if the platform requires.
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ifneq ($(BL2),)
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RESET_TO_BL31 := 0
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$(eval $(call TOOL_ADD_PAYLOAD,${BUILD_PLAT}/tb_fw.crt,--tb-fw-cert))
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endif
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ifneq ($(BL32_EXTRA1),)
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$(eval $(call TOOL_ADD_IMG,BL32_EXTRA1,--tos-fw-extra1))
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endif
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ifneq ($(BL32_EXTRA2),)
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$(eval $(call TOOL_ADD_IMG,BL32_EXTRA2,--tos-fw-extra2))
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endif
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ifneq ($(HW_CONFIG),)
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$(eval $(call TOOL_ADD_IMG,HW_CONFIG,--hw-config))
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endif
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ifeq (${NEED_BL2},yes)
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$(eval $(call add_define,NEED_BL2))
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LOAD_IMAGE_V2 := 1
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# Non-TF Boot ROM
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BL2_AT_EL3 := 1
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endif
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USE_COHERENT_MEM := 1
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RESET_TO_BL31 := 1
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A53_DISABLE_NON_TEMPORAL_HINT := 0
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