imx: imx8qx: add domain suspend/resume support
Add domain suspend/resume support, Linux kernel can "echo mem > /sys/power/state" to put system into suspend mode, all CPUs and cluster will be powered off and can be waked up if irq pending in GIC, tested on i.MX8QX MEK board. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
This commit is contained in:
Anson Huang
parent
3260f5c7c8
commit
762688bff2
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@ -27,3 +27,20 @@ void __dead2 imx_system_reset(void)
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panic();
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}
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int imx_validate_power_state(unsigned int power_state,
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psci_power_state_t *req_state)
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{
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/* TODO */
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return PSCI_E_INVALID_PARAMS;
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}
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void imx_get_sys_suspend_power_state(psci_power_state_t *req_state)
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{
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unsigned int i;
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/* CPU & cluster off, system in retention */
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for (i = MPIDR_AFFLVL0; i < PLAT_MAX_PWR_LVL; i++)
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req_state->pwr_domain_state[i] = PLAT_MAX_OFF_STATE;
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req_state->pwr_domain_state[PLAT_MAX_PWR_LVL] = PLAT_MAX_RET_STATE;
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}
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@ -8,6 +8,7 @@
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#define __PLAT_IMX8_H__
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#include <gicv3.h>
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#include <psci.h>
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unsigned int plat_calc_core_pos(uint64_t mpidr);
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void imx_mailbox_init(uintptr_t base_addr);
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@ -19,4 +20,7 @@ void plat_gic_pcpu_init(void);
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void __dead2 imx_system_off(void);
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void __dead2 imx_system_reset(void);
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int imx_validate_power_state(unsigned int power_state,
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psci_power_state_t *req_state);
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void imx_get_sys_suspend_power_state(psci_power_state_t *req_state);
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#endif /*__PLAT_IMX8_H__ */
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@ -18,13 +18,6 @@ const static int ap_core_index[PLATFORM_CORE_COUNT] = {
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SC_R_A35_0, SC_R_A35_1, SC_R_A35_2, SC_R_A35_3
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};
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plat_local_state_t plat_get_target_pwr_state(unsigned int lvl,
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const plat_local_state_t *target_state,
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unsigned int ncpu)
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{
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return 0;
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}
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int imx_pwr_domain_on(u_register_t mpidr)
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{
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int ret = PSCI_E_SUCCESS;
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@ -71,6 +64,29 @@ void imx_pwr_domain_off(const psci_power_state_t *target_state)
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tf_printf("turn off core:%d\n", cpu_id);
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}
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void imx_domain_suspend(const psci_power_state_t *target_state)
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{
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u_register_t mpidr = read_mpidr_el1();
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unsigned int cpu_id = MPIDR_AFFLVL0_VAL(mpidr);
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plat_gic_cpuif_disable();
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sc_pm_set_cpu_resume_addr(ipc_handle, ap_core_index[cpu_id], BL31_BASE);
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sc_pm_req_cpu_low_power_mode(ipc_handle, ap_core_index[cpu_id],
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SC_PM_PW_MODE_OFF, SC_PM_WAKE_SRC_GIC);
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}
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void imx_domain_suspend_finish(const psci_power_state_t *target_state)
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{
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u_register_t mpidr = read_mpidr_el1();
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unsigned int cpu_id = MPIDR_AFFLVL0_VAL(mpidr);
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sc_pm_req_low_power_mode(ipc_handle, ap_core_index[cpu_id],
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SC_PM_PW_MODE_ON);
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plat_gic_cpuif_enable();
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}
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static const plat_psci_ops_t imx_plat_psci_ops = {
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.pwr_domain_on = imx_pwr_domain_on,
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.pwr_domain_on_finish = imx_pwr_domain_on_finish,
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@ -78,6 +94,10 @@ static const plat_psci_ops_t imx_plat_psci_ops = {
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.system_off = imx_system_off,
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.system_reset = imx_system_reset,
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.pwr_domain_off = imx_pwr_domain_off,
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.pwr_domain_suspend = imx_domain_suspend,
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.pwr_domain_suspend_finish = imx_domain_suspend_finish,
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.get_sys_suspend_power_state = imx_get_sys_suspend_power_state,
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.validate_power_state = imx_validate_power_state,
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};
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int plat_setup_psci_ops(uintptr_t sec_entrypoint,
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@ -86,5 +106,17 @@ int plat_setup_psci_ops(uintptr_t sec_entrypoint,
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imx_mailbox_init(sec_entrypoint);
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*psci_ops = &imx_plat_psci_ops;
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/* Request low power mode for A35 cluster, only need to do once */
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sc_pm_req_low_power_mode(ipc_handle, SC_R_A35, SC_PM_PW_MODE_OFF);
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/* Request RUN and LP modes for DDR, system interconnect etc. */
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sc_pm_req_sys_if_power_mode(ipc_handle, SC_R_A35,
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SC_PM_SYS_IF_DDR, SC_PM_PW_MODE_ON, SC_PM_PW_MODE_STBY);
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sc_pm_req_sys_if_power_mode(ipc_handle, SC_R_A35,
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SC_PM_SYS_IF_MU, SC_PM_PW_MODE_ON, SC_PM_PW_MODE_STBY);
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sc_pm_req_sys_if_power_mode(ipc_handle, SC_R_A35,
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SC_PM_SYS_IF_INTERCONNECT, SC_PM_PW_MODE_ON,
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SC_PM_PW_MODE_STBY);
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return 0;
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}
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@ -21,6 +21,7 @@ BL31_SOURCES += plat/imx/common/lpuart_console.S \
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plat/imx/imx8qx/imx8qx_psci.c \
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plat/imx/common/imx8_topology.c \
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plat/imx/common/imx8_psci.c \
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plat/common/plat_psci_common.c \
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lib/xlat_tables/xlat_tables_common.c \
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lib/xlat_tables/aarch64/xlat_tables.c \
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lib/cpus/aarch64/cortex_a35.S \
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