Add SiP service to configure Arm Ethos-N NPU
By default the Arm Ethos-N NPU will boot up in secure mode. In this mode the non-secure world cannot access the registers needed to use the NPU. To still allow the non-secure world to use the NPU, a SiP service has been added that can delegate non-secure access to the registers needed to use it. Only the HW_CONFIG for the Arm Juno platform has been updated to include the device tree for the NPU and the platform currently only loads the HW_CONFIG in AArch64 builds. Signed-off-by: Mikael Olsson <mikael.olsson@arm.com> Change-Id: I65dfd864042ed43faae0a259dcf319cbadb5f3d2
This commit is contained in:
Mikael Olsson
Manish Pandey
parent
5d5fb10f9c
commit
76a21174d2
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@ -91,6 +91,12 @@ Arm Platform Build Options
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platforms. If this option is specified, then the path to the CryptoCell
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SBROM library must be specified via ``CCSBROM_LIB_PATH`` flag.
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- ``ARM_ETHOSN_NPU_DRIVER``: boolean option to enable a SiP service that can
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configure an Arm Ethos-N NPU. To use this service the target platform's
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``HW_CONFIG`` must include the device tree nodes for the NPU. Currently, only
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the Arm Juno platform has this included in its ``HW_CONFIG`` and the platform
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only loads the ``HW_CONFIG`` in AArch64 builds. Default is 0.
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- ``ARM_SPMC_MANIFEST_DTS`` : path to an alternate manifest file used as the
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SPMC Core manifest. Valid when ``SPD=spmd`` is selected.
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@ -128,4 +134,4 @@ Arm CSS Platform-Specific Build Options
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--------------
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*Copyright (c) 2019-2020, Arm Limited. All rights reserved.*
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*Copyright (c) 2019-2021, Arm Limited. All rights reserved.*
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@ -0,0 +1,164 @@
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/*
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* Copyright (c) 2021, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <stdint.h>
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#include <stdbool.h>
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#include <common/debug.h>
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#include <common/runtime_svc.h>
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#include <drivers/arm/ethosn.h>
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#include <drivers/delay_timer.h>
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#include <lib/mmio.h>
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#include <plat/arm/common/fconf_ethosn_getter.h>
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/* Arm Ethos-N NPU (NPU) status */
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#define ETHOSN_STATUS \
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FCONF_GET_PROPERTY(hw_config, ethosn_config, status)
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/* Number of NPU cores available */
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#define ETHOSN_NUM_CORES \
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FCONF_GET_PROPERTY(hw_config, ethosn_config, num_cores)
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/* Address to an NPU core */
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#define ETHOSN_CORE_ADDR(core_idx) \
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FCONF_GET_PROPERTY(hw_config, ethosn_core_addr, core_idx)
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/* NPU core sec registry address */
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#define ETHOSN_CORE_SEC_REG(core_addr, reg_offset) \
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(core_addr + reg_offset)
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/* Reset timeout in us */
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#define ETHOSN_RESET_TIMEOUT_US U(10 * 1000 * 1000)
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#define ETHOSN_RESET_WAIT_US U(1)
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#define SEC_DEL_REG U(0x0004)
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#define SEC_DEL_VAL U(0x81C)
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#define SEC_DEL_EXCC_MASK U(0x20)
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#define SEC_SECCTLR_REG U(0x0010)
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#define SEC_SECCTLR_VAL U(0x3)
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#define SEC_DEL_MMUSID_REG U(0x2008)
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#define SEC_DEL_MMUSID_VAL U(0x3FFFF)
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#define SEC_DEL_ADDR_EXT_REG U(0x201C)
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#define SEC_DEL_ADDR_EXT_VAL U(0x15)
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#define SEC_SYSCTRL0_REG U(0x0018)
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#define SEC_SYSCTRL0_SOFT_RESET U(3U << 29)
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#define SEC_SYSCTRL0_HARD_RESET U(1U << 31)
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static void ethosn_delegate_to_ns(uintptr_t core_addr)
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{
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mmio_setbits_32(ETHOSN_CORE_SEC_REG(core_addr, SEC_SECCTLR_REG),
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SEC_SECCTLR_VAL);
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mmio_setbits_32(ETHOSN_CORE_SEC_REG(core_addr, SEC_DEL_REG),
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SEC_DEL_VAL);
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mmio_setbits_32(ETHOSN_CORE_SEC_REG(core_addr, SEC_DEL_MMUSID_REG),
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SEC_DEL_MMUSID_VAL);
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mmio_setbits_32(ETHOSN_CORE_SEC_REG(core_addr, SEC_DEL_ADDR_EXT_REG),
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SEC_DEL_ADDR_EXT_VAL);
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}
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static int ethosn_is_sec(void)
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{
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if ((mmio_read_32(ETHOSN_CORE_SEC_REG(ETHOSN_CORE_ADDR(0), SEC_DEL_REG))
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& SEC_DEL_EXCC_MASK) != 0U) {
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return 0;
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}
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return 1;
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}
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static bool ethosn_reset(uintptr_t core_addr, int hard_reset)
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{
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unsigned int timeout;
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const uintptr_t sysctrl0_reg =
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ETHOSN_CORE_SEC_REG(core_addr, SEC_SYSCTRL0_REG);
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const uint32_t reset_val = (hard_reset != 0) ? SEC_SYSCTRL0_HARD_RESET
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: SEC_SYSCTRL0_SOFT_RESET;
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mmio_write_32(sysctrl0_reg, reset_val);
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/* Wait for reset to complete */
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for (timeout = 0U; timeout < ETHOSN_RESET_TIMEOUT_US;
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timeout += ETHOSN_RESET_WAIT_US) {
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if ((mmio_read_32(sysctrl0_reg) & reset_val) == 0U) {
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break;
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}
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udelay(ETHOSN_RESET_WAIT_US);
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}
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return timeout < ETHOSN_RESET_TIMEOUT_US;
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}
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uintptr_t ethosn_smc_handler(uint32_t smc_fid,
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u_register_t core_idx,
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u_register_t x2,
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u_register_t x3,
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u_register_t x4,
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void *cookie,
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void *handle,
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u_register_t flags)
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{
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uintptr_t core_addr;
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int hard_reset = 0;
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/* Only SiP fast calls are expected */
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if ((GET_SMC_TYPE(smc_fid) != SMC_TYPE_FAST) ||
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(GET_SMC_OEN(smc_fid) != OEN_SIP_START)) {
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SMC_RET1(handle, SMC_UNK);
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}
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/* Truncate parameters to 32-bits for SMC32 */
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if (GET_SMC_CC(smc_fid) == SMC_32) {
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core_idx &= 0xFFFFFFFF;
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x2 &= 0xFFFFFFFF;
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x3 &= 0xFFFFFFFF;
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x4 &= 0xFFFFFFFF;
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}
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if (!is_ethosn_fid(smc_fid)) {
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SMC_RET1(handle, SMC_UNK);
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}
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if (ETHOSN_STATUS == ETHOSN_STATUS_DISABLED) {
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WARN("ETHOSN: Arm Ethos-N NPU not available\n");
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SMC_RET1(handle, ETHOSN_NOT_SUPPORTED);
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}
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switch (smc_fid & FUNCID_NUM_MASK) {
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case ETHOSN_FNUM_VERSION:
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SMC_RET2(handle, ETHOSN_VERSION_MAJOR, ETHOSN_VERSION_MINOR);
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case ETHOSN_FNUM_IS_SEC:
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SMC_RET1(handle, ethosn_is_sec());
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case ETHOSN_FNUM_HARD_RESET:
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hard_reset = 1;
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/* Fallthrough */
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case ETHOSN_FNUM_SOFT_RESET:
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if (core_idx >= ETHOSN_NUM_CORES) {
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WARN("ETHOSN: core index out of range\n");
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SMC_RET1(handle, ETHOSN_CORE_IDX_OUT_OF_RANGE);
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}
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core_addr = ETHOSN_CORE_ADDR(core_idx);
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if (!ethosn_reset(core_addr, hard_reset)) {
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SMC_RET1(handle, ETHOSN_FAILURE);
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}
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ethosn_delegate_to_ns(core_addr);
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SMC_RET1(handle, ETHOSN_SUCCESS);
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default:
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SMC_RET1(handle, SMC_UNK);
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}
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}
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@ -0,0 +1,25 @@
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/*
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* Copyright (c) 2021, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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/ {
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#address-cells = <2>;
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#size-cells = <2>;
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ethosn: ethosn@6f300000 {
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compatible = "ethosn";
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reg = <0 0x6f300000 0 0x00100000>;
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status = "okay";
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/*
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* Single-core NPU. For multi-core NPU, additional core nodes
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* and reg values must be added.
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*/
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core0 {
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compatible = "ethosn-core";
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status = "okay";
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};
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};
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};
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@ -9,3 +9,7 @@
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/ {
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};
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#if ARM_ETHOSN_NPU_DRIVER
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#include "juno-ethosn.dtsi"
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#endif
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@ -0,0 +1,61 @@
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/*
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* Copyright (c) 2021, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef ETHOSN_H
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#define ETHOSN_H
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#include <lib/smccc.h>
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/* Function numbers */
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#define ETHOSN_FNUM_VERSION U(0x50)
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#define ETHOSN_FNUM_IS_SEC U(0x51)
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#define ETHOSN_FNUM_HARD_RESET U(0x52)
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#define ETHOSN_FNUM_SOFT_RESET U(0x53)
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/* 0x54-0x5F reserved for future use */
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/* SMC64 function IDs */
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#define ETHOSN_FID_64(func_num) U(0xC2000000 | func_num)
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#define ETHOSN_FID_VERSION_64 ETHOSN_FID_64(ETHOSN_FNUM_VERSION)
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#define ETHOSN_FID_IS_SEC_64 ETHOSN_FID_64(ETHOSN_FNUM_IS_SEC)
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#define ETHOSN_FID_HARD_RESET_64 ETHOSN_FID_64(ETHOSN_FNUM_HARD_RESET)
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#define ETHOSN_FID_SOFT_RESET_64 ETHOSN_FID_64(ETHOSN_FNUM_SOFT_RESET)
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/* SMC32 function IDs */
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#define ETHOSN_FID_32(func_num) U(0x82000000 | func_num)
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#define ETHOSN_FID_VERSION_32 ETHOSN_FID_32(ETHOSN_FNUM_VERSION)
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#define ETHOSN_FID_IS_SEC_32 ETHOSN_FID_32(ETHOSN_FNUM_IS_SEC)
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#define ETHOSN_FID_HARD_RESET_32 ETHOSN_FID_32(ETHOSN_FNUM_HARD_RESET)
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#define ETHOSN_FID_SOFT_RESET_32 ETHOSN_FID_32(ETHOSN_FNUM_SOFT_RESET)
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#define ETHOSN_NUM_SMC_CALLS 8
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/* Macro to identify function calls */
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#define ETHOSN_FID_MASK U(0xFFF0)
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#define ETHOSN_FID_VALUE U(0x50)
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#define is_ethosn_fid(_fid) (((_fid) & ETHOSN_FID_MASK) == ETHOSN_FID_VALUE)
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/* Service version */
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#define ETHOSN_VERSION_MAJOR U(0)
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#define ETHOSN_VERSION_MINOR U(1)
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/* Return codes for function calls */
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#define ETHOSN_SUCCESS 0
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#define ETHOSN_NOT_SUPPORTED -1
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/* -2 Reserved for NOT_REQUIRED */
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/* -3 Reserved for INVALID_PARAMETER */
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#define ETHOSN_FAILURE -4
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#define ETHOSN_CORE_IDX_OUT_OF_RANGE -5
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uintptr_t ethosn_smc_handler(uint32_t smc_fid,
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u_register_t core_idx,
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u_register_t x2,
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u_register_t x3,
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u_register_t x4,
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void *cookie,
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void *handle,
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u_register_t flags);
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#endif /* ETHOSN_H */
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2016-2019,2021, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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/* DEBUGFS_SMC_32 0x82000030U */
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/* DEBUGFS_SMC_64 0xC2000030U */
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/*
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* Arm Ethos-N NPU SiP SMC function IDs
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* 0xC2000050-0xC200005F
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* 0x82000050-0x8200005F
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*/
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/* ARM SiP Service Calls version numbers */
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#define ARM_SIP_SVC_VERSION_MAJOR U(0x0)
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#define ARM_SIP_SVC_VERSION_MINOR U(0x2)
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/*
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* Copyright (c) 2021, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef FCONF_ETHOSN_GETTER_H
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#define FCONF_ETHOSN_GETTER_H
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#include <assert.h>
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#include <lib/fconf/fconf.h>
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#define hw_config__ethosn_config_getter(prop) ethosn_config.prop
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#define hw_config__ethosn_core_addr_getter(idx) __extension__ ({ \
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assert(idx < ethosn_config.num_cores); \
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ethosn_config.core_addr[idx]; \
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})
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#define ETHOSN_STATUS_DISABLED U(0)
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#define ETHOSN_STATUS_ENABLED U(1)
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#define ETHOSN_CORE_NUM_MAX U(64)
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struct ethosn_config_t {
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uint8_t status;
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uint32_t num_cores;
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uint64_t core_addr[ETHOSN_CORE_NUM_MAX];
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};
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int fconf_populate_arm_ethosn(uintptr_t config);
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extern struct ethosn_config_t ethosn_config;
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#endif /* FCONF_ETHOSN_GETTER_H */
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@ -1,5 +1,5 @@
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#
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# Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
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# Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved.
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#
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# SPDX-License-Identifier: BSD-3-Clause
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#
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@ -100,6 +100,11 @@ ifeq (${ARM_LINUX_KERNEL_AS_BL33},1)
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$(eval $(call add_define,ARM_PRELOADED_DTB_BASE))
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endif
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# Arm Ethos-N NPU SiP service
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ARM_ETHOSN_NPU_DRIVER := 0
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$(eval $(call assert_boolean,ARM_ETHOSN_NPU_DRIVER))
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$(eval $(call add_define,ARM_ETHOSN_NPU_DRIVER))
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# Use an implementation of SHA-256 with a smaller memory footprint but reduced
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# speed.
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$(eval $(call add_define,MBEDTLS_SHA256_SMALLER))
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plat/arm/common/arm_topology.c \
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plat/common/plat_psci_common.c
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ifeq (${ENABLE_PMF}, 1)
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ifneq ($(filter 1,${ENABLE_PMF} ${ARM_ETHOSN_NPU_DRIVER}),)
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ARM_SVC_HANDLER_SRCS :=
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ifeq (${ENABLE_PMF},1)
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ARM_SVC_HANDLER_SRCS += lib/pmf/pmf_smc.c
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endif
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ifeq (${ARM_ETHOSN_NPU_DRIVER},1)
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ARM_SVC_HANDLER_SRCS += plat/arm/common/fconf/fconf_ethosn_getter.c \
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drivers/delay_timer/delay_timer.c \
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drivers/arm/ethosn/ethosn_smc.c
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endif
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ifeq (${ARCH}, aarch64)
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BL31_SOURCES += plat/arm/common/aarch64/execution_state_switch.c\
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plat/arm/common/arm_sip_svc.c \
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lib/pmf/pmf_smc.c
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${ARM_SVC_HANDLER_SRCS}
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else
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BL32_SOURCES += plat/arm/common/arm_sip_svc.c \
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lib/pmf/pmf_smc.c
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${ARM_SVC_HANDLER_SRCS}
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endif
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endif
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2016-2019,2021, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -8,6 +8,7 @@
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#include <common/debug.h>
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#include <common/runtime_svc.h>
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#include <drivers/arm/ethosn.h>
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#include <lib/debugfs.h>
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#include <lib/pmf/pmf.h>
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#include <plat/arm/common/arm_sip_svc.h>
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@ -50,6 +51,8 @@ static uintptr_t arm_sip_handler(unsigned int smc_fid,
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{
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int call_count = 0;
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#if ENABLE_PMF
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/*
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* Dispatch PMF calls to PMF SMC handler and return its return
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* value
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@ -59,6 +62,8 @@ static uintptr_t arm_sip_handler(unsigned int smc_fid,
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handle, flags);
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}
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#endif /* ENABLE_PMF */
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#if USE_DEBUGFS
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if (is_debugfs_fid(smc_fid)) {
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@ -68,6 +73,15 @@ static uintptr_t arm_sip_handler(unsigned int smc_fid,
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#endif /* USE_DEBUGFS */
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||||
|
||||
#if ARM_ETHOSN_NPU_DRIVER
|
||||
|
||||
if (is_ethosn_fid(smc_fid)) {
|
||||
return ethosn_smc_handler(smc_fid, x1, x2, x3, x4, cookie,
|
||||
handle, flags);
|
||||
}
|
||||
|
||||
#endif /* ARM_ETHOSN_NPU_DRIVER */
|
||||
|
||||
switch (smc_fid) {
|
||||
case ARM_SIP_SVC_EXE_STATE_SWITCH: {
|
||||
/* Execution state can be switched only if EL3 is AArch64 */
|
||||
|
|
@ -92,6 +106,11 @@ static uintptr_t arm_sip_handler(unsigned int smc_fid,
|
|||
/* PMF calls */
|
||||
call_count += PMF_NUM_SMC_CALLS;
|
||||
|
||||
#if ARM_ETHOSN_NPU_DRIVER
|
||||
/* ETHOSN calls */
|
||||
call_count += ETHOSN_NUM_SMC_CALLS;
|
||||
#endif /* ARM_ETHOSN_NPU_DRIVER */
|
||||
|
||||
/* State switch call */
|
||||
call_count += 1;
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,108 @@
|
|||
/*
|
||||
* Copyright (c) 2021, Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <assert.h>
|
||||
#include <string.h>
|
||||
|
||||
#include <common/debug.h>
|
||||
#include <common/fdt_wrappers.h>
|
||||
#include <libfdt.h>
|
||||
#include <plat/arm/common/fconf_ethosn_getter.h>
|
||||
|
||||
struct ethosn_config_t ethosn_config;
|
||||
|
||||
static uint8_t fdt_node_get_status(const void *fdt, int node)
|
||||
{
|
||||
int len;
|
||||
uint8_t status = ETHOSN_STATUS_DISABLED;
|
||||
const char *node_status;
|
||||
|
||||
node_status = fdt_getprop(fdt, node, "status", &len);
|
||||
if (node_status == NULL ||
|
||||
(len == 5 && /* Includes null character */
|
||||
strncmp(node_status, "okay", 4U) == 0)) {
|
||||
status = ETHOSN_STATUS_ENABLED;
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
int fconf_populate_ethosn_config(uintptr_t config)
|
||||
{
|
||||
int ethosn_node;
|
||||
int sub_node;
|
||||
uint8_t ethosn_status;
|
||||
uint32_t core_count = 0U;
|
||||
uint32_t core_addr_idx = 0U;
|
||||
const void *hw_conf_dtb = (const void *)config;
|
||||
|
||||
/* Find offset to node with 'ethosn' compatible property */
|
||||
ethosn_node = fdt_node_offset_by_compatible(hw_conf_dtb, -1, "ethosn");
|
||||
if (ethosn_node < 0) {
|
||||
ERROR("FCONF: Can't find 'ethosn' compatible node in dtb\n");
|
||||
return ethosn_node;
|
||||
}
|
||||
|
||||
/* If the Arm Ethos-N NPU is disabled the core check can be skipped */
|
||||
ethosn_status = fdt_node_get_status(hw_conf_dtb, ethosn_node);
|
||||
if (ethosn_status == ETHOSN_STATUS_DISABLED) {
|
||||
return 0;
|
||||
}
|
||||
|
||||
fdt_for_each_subnode(sub_node, hw_conf_dtb, ethosn_node) {
|
||||
int err;
|
||||
uintptr_t addr;
|
||||
uint8_t status;
|
||||
|
||||
/* Check that the sub node is "ethosn-core" compatible */
|
||||
if (fdt_node_check_compatible(hw_conf_dtb, sub_node,
|
||||
"ethosn-core") != 0) {
|
||||
/* Ignore incompatible sub node */
|
||||
continue;
|
||||
}
|
||||
|
||||
/* Including disabled cores */
|
||||
if (core_addr_idx >= ETHOSN_CORE_NUM_MAX) {
|
||||
ERROR("FCONF: Reached max number of Arm Ethos-N NPU cores\n");
|
||||
return -1;
|
||||
}
|
||||
|
||||
status = fdt_node_get_status(hw_conf_dtb, ethosn_node);
|
||||
if (status == ETHOSN_STATUS_DISABLED) {
|
||||
++core_addr_idx;
|
||||
continue;
|
||||
}
|
||||
|
||||
err = fdt_get_reg_props_by_index(hw_conf_dtb, ethosn_node,
|
||||
core_addr_idx, &addr, NULL);
|
||||
if (err < 0) {
|
||||
ERROR("FCONF: Failed to read reg property for Arm Ethos-N NPU core %u\n",
|
||||
core_addr_idx);
|
||||
return err;
|
||||
}
|
||||
|
||||
ethosn_config.core_addr[core_count++] = addr;
|
||||
++core_addr_idx;
|
||||
}
|
||||
|
||||
if ((sub_node < 0) && (sub_node != -FDT_ERR_NOTFOUND)) {
|
||||
ERROR("FCONF: Failed to parse sub nodes\n");
|
||||
return sub_node;
|
||||
}
|
||||
|
||||
/* The Arm Ethos-N NPU can't be used if no cores were found */
|
||||
if (core_count == 0) {
|
||||
ERROR("FCONF: No Arm Ethos-N NPU cores found\n");
|
||||
return -1;
|
||||
}
|
||||
|
||||
ethosn_config.num_cores = core_count;
|
||||
ethosn_config.status = ethosn_status;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
FCONF_REGISTER_POPULATOR(HW_CONFIG, ethosn_config, fconf_populate_ethosn_config);
|
||||
Loading…
Reference in New Issue