rcar_gen3: drivers: Change to restore timer counter value at resume
Changed to save and restore cntpct_el0 using memory mapped register for generic timer when System Suspend and Resume. Reported by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com> Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com> Change-Id: I40fd9f5434c4d52b320cd1d20322b9b8e4e67155
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@ -1,5 +1,5 @@
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/*
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/*
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* Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved.
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* Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
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*
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*
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* SPDX-License-Identifier: BSD-3-Clause
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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*/
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@ -94,9 +94,6 @@ int32_t rcar_log_init(void)
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sizeof(t_log->header.head));
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sizeof(t_log->header.head));
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t_log->header.index = 0U;
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t_log->header.index = 0U;
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t_log->header.size = 0U;
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t_log->header.size = 0U;
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#ifndef IMAGE_BL2
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rcar_stack_generic_timer[INDEX_TIMER_COUNT] = 0U;
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#endif
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}
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}
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rcar_lock_init();
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rcar_lock_init();
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@ -1,5 +1,5 @@
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/*
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/*
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* Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved.
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* Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
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*
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*
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* SPDX-License-Identifier: BSD-3-Clause
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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*/
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@ -12,8 +12,4 @@
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int32_t rcar_set_log_data(int32_t c);
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int32_t rcar_set_log_data(int32_t c);
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int32_t rcar_log_init(void);
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int32_t rcar_log_init(void);
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#if IMAGE_BL31
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extern uint64_t rcar_stack_generic_timer[5];
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#endif
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#endif /* RCAR_PRINTF_H */
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#endif /* RCAR_PRINTF_H */
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@ -1,21 +1,13 @@
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/*
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/*
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* Copyright (c) 2018, Renesas Electronics Corporation. All rights reserved.
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* Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
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*
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*
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* SPDX-License-Identifier: BSD-3-Clause
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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*/
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#include <arch.h>
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#include <arch.h>
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#include <asm_macros.S>
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#include <asm_macros.S>
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#include "rcar_def.h"
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.global rcar_pwrc_switch_stack
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.global rcar_pwrc_switch_stack
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.global rcar_pwrc_save_generic_timer
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.global rcar_pwrc_restore_generic_timer
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#define OFFSET_SP_X9_X10 (0x00)
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#define OFFSET_CNTFID0 (0x10)
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#define OFFSET_CNTPCT_EL0 (0x18)
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#define OFFSET_TIMER_COUNT (0x20)
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/*
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/*
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* x0 : jump address,
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* x0 : jump address,
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@ -54,37 +46,3 @@ func rcar_pwrc_switch_stack
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ldp x29, x30, [sp,#-16]
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ldp x29, x30, [sp,#-16]
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ret
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ret
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endfunc rcar_pwrc_switch_stack
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endfunc rcar_pwrc_switch_stack
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/* x0 : stack pointer base address */
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func rcar_pwrc_save_generic_timer
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stp x9, x10, [x0, #OFFSET_SP_X9_X10]
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/* save CNTFID0 and cntpct_el0 */
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mov_imm x10, (RCAR_CNTC_BASE + CNTFID_OFF)
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ldr x9, [x10]
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mrs x10, cntpct_el0
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stp x9, x10, [x0, #OFFSET_CNTFID0]
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ldp x9, x10, [x0, #OFFSET_SP_X9_X10]
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ret
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endfunc rcar_pwrc_save_generic_timer
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/* x0 : Stack pointer base address */
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func rcar_pwrc_restore_generic_timer
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stp x9, x10, [x0, #OFFSET_SP_X9_X10]
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/* restore CNTFID0 and cntpct_el0 */
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ldr x10, [x0, #OFFSET_CNTFID0]
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mov_imm x9, (RCAR_CNTC_BASE + CNTFID_OFF)
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str x10, [x9]
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ldp x9, x10, [x0, #OFFSET_CNTPCT_EL0]
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add x9, x9, x10
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str x9, [x0, #OFFSET_TIMER_COUNT]
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ldp x9, x10, [x0, #OFFSET_SP_X9_X10]
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ret
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endfunc rcar_pwrc_restore_generic_timer
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@ -13,6 +13,7 @@
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#include <lib/bakery_lock.h>
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#include <lib/bakery_lock.h>
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#include <lib/mmio.h>
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#include <lib/mmio.h>
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#include <lib/xlat_tables/xlat_tables_v2.h>
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#include <lib/xlat_tables/xlat_tables_v2.h>
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#include <plat/common/platform.h>
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#include "iic_dvfs.h"
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#include "iic_dvfs.h"
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#include "rcar_def.h"
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#include "rcar_def.h"
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@ -126,6 +127,14 @@ RCAR_INSTANTIATE_LOCK
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#define RST_MODEMR (RST_BASE + 0x0060U)
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#define RST_MODEMR (RST_BASE + 0x0060U)
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#define RST_MODEMR_BIT0 (0x00000001U)
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#define RST_MODEMR_BIT0 (0x00000001U)
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#define RCAR_CNTCR_OFF (0x00U)
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#define RCAR_CNTCVL_OFF (0x08U)
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#define RCAR_CNTCVU_OFF (0x0CU)
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#define RCAR_CNTFID_OFF (0x20U)
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#define RCAR_CNTCR_EN ((uint32_t)1U << 0U)
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#define RCAR_CNTCR_FCREQ(x) ((uint32_t)(x) << 8U)
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#if PMIC_ROHM_BD9571
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#if PMIC_ROHM_BD9571
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#define BIT_BKUP_CTRL_OUT ((uint8_t)(1U << 4))
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#define BIT_BKUP_CTRL_OUT ((uint8_t)(1U << 4))
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#define PMIC_BKUP_MODE_CNT (0x20U)
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#define PMIC_BKUP_MODE_CNT (0x20U)
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@ -323,6 +332,39 @@ done:
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rcar_lock_release();
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rcar_lock_release();
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}
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}
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static uint64_t rcar_pwrc_saved_cntpct_el0;
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static uint32_t rcar_pwrc_saved_cntfid;
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#if RCAR_SYSTEM_SUSPEND
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static void rcar_pwrc_save_timer_state(void)
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{
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rcar_pwrc_saved_cntpct_el0 = read_cntpct_el0();
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rcar_pwrc_saved_cntfid =
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mmio_read_32((uintptr_t)(RCAR_CNTC_BASE + RCAR_CNTFID_OFF));
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}
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#endif
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void rcar_pwrc_restore_timer_state(void)
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{
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/* Stop timer before restoring counter value */
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mmio_write_32((uintptr_t)(RCAR_CNTC_BASE + RCAR_CNTCR_OFF), 0U);
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mmio_write_32((uintptr_t)(RCAR_CNTC_BASE + RCAR_CNTCVL_OFF),
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(uint32_t)(rcar_pwrc_saved_cntpct_el0 & 0xFFFFFFFFU));
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mmio_write_32((uintptr_t)(RCAR_CNTC_BASE + RCAR_CNTCVU_OFF),
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(uint32_t)(rcar_pwrc_saved_cntpct_el0 >> 32U));
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mmio_write_32((uintptr_t)(RCAR_CNTC_BASE + RCAR_CNTFID_OFF),
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rcar_pwrc_saved_cntfid);
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/* Start generic timer back */
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write_cntfrq_el0((u_register_t)plat_get_syscnt_freq2());
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mmio_write_32((uintptr_t)(RCAR_CNTC_BASE + RCAR_CNTCR_OFF),
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(RCAR_CNTCR_FCREQ(0U) | RCAR_CNTCR_EN));
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}
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#if !PMIC_ROHM_BD9571
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#if !PMIC_ROHM_BD9571
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void rcar_pwrc_system_reset(void)
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void rcar_pwrc_system_reset(void)
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{
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{
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DEVICE_SRAM_STACK_SIZE);
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DEVICE_SRAM_STACK_SIZE);
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uint32_t sctlr;
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uint32_t sctlr;
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rcar_pwrc_save_generic_timer(rcar_stack_generic_timer);
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rcar_pwrc_save_timer_state();
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/* disable MMU */
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/* disable MMU */
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sctlr = (uint32_t) read_sctlr_el3();
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sctlr = (uint32_t) read_sctlr_el3();
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/*
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/*
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* Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved.
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* Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
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*
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*
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* SPDX-License-Identifier: BSD-3-Clause
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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*/
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uint32_t rcar_pwrc_get_cluster(void);
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uint32_t rcar_pwrc_get_cluster(void);
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uint32_t rcar_pwrc_get_mpidr_cluster(uint64_t mpidr);
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uint32_t rcar_pwrc_get_mpidr_cluster(uint64_t mpidr);
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uint32_t rcar_pwrc_get_cpu_num(uint32_t cluster_type);
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uint32_t rcar_pwrc_get_cpu_num(uint32_t cluster_type);
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void rcar_pwrc_restore_timer_state(void);
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void plat_secondary_reset(void);
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void plat_secondary_reset(void);
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void rcar_pwrc_code_copy_to_system_ram(void);
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void rcar_pwrc_code_copy_to_system_ram(void);
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void rcar_pwrc_suspend_to_ram(void);
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void rcar_pwrc_suspend_to_ram(void);
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#endif
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#endif
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extern void rcar_pwrc_save_generic_timer(uint64_t *rcar_stack_generic_timer);
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extern uint32_t rcar_pwrc_switch_stack(uintptr_t jump, uintptr_t stack,
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extern uint32_t rcar_pwrc_switch_stack(uintptr_t jump, uintptr_t stack,
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void *arg);
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void *arg);
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extern uint64_t rcar_stack_generic_timer[5];
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#endif
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#endif
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#endif /* PWRC_H */
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#endif /* PWRC_H */
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/*
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/*
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* Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved.
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* Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
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*
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*
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* SPDX-License-Identifier: BSD-3-Clause
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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*/
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#define CLUSTER_PWR_STATE(s) ((s)->pwr_domain_state[MPIDR_AFFLVL1])
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#define CLUSTER_PWR_STATE(s) ((s)->pwr_domain_state[MPIDR_AFFLVL1])
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#define CORE_PWR_STATE(s) ((s)->pwr_domain_state[MPIDR_AFFLVL0])
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#define CORE_PWR_STATE(s) ((s)->pwr_domain_state[MPIDR_AFFLVL0])
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uint64_t rcar_stack_generic_timer[5] __attribute__ ((section("data")));
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extern void rcar_pwrc_restore_generic_timer(uint64_t *stack);
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extern void rcar_pwrc_restore_generic_timer(uint64_t *stack);
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extern void plat_rcar_gic_driver_init(void);
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extern void plat_rcar_gic_driver_init(void);
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extern void plat_rcar_gic_init(void);
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extern void plat_rcar_gic_init(void);
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@ -150,11 +148,7 @@ static void rcar_pwr_domain_suspend_finish(const psci_power_state_t
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if (cluster_type == RCAR_CLUSTER_A53A57)
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if (cluster_type == RCAR_CLUSTER_A53A57)
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plat_cci_init();
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plat_cci_init();
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rcar_pwrc_restore_generic_timer(rcar_stack_generic_timer);
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rcar_pwrc_restore_timer_state();
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/* start generic timer */
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write_cntfrq_el0(plat_get_syscnt_freq2());
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mmio_write_32(RCAR_CNTC_BASE + CNTCR_OFF, CNTCR_FCREQ(U(0)) | CNTCR_EN);
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rcar_pwrc_setup();
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rcar_pwrc_setup();
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rcar_pwrc_code_copy_to_system_ram();
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rcar_pwrc_code_copy_to_system_ram();
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