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feat(intel): add SMC support for ROM Patch SHA384 mailbox 

HSD #16014059592:
Add support for ROM Patch SHA384 mailbox SMC call.

Signed-off-by: Kris Chaplin <kris.chaplin@linux.intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: Ide9a7af41a089980745cb7216a9bf85e7fbd84e3
This commit is contained in:
Sieu Mun Tang 2022-03-17 03:11:55 +08:00
parent f78cb61a11
commit 77902fca8f
5 changed files with 47 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
plat/intel/soc/common/include/socfpga_fcs.h
View File

@ -11,9 +11,11 @@
#define FCS_RANDOM_WORD_SIZE 8U
#define FCS_PROV_DATA_WORD_SIZE 44U
#define FCS_SHA384_WORD_SIZE 12U
#define FCS_RANDOM_BYTE_SIZE (FCS_RANDOM_WORD_SIZE * 4U)
#define FCS_PROV_DATA_BYTE_SIZE (FCS_PROV_DATA_WORD_SIZE * 4U)
#define FCS_SHA384_BYTE_SIZE (FCS_SHA384_WORD_SIZE * 4U)
#define FCS_CRYPTION_DATA_0 0x10100
@ -38,4 +40,7 @@ uint32_t intel_fcs_cryption(uint32_t mode, uint32_t src_addr,
uint32_t src_size, uint32_t dst_addr,
uint32_t dst_size, uint32_t *send_id);
uint32_t intel_fcs_get_rom_patch_sha384(uint64_t addr, uint64_t *ret_size,
uint32_t *mbox_error);
#endif /* SOCFPGA_FCS_H */

2
plat/intel/soc/common/include/socfpga_mailbox.h
View File

@ -67,6 +67,8 @@
#define MBOX_FCS_ENCRYPT_REQ 0x7E
#define MBOX_FCS_DECRYPT_REQ 0x7F
#define MBOX_FCS_RANDOM_GEN 0x80
/* Miscellaneous commands */
#define MBOX_GET_ROM_PATCH_SHA384 0x1B0
/* Mailbox Definitions */

3
plat/intel/soc/common/include/socfpga_sip_svc.h
View File

@ -44,6 +44,9 @@
/* ECC */
#define INTEL_SIP_SMC_ECC_DBE 0xC200000D
/* Generic Command */
#define INTEL_SIP_SMC_GET_ROM_PATCH_SHA384 0xC2000040
/* Send Mailbox Command */
#define INTEL_SIP_SMC_MBOX_SEND_CMD 0xC200001E

30
plat/intel/soc/common/sip/socfpga_sip_fcs.c
View File

@ -118,3 +118,33 @@ uint32_t intel_fcs_cryption(uint32_t mode, uint32_t src_addr,
return INTEL_SIP_SMC_STATUS_OK;
}
uint32_t intel_fcs_get_rom_patch_sha384(uint64_t addr, uint64_t *ret_size,
uint32_t *mbox_error)
{
int status;
unsigned int resp_len = FCS_SHA384_WORD_SIZE;
if (!is_address_in_ddr_range(addr, FCS_SHA384_BYTE_SIZE)) {
return INTEL_SIP_SMC_STATUS_REJECTED;
}
status = mailbox_send_cmd(MBOX_JOB_ID, MBOX_GET_ROM_PATCH_SHA384, NULL, 0U,
CMD_CASUAL, (uint32_t *) addr, &resp_len);
if (status < 0) {
*mbox_error = -status;
return INTEL_SIP_SMC_STATUS_ERROR;
}
if (resp_len != FCS_SHA384_WORD_SIZE) {
*mbox_error = GENERIC_RESPONSE_ERROR;
return INTEL_SIP_SMC_STATUS_ERROR;
}
*ret_size = FCS_SHA384_BYTE_SIZE;
flush_dcache_range(addr, *ret_size);
return INTEL_SIP_SMC_STATUS_OK;
}

8
plat/intel/soc/common/socfpga_sip_svc.c
View File

@ -433,8 +433,9 @@ uintptr_t sip_smc_handler(uint32_t smc_fid,
u_register_t flags)
{
uint32_t retval = 0;
uint32_t mbox_error = 0;
uint32_t completed_addr[3];
uint64_t rsu_respbuf[9];
uint64_t retval64, rsu_respbuf[9];
int status = INTEL_SIP_SMC_STATUS_OK;
int mbox_status;
unsigned int len_in_resp;
@ -542,6 +543,11 @@ uintptr_t sip_smc_handler(uint32_t smc_fid,
&len_in_resp);
SMC_RET3(handle, status, mbox_status, len_in_resp);
case INTEL_SIP_SMC_GET_ROM_PATCH_SHA384:
status = intel_fcs_get_rom_patch_sha384(x1, &retval64,
&mbox_error);
SMC_RET4(handle, status, mbox_error, x1, retval64);
default:
return socfpga_sip_handler(smc_fid, x1, x2, x3, x4,
cookie, handle, flags);