andrius
/
arm-trusted-firmware
1
0
Fork 0
Code Issues Pull Requests Releases Wiki Activity

Merge pull request #1734 from marex/arm/master/update-rcar-2.0.0 

Arm/master/update rcar 2.0.0
This commit is contained in:
Antonio Niño Díaz 2019-01-08 15:46:29 +00:00 committed by GitHub
parent c871903260 e68d214665
commit 7825d719d4
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
47 changed files with 2210 additions and 1799 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
drivers/renesas/rcar/auth/auth_mod.c
View File

@ -113,7 +113,7 @@ verify_image:
}
#if RCAR_BL2_DCACHE == 1
/* clean and disable */
write_sctlr_el1(read_sctlr_el1() & ~SCTLR_C_BIT);
write_sctlr_el3(read_sctlr_el3() & ~SCTLR_C_BIT);
dcsw_op_all(DCCISW);
#endif
ret = (mmio_read_32(RCAR_BOOT_KEY_CERT_NEW) == RCAR_CERT_MAGIC_NUM) ?
@ -124,7 +124,7 @@ verify_image:
#if RCAR_BL2_DCACHE == 1
/* enable */
write_sctlr_el1(read_sctlr_el1() | SCTLR_C_BIT);
write_sctlr_el3(read_sctlr_el3() | SCTLR_C_BIT);
#endif
#endif

1
drivers/renesas/rcar/cpld/ulcb_cpld.c
View File

@ -5,6 +5,7 @@
*/
#include <lib/mmio.h>
#include "ulcb_cpld.h"
#define SCLK 8 /* GP_6_8 */
#define SSTBZ 3 /* GP_2_3 */

12
drivers/renesas/rcar/cpld/ulcb_cpld.h Normal file
View File

@ -0,0 +1,12 @@
/*
* Copyright (c) 2018, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef RCAR_ULCB_CPLD_H__
#define RCAR_ULCB_CPLD_H__
extern void rcar_cpld_reset_cpu(void);
#endif /* RCAR_ULCB_CPLD_H__ */

109
drivers/renesas/rcar/delay/micro_delay.S
View File

@ -1,109 +0,0 @@
/*
* Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <arch.h>
#include <asm_macros.S>
#include "micro_delay.h"
#define CPG_BASE (0xE6150000)
#define CPG_SMSTPCR1 (0x0134)
#define CPG_CPGWPR (0x0900)
/* Module bit for TMU ch3-5 */
#define MSTPCR1_TMU1 (1 << 24)
#define TMU3_BASE (0xE6FC0000)
#define TMU_TSTR (0x0004)
#define TMU_TCOR (0x0008)
#define TMU_TCNT (0x000C)
#define TMU_TCR (0x0010)
/* Start bit for TMU ch3 */
#define TSTR1_TMU3 (1 << 0)
#define MIDR_CA57 (0x0D07 << MIDR_PN_SHIFT)
#define MIDR_CA53 (0x0D03 << MIDR_PN_SHIFT)
.globl rcar_micro_delay
#if (TMU3_MEASUREMENT == 1)
.globl tmu3_init
.globl tmu3_start
.globl tmu3_stop
.globl tcnt3_snapshot
#endif
/* Aligned with the cache line */
.align 6
func rcar_micro_delay
cbz x0, micro_delay_e
mrs x1, midr_el1
and x1, x1, #MIDR_PN_MASK << MIDR_PN_SHIFT
mov w2, #MIDR_CA53
cmp w1, w2
b.eq micro_delay_ca53
b micro_delay_ca57
micro_delay_e:
ret
endfunc rcar_micro_delay
func micro_delay_ca57
ca57_loop_1:
mov x1, #185
ca57_loop_2:
subs x1, x1, #1
b.ne ca57_loop_2
subs x0, x0, #1
b.ne ca57_loop_1
ret
endfunc micro_delay_ca57
func micro_delay_ca53
ca53_loop_1:
mov x1, #134
ca53_loop_2:
subs x1, x1, #1
b.ne ca53_loop_2
subs x0, x0, #1
b.ne ca53_loop_1
ret
endfunc micro_delay_ca53
#if (TMU3_MEASUREMENT == 1)
func tmu3_init
ldr x2, =CPG_BASE
ldr w0, [x2, #CPG_SMSTPCR1]
ldr w1, [x2, #CPG_MSTPSR1]
ldr w2, #MSTPCR1_TMU1
bl mstpcr_write
ret
endfunc tmu3_init
func tmu3_start
ldr x0, =TMU3_BASE
mov w1, #0xFFFFFFFF
str w1, [x0, TMU_TCNT]
ldr x0, =TMU3_BASE
ldrb w1, [x0, TMU_TSTR]
orr w1, w1, #TSTR1_TMU3
strb w1, [x0, TMU_TSTR]
ret
endfunc tmu3_start
func tcnt3_snapshot
ldr x0, =TMU3_BASE
ldr w0, [x0, TMU_TCNT]
ret
endfunc tcnt3_snapshot
func tmu3_stop
ldr x0, =TMU3_BASE
ldrb w1, [x0, TMU_TSTR]
and w1, w1, #~TSTR1_TMU3
strb w1, [x0, TMU_TSTR]
ret
endfunc tmu3_stop
#endif

30
drivers/renesas/rcar/delay/micro_delay.c Normal file
View File

@ -0,0 +1,30 @@
/*
* Copyright (c) 2018, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <arch.h>
#include <arch_helpers.h>
#include "micro_delay.h"
#define RCAR_CONV_MICROSEC 1000000U
void
#if IMAGE_BL31
__attribute__ ((section (".system_ram")))
#endif
rcar_micro_delay(uint64_t micro_sec)
{
uint64_t freq;
uint64_t base_count;
uint64_t get_count;
uint64_t wait_time = 0U;
freq = read_cntfrq_el0();
base_count = read_cntpct_el0();
while (micro_sec > wait_time) {
get_count = read_cntpct_el0();
wait_time = ((get_count - base_count) * RCAR_CONV_MICROSEC) / freq;
}
}

13
drivers/renesas/rcar/delay/micro_delay.h
View File

@ -7,20 +7,9 @@
#ifndef MICRO_DELAY_H
#define MICRO_DELAY_H
#define TMU3_MEASUREMENT (0)
#ifndef __ASSEMBLY__
#include <stdint.h>
void rcar_micro_delay(uint32_t count_us);
#if (TMU3_MEASUREMENT == 1)
void tmu3_start(void);
void tmu3_init(void);
void tmu3_stop(void);
uint32_t tcnt3_snapshot(void);
#endif
void rcar_micro_delay(uint64_t micro_sec);
#endif
#endif /* MICRO_DELAY_H */

28
drivers/renesas/rcar/pwrc/pwrc.c
View File

@ -17,6 +17,7 @@
#include "iic_dvfs.h"
#include "rcar_def.h"
#include "rcar_private.h"
#include "micro_delay.h"
#include "pwrc.h"
/*
@ -122,7 +123,6 @@ RCAR_INSTANTIATE_LOCK
#define RST_BASE (0xE6160000U)
#define RST_MODEMR (RST_BASE + 0x0060U)
#define RST_MODEMR_BIT0 (0x00000001U)
#define RCAR_CONV_MICROSEC (1000000U)
#if PMIC_ROHM_BD9571
#define BIT_BKUP_CTRL_OUT ((uint8_t)(1U << 4))
@ -143,23 +143,6 @@ IMPORT_SYM(unsigned long, __system_ram_end__, SYSTEM_RAM_END);
IMPORT_SYM(unsigned long, __SRAM_COPY_START__, SRAM_COPY_START);
#endif
#if RCAR_SYSTEM_SUSPEND
static void __attribute__ ((section (".system_ram")))
rcar_pwrc_micro_delay(uint64_t micro_sec)
{
uint64_t freq, base, val;
uint64_t wait_time = 0;
freq = read_cntfrq_el0();
base = read_cntpct_el0();
while (micro_sec > wait_time) {
val = read_cntpct_el0() - base;
wait_time = val * RCAR_CONV_MICROSEC / freq;
}
}
#endif
uint32_t rcar_pwrc_status(uint64_t mpidr)
{
uint32_t ret = 0;
@ -414,7 +397,7 @@ self_refresh:
mmio_write_32(DBSC4_REG_DBACEN, 0);
if (product == RCAR_PRODUCT_H3 && cut < RCAR_CUT_VER20)
rcar_pwrc_micro_delay(100);
rcar_micro_delay(100);
else if (product == RCAR_PRODUCT_H3) {
mmio_write_32(DBSC4_REG_DBCAM0CTRL0, 1);
DBCAM_FLUSH(0);
@ -465,7 +448,7 @@ self_refresh:
/* Set the auto-refresh enable register */
mmio_write_32(DBSC4_REG_DBRFEN, 0U);
rcar_pwrc_micro_delay(1U);
rcar_micro_delay(1U);
if (product == RCAR_PRODUCT_M3)
return;
@ -650,7 +633,6 @@ void rcar_pwrc_set_suspend_to_ram(void)
DEVICE_SRAM_STACK_SIZE);
uint32_t sctlr;
rcar_pwrc_code_copy_to_system_ram();
rcar_pwrc_save_generic_timer(rcar_stack_generic_timer);
/* disable MMU */
@ -665,10 +647,7 @@ void rcar_pwrc_init_suspend_to_ram(void)
{
#if PMIC_ROHM_BD9571
uint8_t mode;
#endif
rcar_pwrc_code_copy_to_system_ram();
#if PMIC_ROHM_BD9571
if (rcar_iic_dvfs_receive(PMIC, PMIC_BKUP_MODE_CNT, &mode))
panic();
@ -683,7 +662,6 @@ void rcar_pwrc_suspend_to_ram(void)
#if RCAR_SYSTEM_RESET_KEEPON_DDR
int32_t error;
rcar_pwrc_code_copy_to_system_ram();
error = rcar_iic_dvfs_send(PMIC, REG_KEEP10, 0);
if (error) {
ERROR("Failed send KEEP10 init ret=%d \n", error);

19
drivers/renesas/rcar/scif/scif.S
View File

@ -75,6 +75,8 @@
#if SCIF_CLK == SCIF_EXTARNAL_CLK
#define SCSCR_CKE_INT_CLK (SCSCR_CKE_BRG)
#else
#define SCFSR_TEND_MASK (1 << 6)
#define SCFSR_TEND_TRANS_END (0x0040)
#define SCSCR_CKE_INT_CLK (SCSCR_CKE_INT)
#endif
#define SCFSR_INIT_DATA (0x0000)
@ -281,6 +283,11 @@ func console_core_putc
bcs 2b
strb w0, [x1, #SCIF_SCFTDR]
/* Clear TEND flag */
ldrh w2, [x1, #SCIF_SCFSR]
and w2, w2, #~SCFSR_TEND_MASK
strh w2, [x1, #SCIF_SCFSR]
ret
endfunc console_core_putc
@ -309,16 +316,12 @@ endfunc console_getc
func console_flush
ldr x0, =SCIF2_BASE
1:
ldrh w1, [x0, #SCIF_SCFDR]
ubfx w1, w1, #8, #5
cmp w1, #0
/* Check TEND flag */
ldrh w1, [x0, #SCIF_SCFSR]
and w1, w1, #SCFSR_TEND_MASK
cmp w1, #SCFSR_TEND_TRANS_END
bne 1b
mov x0, #100
mov x3, x30
bl rcar_micro_delay
mov x30, x3
ldr x0, =SCIF2_BASE
ldrh w1, [x0, #SCIF_SCSCR]
and w1, w1, #~(SCSCR_TE_EN + SCSCR_RE_EN)

4
drivers/renesas/rcar/watchdog/swdt.c
View File

@ -133,7 +133,11 @@ void rcar_swdt_release(void)
(ARM_IRQ_SEC_WDT & ~ITARGET_MASK);
uint32_t i;
/* Disable FIQ interrupt */
write_daifset(DAIF_FIQ_BIT);
/* FIQ interrupts are not taken to EL3 */
write_scr_el3(read_scr_el3() & ~SCR_FIQ_BIT);
swdt_disable();
gicv2_cpuif_disable();

2141
drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_e3.c
View File

File diff suppressed because it is too large Load Diff

2
drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_e3.h
View File

@ -9,7 +9,7 @@
#include <stdint.h>
#define RCAR_E3_DDR_VERSION "rev.0.09"
#define RCAR_E3_DDR_VERSION "rev.0.11"
#ifdef ddr_qos_init_setting
#define REFRESH_RATE 3900 /* Average periodic refresh interval[ns]. Support 3900,7800 */

688
drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram.c
View File

File diff suppressed because it is too large Load Diff

119
drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram_config.c
View File

@ -4,24 +4,33 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
#define BOARDNUM 16
#define BOARDNUM 18
#define BOARD_JUDGE_AUTO
#ifdef BOARD_JUDGE_AUTO
static uint32_t _board_judge(void);
static uint32_t boardcnf_get_brd_type(void)
{
return _board_judge();
}
#else
static uint32_t boardcnf_get_brd_type(void)
{
return (1);
}
#endif
#define DDR_FAST_INIT
struct _boardcnf_ch {
uint8_t ddr_density[CS_CNT];
uint32_t ca_swap;
uint64_t ca_swap;
uint16_t dqs_swap;
uint32_t dq_swap[SLICE_CNT];
uint8_t dm_swap[SLICE_CNT];
uint16_t wdqlvl_patt[16];
int8_t cacs_adj[10];
int8_t cacs_adj[16];
int8_t dm_adj_w[SLICE_CNT];
int8_t dq_adj_w[SLICE_CNT * 8];
int8_t dm_adj_r[SLICE_CNT];
@ -876,7 +885,11 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = {
0x0a0,
{
{
#if (RCAR_DRAM_LPDDR4_MEMCONF == 2)
{0x04, 0x04},
#else
{0x02, 0x02},
#endif
0x00342501,
0x3201,
{0x10672534, 0x43257106, 0x34527601, 0x71605243},
@ -1227,7 +1240,89 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = {
0, 0, 0, 0, 0, 0, 0, 0}
}
}
},
/* boardcnf[16] RENESAS KRIEK-P2P board with M3-W/SoC */
{
0x03,
0x01,
0x0320,
0,
0x0300,
0x00a0,
{
{
{0x04, 0x04},
0x520314FFFF523041,
0x3201,
{0x01672543, 0x45361207, 0x45632107, 0x60715234},
{0x08, 0x08, 0x08, 0x08},
WDQLVL_PAT,
{0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0}
},
{
{0x04, 0x04},
0x314250FFFF312405,
0x2310,
{0x01672543, 0x45361207, 0x45632107, 0x60715234},
{0x08, 0x08, 0x08, 0x08},
WDQLVL_PAT,
{0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0}
}
}
},
/* boardcnf[17] RENESAS KRIEK-P2P board with M3-N/SoC */
{
0x01,
0x01,
0x0300,
0,
0x0300,
0x00a0,
{
{
{0x04, 0x04},
0x520314FFFF523041,
0x3201,
{0x01672543, 0x45361207, 0x45632107, 0x60715234},
{0x08, 0x08, 0x08, 0x08},
WDQLVL_PAT,
{0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0}
}
}
}
};
void boardcnf_get_brd_clk(uint32_t brd, uint32_t * clk, uint32_t * div)
@ -1258,6 +1353,7 @@ void boardcnf_get_brd_clk(uint32_t brd, uint32_t * clk, uint32_t * div)
break;
}
}
(void)brd;
}
void boardcnf_get_ddr_mbps(uint32_t brd, uint32_t * mbps, uint32_t * div)
@ -1284,6 +1380,7 @@ void boardcnf_get_ddr_mbps(uint32_t brd, uint32_t * mbps, uint32_t * div)
*div = 1;
break;
}
(void)brd;
}
#define _def_REFPERIOD 1890
@ -1393,10 +1490,10 @@ static uint32_t opencheck_SSI_WS6(void)
if (down == up) {
/* Same = Connect */
return 0;
} else {
/* Diff = Open */
return 1;
}
/* Diff = Open */
return 1;
}
#endif
@ -1431,6 +1528,7 @@ static uint32_t _board_judge(void)
usb2_ovc_open = opencheck_SSI_WS6();
/* RENESAS Eva-borad */
brd = 99;
if (Prr_Product == PRR_PRODUCT_V3H) {
/* RENESAS Condor board */
brd = 12;
@ -1441,10 +1539,12 @@ static uint32_t _board_judge(void)
} else if (Prr_Product == PRR_PRODUCT_M3) {
/* RENESAS Kriek board with M3-W */
brd = 1;
} else if (Prr_Cut <= PRR_PRODUCT_11) {
} else if ((Prr_Product == PRR_PRODUCT_H3)
&& (Prr_Cut<=PRR_PRODUCT_11)) {
/* RENESAS Kriek board with PM3 */
brd = 13;
} else {
} else if ((Prr_Product == PRR_PRODUCT_H3)
&& (Prr_Cut > PRR_PRODUCT_20)) {
/* RENESAS Kriek board with H3N */
brd = 15;
}
@ -1467,12 +1567,13 @@ static uint32_t _board_judge(void)
} else if (Prr_Product == PRR_PRODUCT_M3N) {
/* RENESAS SALVATOR-X (M3-N/SIP) */
brd = 11;
} else {
} else if (Prr_Product == PRR_PRODUCT_M3) {
/* RENESAS SALVATOR-X (M3-W/SIP) */
brd = 0;
}
}
#endif
return brd;
}
#endif

2
drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram_regdef.h
View File

@ -4,7 +4,7 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
#define RCAR_DDR_VERSION "rev.0.33"
#define RCAR_DDR_VERSION "rev.0.34"
#define DRAM_CH_CNT (0x04)
#define SLICE_CNT (0x04)
#define CS_CNT (0x02)

2
drivers/staging/renesas/rcar/ddr/ddr_b/init_dram_tbl_m3n.h
View File

@ -267,7 +267,7 @@ static const uint32_t DDR_PHY_ADR_G_REGSET_M3N[DDR_PHY_ADR_G_REGSET_NUM_M3N] = {
/*0bb9*/ 0x00000000,
/*0bba*/ 0x00000000,
/*0bbb*/ 0x00000000,
/*0bbc*/ 0x00000065,
/*0bbc*/ 0x00000265,
/*0bbd*/ 0x00000000,
/*0bbe*/ 0x00040401,
/*0bbf*/ 0x00000000,

124
drivers/staging/renesas/rcar/ddr/dram_sub_func.c
View File

@ -19,10 +19,11 @@
#define PRR_PRODUCT_V3H (0x00005600U) /* R-Car V3H */
#if RCAR_SYSTEM_SUSPEND
#include "iic_dvfs.h"
/* Local defines */
#define DRAM_BACKUP_GPIO_USE (0)
#include "iic_dvfs.h"
#if PMIC_ROHM_BD9571
#define PMIC_SLAVE_ADDR (0x30U)
#define PMIC_BKUP_MODE_CNT (0x20U)
#define PMIC_QLLM_CNT (0x27U)
#define BIT_BKUP_CTRL_OUT ((uint8_t)(1U << 4U))
@ -52,40 +53,53 @@
void rcar_dram_get_boot_status(uint32_t * status)
{
#if RCAR_SYSTEM_SUSPEND
uint32_t shift = GPIO_BKUP_TRG_SHIFT_SALVATOR;
uint32_t gpio = GPIO_INDT1;
uint32_t reg, product;
uint32_t reg_data;
uint32_t product;
uint32_t shift;
uint32_t gpio;
product = mmio_read_32(PRR) & PRR_PRODUCT_MASK;
if (product == PRR_PRODUCT_V3H) {
shift = GPIO_BKUP_TRG_SHIFT_CONDOR;
gpio = GPIO_INDT3;
} else if (product == PRR_PRODUCT_E3) {
shift = GPIO_BKUP_TRG_SHIFT_EBISU;
gpio = GPIO_INDT6;
} else {
shift = GPIO_BKUP_TRG_SHIFT_SALVATOR;
gpio = GPIO_INDT1;
}
reg = mmio_read_32(gpio) & (1U << shift);
*status = reg ? DRAM_BOOT_STATUS_WARM : DRAM_BOOT_STATUS_COLD;
#else
reg_data = mmio_read_32(gpio);
if (0U != (reg_data & ((uint32_t)1U << shift))) {
*status = DRAM_BOOT_STATUS_WARM;
} else {
*status = DRAM_BOOT_STATUS_COLD;
}
#else /* RCAR_SYSTEM_SUSPEND */
*status = DRAM_BOOT_STATUS_COLD;
#endif
#endif /* RCAR_SYSTEM_SUSPEND */
}
int32_t rcar_dram_update_boot_status(uint32_t status)
{
int32_t ret = 0;
#if RCAR_SYSTEM_SUSPEND
uint32_t reg_data;
#if PMIC_ROHM_BD9571
#if DRAM_BACKUP_GPIO_USE == 0
uint8_t mode = 0U;
uint8_t bkup_mode_cnt = 0U;
#else
uint32_t reqb, outd;
#endif
uint8_t qllm = 0;
uint8_t qllm_cnt = 0U;
int32_t i2c_dvfs_ret = -1;
#endif
uint32_t i, product, trg, gpio;
uint32_t loop_count;
uint32_t product;
uint32_t trg;
uint32_t gpio;
product = mmio_read_32(PRR) & PRR_PRODUCT_MASK;
if (product == PRR_PRODUCT_V3H) {
@ -111,50 +125,58 @@ int32_t rcar_dram_update_boot_status(uint32_t status)
gpio = GPIO_INDT1;
}
if (status != DRAM_BOOT_STATUS_WARM)
goto cold;
if (status == DRAM_BOOT_STATUS_WARM) {
#if DRAM_BACKUP_GPIO_USE==1
mmio_setbits_32(outd, 1U << reqb);
#else
#if PMIC_ROHM_BD9571
if (rcar_iic_dvfs_receive(PMIC, PMIC_BKUP_MODE_CNT, &mode)) {
ERROR("BKUP mode cnt READ ERROR.\n");
return DRAM_UPDATE_STATUS_ERR;
/* Set BKUP_CRTL_OUT=High (BKUP mode cnt register) */
i2c_dvfs_ret = rcar_iic_dvfs_receive(PMIC_SLAVE_ADDR,
PMIC_BKUP_MODE_CNT, &bkup_mode_cnt);
if (0 != i2c_dvfs_ret) {
ERROR("BKUP mode cnt READ ERROR.\n");
ret = DRAM_UPDATE_STATUS_ERR;
} else {
bkup_mode_cnt &= (uint8_t)~BIT_BKUP_CTRL_OUT;
i2c_dvfs_ret = rcar_iic_dvfs_send(PMIC_SLAVE_ADDR,
PMIC_BKUP_MODE_CNT, bkup_mode_cnt);
if (0 != i2c_dvfs_ret) {
ERROR("BKUP mode cnt WRITE ERROR. "
"value = %d\n", bkup_mode_cnt);
ret = DRAM_UPDATE_STATUS_ERR;
}
}
#endif /* PMIC_ROHM_BD9571 */
#endif /* DRAM_BACKUP_GPIO_USE==1 */
/* Wait BKUP_TRG=Low */
loop_count = DRAM_BKUP_TRG_LOOP_CNT;
while (0U < loop_count) {
reg_data = mmio_read_32(gpio);
if ((reg_data &
((uint32_t)1U << trg)) == 0U) {
break;
}
loop_count--;
}
if (0U == loop_count) {
ERROR( "\nWarm booting...\n" \
" The potential of BKUP_TRG did not switch " \
"to Low.\n If you expect the operation of " \
"cold boot,\n check the board configuration" \
" (ex, Dip-SW) and/or the H/W failure.\n");
ret = DRAM_UPDATE_STATUS_ERR;
}
}
mode &= ~BIT_BKUP_CTRL_OUT;
if (rcar_iic_dvfs_send(PMIC, PMIC_BKUP_MODE_CNT, mode)) {
ERROR("BKUP mode cnt WRITE ERROR. value = %d\n", mode);
return DRAM_UPDATE_STATUS_ERR;
}
#endif
#endif
for (i = 0; i < DRAM_BKUP_TRG_LOOP_CNT; i++) {
if (mmio_read_32(gpio) & (1U << trg))
continue;
goto cold;
}
ERROR("\nWarm booting Error...\n"
" The potential of BKUP_TRG did not switch "
"to Low.\n If you expect the operation of "
"cold boot,\n check the board configuration"
" (ex, Dip-SW) and/or the H/W failure.\n");
return DRAM_UPDATE_STATUS_ERR;
cold:
#if PMIC_ROHM_BD9571
if (ret)
return ret;
qllm = (BIT_QLLM_DDR0_EN | BIT_QLLM_DDR1_EN);
if (rcar_iic_dvfs_send(PMIC, PMIC_QLLM_CNT, qllm)) {
ERROR("QLLM cnt WRITE ERROR. value = %d\n", qllm);
ret = DRAM_UPDATE_STATUS_ERR;
if(0 == ret) {
qllm_cnt = (BIT_QLLM_DDR0_EN | BIT_QLLM_DDR1_EN);
i2c_dvfs_ret = rcar_iic_dvfs_send(PMIC_SLAVE_ADDR,
PMIC_QLLM_CNT, qllm_cnt);
if (0 != i2c_dvfs_ret) {
ERROR("QLLM cnt WRITE ERROR. "
"value = %d\n", qllm_cnt);
ret = DRAM_UPDATE_STATUS_ERR;
}
}
#endif
#endif

211
drivers/staging/renesas/rcar/pfc/E3/pfc_init_e3.c
View File

@ -490,7 +490,8 @@ void pfc_init_e3(void)
| MOD_SEL0_REMOCON_A
| MOD_SEL0_SCIF_A
| MOD_SEL0_SCIF0_A
| MOD_SEL0_SCIF2_A | MOD_SEL0_SPEED_PULSE_IF_A);
| MOD_SEL0_SCIF2_A
| MOD_SEL0_SPEED_PULSE_IF_A);
pfc_reg_write(PFC_MOD_SEL1, MOD_SEL1_SIMCARD_A
| MOD_SEL1_SSI2_A
| MOD_SEL1_TIMER_TMU_A
@ -507,135 +508,137 @@ void pfc_init_e3(void)
| MOD_SEL1_SCIF4_A
| MOD_SEL1_SCIF5_A
| MOD_SEL1_VIN4_A
| MOD_SEL1_VIN5_A | MOD_SEL1_ADGC_A | MOD_SEL1_SSI9_A);
| MOD_SEL1_VIN5_A
| MOD_SEL1_ADGC_A
| MOD_SEL1_SSI9_A);
/* initialize peripheral function select */
pfc_reg_write(PFC_IPSR0, IPSR_28_FUNC(0) /* QSPI1_MISO/IO1 */
|IPSR_24_FUNC(0) /* QSPI1_MOSI/IO0 */
|IPSR_20_FUNC(0) /* QSPI1_SPCLK */
|IPSR_16_FUNC(0) /* QSPI0_IO3 */
|IPSR_12_FUNC(0) /* QSPI0_IO2 */
|IPSR_8_FUNC(0) /* QSPI0_MISO/IO1 */
|IPSR_4_FUNC(0) /* QSPI0_MOSI/IO0 */
|IPSR_0_FUNC(0)); /* QSPI0_SPCLK */
| IPSR_24_FUNC(0) /* QSPI1_MOSI/IO0 */
| IPSR_20_FUNC(0) /* QSPI1_SPCLK */
| IPSR_16_FUNC(0) /* QSPI0_IO3 */
| IPSR_12_FUNC(0) /* QSPI0_IO2 */
| IPSR_8_FUNC(0) /* QSPI0_MISO/IO1 */
| IPSR_4_FUNC(0) /* QSPI0_MOSI/IO0 */
| IPSR_0_FUNC(0)); /* QSPI0_SPCLK */
pfc_reg_write(PFC_IPSR1, IPSR_28_FUNC(0) /* AVB_RD2 */
|IPSR_24_FUNC(0) /* AVB_RD1 */
|IPSR_20_FUNC(0) /* AVB_RD0 */
|IPSR_16_FUNC(0) /* RPC_RESET# */
|IPSR_12_FUNC(0) /* RPC_INT# */
|IPSR_8_FUNC(0) /* QSPI1_SSL */
|IPSR_4_FUNC(0) /* QSPI1_IO3 */
|IPSR_0_FUNC(0)); /* QSPI1_IO2 */
| IPSR_24_FUNC(0) /* AVB_RD1 */
| IPSR_20_FUNC(0) /* AVB_RD0 */
| IPSR_16_FUNC(0) /* RPC_RESET# */
| IPSR_12_FUNC(0) /* RPC_INT# */
| IPSR_8_FUNC(0) /* QSPI1_SSL */
| IPSR_4_FUNC(0) /* QSPI1_IO3 */
| IPSR_0_FUNC(0)); /* QSPI1_IO2 */
pfc_reg_write(PFC_IPSR2, IPSR_28_FUNC(1) /* IRQ0 */
|IPSR_24_FUNC(0)
| IPSR_24_FUNC(0)
| IPSR_20_FUNC(0)
| IPSR_16_FUNC(2) /* AVB_LINK */
|IPSR_12_FUNC(0)
| IPSR_12_FUNC(0)
| IPSR_8_FUNC(0) /* AVB_MDC */
|IPSR_4_FUNC(0) /* AVB_MDIO */
|IPSR_0_FUNC(0)); /* AVB_TXCREFCLK */
| IPSR_4_FUNC(0) /* AVB_MDIO */
| IPSR_0_FUNC(0)); /* AVB_TXCREFCLK */
pfc_reg_write(PFC_IPSR3, IPSR_28_FUNC(5) /* DU_HSYNC */
|IPSR_24_FUNC(0)
| IPSR_24_FUNC(0)
| IPSR_20_FUNC(0)
| IPSR_16_FUNC(0)
| IPSR_12_FUNC(5) /* DU_DG4 */
|IPSR_8_FUNC(5) /* DU_DOTCLKOUT0 */
|IPSR_4_FUNC(5) /* DU_DISP */
|IPSR_0_FUNC(1)); /* IRQ1 */
| IPSR_8_FUNC(5) /* DU_DOTCLKOUT0 */
| IPSR_4_FUNC(5) /* DU_DISP */
| IPSR_0_FUNC(1)); /* IRQ1 */
pfc_reg_write(PFC_IPSR4, IPSR_28_FUNC(5) /* DU_DB5 */
|IPSR_24_FUNC(5) /* DU_DB4 */
|IPSR_20_FUNC(5) /* DU_DB3 */
|IPSR_16_FUNC(5) /* DU_DB2 */
|IPSR_12_FUNC(5) /* DU_DG6 */
|IPSR_8_FUNC(5) /* DU_VSYNC */
|IPSR_4_FUNC(5) /* DU_DG5 */
|IPSR_0_FUNC(5)); /* DU_DG7 */
| IPSR_24_FUNC(5) /* DU_DB4 */
| IPSR_20_FUNC(5) /* DU_DB3 */
| IPSR_16_FUNC(5) /* DU_DB2 */
| IPSR_12_FUNC(5) /* DU_DG6 */
| IPSR_8_FUNC(5) /* DU_VSYNC */
| IPSR_4_FUNC(5) /* DU_DG5 */
| IPSR_0_FUNC(5)); /* DU_DG7 */
pfc_reg_write(PFC_IPSR5, IPSR_28_FUNC(5) /* DU_DR3 */
|IPSR_24_FUNC(5) /* DU_DB7 */
|IPSR_20_FUNC(5) /* DU_DR2 */
|IPSR_16_FUNC(5) /* DU_DR1 */
|IPSR_12_FUNC(5) /* DU_DR0 */
|IPSR_8_FUNC(5) /* DU_DB1 */
|IPSR_4_FUNC(5) /* DU_DB0 */
|IPSR_0_FUNC(5)); /* DU_DB6 */
| IPSR_24_FUNC(5) /* DU_DB7 */
| IPSR_20_FUNC(5) /* DU_DR2 */
| IPSR_16_FUNC(5) /* DU_DR1 */
| IPSR_12_FUNC(5) /* DU_DR0 */
| IPSR_8_FUNC(5) /* DU_DB1 */
| IPSR_4_FUNC(5) /* DU_DB0 */
| IPSR_0_FUNC(5)); /* DU_DB6 */
pfc_reg_write(PFC_IPSR6, IPSR_28_FUNC(5) /* DU_DG1 */
|IPSR_24_FUNC(5) /* DU_DG0 */
|IPSR_20_FUNC(5) /* DU_DR7 */
|IPSR_16_FUNC(2) /* IRQ5 */
|IPSR_12_FUNC(5) /* DU_DR6 */
|IPSR_8_FUNC(5) /* DU_DR5 */
|IPSR_4_FUNC(0)
| IPSR_24_FUNC(5) /* DU_DG0 */
| IPSR_20_FUNC(5) /* DU_DR7 */
| IPSR_16_FUNC(2) /* IRQ5 */
| IPSR_12_FUNC(5) /* DU_DR6 */
| IPSR_8_FUNC(5) /* DU_DR5 */
| IPSR_4_FUNC(0)
| IPSR_0_FUNC(5)); /* DU_DR4 */
pfc_reg_write(PFC_IPSR7, IPSR_28_FUNC(0) /* SD0_CLK */
|IPSR_24_FUNC(0)
| IPSR_24_FUNC(0)
| IPSR_20_FUNC(5) /* DU_DOTCLKIN0 */
|IPSR_16_FUNC(5) /* DU_DG3 */
|IPSR_12_FUNC(0)
| IPSR_16_FUNC(5) /* DU_DG3 */
| IPSR_12_FUNC(0)
| IPSR_8_FUNC(0)
| IPSR_4_FUNC(0)
| IPSR_0_FUNC(5)); /* DU_DG2 */
pfc_reg_write(PFC_IPSR8, IPSR_28_FUNC(0) /* SD1_DAT0 */
|IPSR_24_FUNC(0) /* SD1_CMD */
|IPSR_20_FUNC(0) /* SD1_CLK */
|IPSR_16_FUNC(0) /* SD0_DAT3 */
|IPSR_12_FUNC(0) /* SD0_DAT2 */
|IPSR_8_FUNC(0) /* SD0_DAT1 */
|IPSR_4_FUNC(0) /* SD0_DAT0 */
|IPSR_0_FUNC(0)); /* SD0_CMD */
| IPSR_24_FUNC(0) /* SD1_CMD */
| IPSR_20_FUNC(0) /* SD1_CLK */
| IPSR_16_FUNC(0) /* SD0_DAT3 */
| IPSR_12_FUNC(0) /* SD0_DAT2 */
| IPSR_8_FUNC(0) /* SD0_DAT1 */
| IPSR_4_FUNC(0) /* SD0_DAT0 */
| IPSR_0_FUNC(0)); /* SD0_CMD */
pfc_reg_write(PFC_IPSR9, IPSR_28_FUNC(0) /* SD3_DAT2 */
|IPSR_24_FUNC(0) /* SD3_DAT1 */
|IPSR_20_FUNC(0) /* SD3_DAT0 */
|IPSR_16_FUNC(0) /* SD3_CMD */
|IPSR_12_FUNC(0) /* SD3_CLK */
|IPSR_8_FUNC(0) /* SD1_DAT3 */
|IPSR_4_FUNC(0) /* SD1_DAT2 */
|IPSR_0_FUNC(0)); /* SD1_DAT1 */
| IPSR_24_FUNC(0) /* SD3_DAT1 */
| IPSR_20_FUNC(0) /* SD3_DAT0 */
| IPSR_16_FUNC(0) /* SD3_CMD */
| IPSR_12_FUNC(0) /* SD3_CLK */
| IPSR_8_FUNC(0) /* SD1_DAT3 */
| IPSR_4_FUNC(0) /* SD1_DAT2 */
| IPSR_0_FUNC(0)); /* SD1_DAT1 */
pfc_reg_write(PFC_IPSR10, IPSR_28_FUNC(0) /* SD0_WP */
|IPSR_24_FUNC(0) /* SD0_CD */
|IPSR_20_FUNC(0) /* SD3_DS */
|IPSR_16_FUNC(0) /* SD3_DAT7 */
|IPSR_12_FUNC(0) /* SD3_DAT6 */
|IPSR_8_FUNC(0) /* SD3_DAT5 */
|IPSR_4_FUNC(0) /* SD3_DAT4 */
|IPSR_0_FUNC(0)); /* SD3_DAT3 */
| IPSR_24_FUNC(0) /* SD0_CD */
| IPSR_20_FUNC(0) /* SD3_DS */
| IPSR_16_FUNC(0) /* SD3_DAT7 */
| IPSR_12_FUNC(0) /* SD3_DAT6 */
| IPSR_8_FUNC(0) /* SD3_DAT5 */
| IPSR_4_FUNC(0) /* SD3_DAT4 */
| IPSR_0_FUNC(0)); /* SD3_DAT3 */
pfc_reg_write(PFC_IPSR11, IPSR_28_FUNC(0)
| IPSR_24_FUNC(0)
| IPSR_20_FUNC(2) /* AUDIO_CLKOUT1_A */
|IPSR_16_FUNC(2) /* AUDIO_CLKOUT_A */
|IPSR_12_FUNC(0)
| IPSR_16_FUNC(2) /* AUDIO_CLKOUT_A */
| IPSR_12_FUNC(0)
| IPSR_8_FUNC(0)
| IPSR_4_FUNC(0) /* SD1_WP */
|IPSR_0_FUNC(0)); /* SD1_CD */
| IPSR_0_FUNC(0)); /* SD1_CD */
pfc_reg_write(PFC_IPSR12, IPSR_28_FUNC(0)
| IPSR_24_FUNC(0)
| IPSR_20_FUNC(0)
| IPSR_16_FUNC(0)
| IPSR_12_FUNC(0) /* RX2_A */
|IPSR_8_FUNC(0) /* TX2_A */
|IPSR_4_FUNC(2) /* AUDIO_CLKB_A */
|IPSR_0_FUNC(0));
| IPSR_8_FUNC(0) /* TX2_A */
| IPSR_4_FUNC(2) /* AUDIO_CLKB_A */
| IPSR_0_FUNC(0));
pfc_reg_write(PFC_IPSR13, IPSR_28_FUNC(0)
| IPSR_24_FUNC(0)
| IPSR_20_FUNC(0)
| IPSR_16_FUNC(0)
| IPSR_12_FUNC(0)
| IPSR_8_FUNC(2) /* AUDIO_CLKC_A */
|IPSR_4_FUNC(1) /* HTX2_A */
|IPSR_0_FUNC(1)); /* HRX2_A */
| IPSR_4_FUNC(1) /* HTX2_A */
| IPSR_0_FUNC(1)); /* HRX2_A */
pfc_reg_write(PFC_IPSR14, IPSR_28_FUNC(3) /* USB0_PWEN_B */
|IPSR_24_FUNC(0) /* SSI_SDATA4 */
|IPSR_20_FUNC(0) /* SSI_SDATA3 */
|IPSR_16_FUNC(0) /* SSI_WS349 */
|IPSR_12_FUNC(0) /* SSI_SCK349 */
|IPSR_8_FUNC(0)
| IPSR_24_FUNC(0) /* SSI_SDATA4 */
| IPSR_20_FUNC(0) /* SSI_SDATA3 */
| IPSR_16_FUNC(0) /* SSI_WS349 */
| IPSR_12_FUNC(0) /* SSI_SCK349 */
| IPSR_8_FUNC(0)
| IPSR_4_FUNC(0) /* SSI_SDATA1 */
|IPSR_0_FUNC(0)); /* SSI_SDATA0 */
| IPSR_0_FUNC(0)); /* SSI_SDATA0 */
pfc_reg_write(PFC_IPSR15, IPSR_28_FUNC(0) /* USB30_OVC */
|IPSR_24_FUNC(0) /* USB30_PWEN */
|IPSR_20_FUNC(0) /* AUDIO_CLKA */
|IPSR_16_FUNC(1) /* HRTS2#_A */
|IPSR_12_FUNC(1) /* HCTS2#_A */
|IPSR_8_FUNC(0)
| IPSR_24_FUNC(0) /* USB30_PWEN */
| IPSR_20_FUNC(0) /* AUDIO_CLKA */
| IPSR_16_FUNC(1) /* HRTS2#_A */
| IPSR_12_FUNC(1) /* HCTS2#_A */
| IPSR_8_FUNC(0)
| IPSR_4_FUNC(0)
| IPSR_0_FUNC(3)); /* USB0_OVC_B */
@ -648,7 +651,11 @@ void pfc_init_e3(void)
| GPSR0_D8
| GPSR0_D7
| GPSR0_D6
| GPSR0_D5 | GPSR0_D3 | GPSR0_D2 | GPSR0_D1 | GPSR0_D0);
| GPSR0_D5
| GPSR0_D3
| GPSR0_D2
| GPSR0_D1
| GPSR0_D0);
pfc_reg_write(PFC_GPSR1, GPSR1_WE0
| GPSR1_CS0
| GPSR1_A19
@ -663,7 +670,11 @@ void pfc_init_e3(void)
| GPSR1_A10
| GPSR1_A9
| GPSR1_A8
| GPSR1_A4 | GPSR1_A3 | GPSR1_A2 | GPSR1_A1 | GPSR1_A0);
| GPSR1_A4
| GPSR1_A3
| GPSR1_A2
| GPSR1_A1
| GPSR1_A0);
pfc_reg_write(PFC_GPSR2, GPSR2_BIT27_REVERCED
| GPSR2_BIT26_REVERCED
| GPSR2_RD
@ -687,7 +698,8 @@ void pfc_init_e3(void)
| GPSR2_QSPI0_IO3
| GPSR2_QSPI0_IO2
| GPSR2_QSPI0_MISO_IO1
| GPSR2_QSPI0_MOSI_IO0 | GPSR2_QSPI0_SPCLK);
| GPSR2_QSPI0_MOSI_IO0
| GPSR2_QSPI0_SPCLK);
pfc_reg_write(PFC_GPSR3, GPSR3_SD1_WP
| GPSR3_SD1_CD
| GPSR3_SD0_WP
@ -701,7 +713,9 @@ void pfc_init_e3(void)
| GPSR3_SD0_DAT3
| GPSR3_SD0_DAT2
| GPSR3_SD0_DAT1
| GPSR3_SD0_DAT0 | GPSR3_SD0_CMD | GPSR3_SD0_CLK);
| GPSR3_SD0_DAT0
| GPSR3_SD0_CMD
| GPSR3_SD0_CLK);
pfc_reg_write(PFC_GPSR4, GPSR4_SD3_DS
| GPSR4_SD3_DAT7
| GPSR4_SD3_DAT6
@ -710,13 +724,17 @@ void pfc_init_e3(void)
| GPSR4_SD3_DAT3
| GPSR4_SD3_DAT2
| GPSR4_SD3_DAT1
| GPSR4_SD3_DAT0 | GPSR4_SD3_CMD | GPSR4_SD3_CLK);
| GPSR4_SD3_DAT0
| GPSR4_SD3_CMD
| GPSR4_SD3_CLK);
pfc_reg_write(PFC_GPSR5, GPSR5_SSI_SDATA9
| GPSR5_MSIOF0_SS2
| GPSR5_MSIOF0_SS1
| GPSR5_RX2_A
| GPSR5_TX2_A
| GPSR5_SCK2_A | GPSR5_RTS0_TANS_A | GPSR5_CTS0_A);
| GPSR5_SCK2_A
| GPSR5_RTS0_TANS_A
| GPSR5_CTS0_A);
pfc_reg_write(PFC_GPSR6, GPSR6_USB30_PWEN
| GPSR6_SSI_SDATA6
| GPSR6_SSI_WS6
@ -730,7 +748,8 @@ void pfc_init_e3(void)
| GPSR6_SSI_SCK349
| GPSR6_SSI_SDATA1
| GPSR6_SSI_SDATA0
| GPSR6_SSI_WS01239 | GPSR6_SSI_SCK01239);
| GPSR6_SSI_WS01239
| GPSR6_SSI_SCK01239);
/* initialize POC control */
reg = mmio_read_32(PFC_IOCTRL30);
@ -743,7 +762,9 @@ void pfc_init_e3(void)
| POC_SD0_DAT3_33V
| POC_SD0_DAT2_33V
| POC_SD0_DAT1_33V
| POC_SD0_DAT0_33V | POC_SD0_CMD_33V | POC_SD0_CLK_33V);
| POC_SD0_DAT0_33V
| POC_SD0_CMD_33V
| POC_SD0_CLK_33V);
pfc_reg_write(PFC_IOCTRL30, reg);
reg = mmio_read_32(PFC_IOCTRL32);
reg = (reg & IOCTRL32_MASK);

51
drivers/staging/renesas/rcar/pfc/H3/pfc_init_h3_v1.c
View File

@ -802,7 +802,9 @@ void pfc_init_h3_v1(void)
| MOD_SEL0_DRIF2_A
| MOD_SEL0_DRIF1_A
| MOD_SEL0_DRIF0_A
| MOD_SEL0_CANFD0_A | MOD_SEL0_ADG_A | MOD_SEL0_5LINE_A);
| MOD_SEL0_CANFD0_A
| MOD_SEL0_ADG_A
| MOD_SEL0_5LINE_A);
pfc_reg_write(PFC_MOD_SEL1, MOD_SEL1_TSIF1_A
| MOD_SEL1_TSIF0_A
| MOD_SEL1_TIMER_TMU_A
@ -822,9 +824,13 @@ void pfc_init_h3_v1(void)
| MOD_SEL1_PWM6_A
| MOD_SEL1_PWM5_A
| MOD_SEL1_PWM4_A
| MOD_SEL1_PWM3_A | MOD_SEL1_PWM2_A | MOD_SEL1_PWM1_A);
| MOD_SEL1_PWM3_A
| MOD_SEL1_PWM2_A
| MOD_SEL1_PWM1_A);
pfc_reg_write(PFC_MOD_SEL2, MOD_SEL2_I2C_5_A
| MOD_SEL2_I2C_3_A | MOD_SEL2_I2C_0_A | MOD_SEL2_VIN4_A);
| MOD_SEL2_I2C_3_A
| MOD_SEL2_I2C_0_A
| MOD_SEL2_VIN4_A);
/* initialize peripheral function select */
pfc_reg_write(PFC_IPSR0, IPSR_28_FUNC(0)
@ -971,7 +977,10 @@ void pfc_init_h3_v1(void)
| GPSR0_D14
| GPSR0_D13
| GPSR0_D12
| GPSR0_D11 | GPSR0_D10 | GPSR0_D9 | GPSR0_D8);
| GPSR0_D11
| GPSR0_D10
| GPSR0_D9
| GPSR0_D8);
pfc_reg_write(PFC_GPSR1, GPSR1_EX_WAIT0_A
| GPSR1_A19
| GPSR1_A18
@ -984,7 +993,11 @@ void pfc_init_h3_v1(void)
| GPSR1_A7
| GPSR1_A6
| GPSR1_A5
| GPSR1_A4 | GPSR1_A3 | GPSR1_A2 | GPSR1_A1 | GPSR1_A0);
| GPSR1_A4
| GPSR1_A3
| GPSR1_A2
| GPSR1_A1
| GPSR1_A0);
pfc_reg_write(PFC_GPSR2, GPSR2_AVB_AVTP_CAPTURE_A
| GPSR2_AVB_AVTP_MATCH_A
| GPSR2_AVB_LINK
@ -994,7 +1007,10 @@ void pfc_init_h3_v1(void)
| GPSR2_PWM1_A
| GPSR2_IRQ5
| GPSR2_IRQ4
| GPSR2_IRQ3 | GPSR2_IRQ2 | GPSR2_IRQ1 | GPSR2_IRQ0);
| GPSR2_IRQ3
| GPSR2_IRQ2
| GPSR2_IRQ1
| GPSR2_IRQ0);
pfc_reg_write(PFC_GPSR3, GPSR3_SD0_WP
| GPSR3_SD0_CD
| GPSR3_SD1_DAT3
@ -1004,7 +1020,9 @@ void pfc_init_h3_v1(void)
| GPSR3_SD0_DAT3
| GPSR3_SD0_DAT2
| GPSR3_SD0_DAT1
| GPSR3_SD0_DAT0 | GPSR3_SD0_CMD | GPSR3_SD0_CLK);
| GPSR3_SD0_DAT0
| GPSR3_SD0_CMD
| GPSR3_SD0_CLK);
pfc_reg_write(PFC_GPSR4, GPSR4_SD3_DAT7
| GPSR4_SD3_DAT6
| GPSR4_SD3_DAT3
@ -1017,7 +1035,9 @@ void pfc_init_h3_v1(void)
| GPSR4_SD2_DAT3
| GPSR4_SD2_DAT2
| GPSR4_SD2_DAT1
| GPSR4_SD2_DAT0 | GPSR4_SD2_CMD | GPSR4_SD2_CLK);
| GPSR4_SD2_DAT0
| GPSR4_SD2_CMD
| GPSR4_SD2_CLK);
pfc_reg_write(PFC_GPSR5, GPSR5_MSIOF0_SS2
| GPSR5_MSIOF0_SS1
| GPSR5_MSIOF0_SYNC
@ -1032,7 +1052,9 @@ void pfc_init_h3_v1(void)
| GPSR5_RTS1_TANS
| GPSR5_CTS1
| GPSR5_TX1_A
| GPSR5_RX1_A | GPSR5_RTS0_TANS | GPSR5_SCK0);
| GPSR5_RX1_A
| GPSR5_RTS0_TANS
| GPSR5_SCK0);
pfc_reg_write(PFC_GPSR6, GPSR6_USB30_OVC
| GPSR6_USB30_PWEN
| GPSR6_USB1_OVC
@ -1052,9 +1074,12 @@ void pfc_init_h3_v1(void)
| GPSR6_SSI_SCK4
| GPSR6_SSI_SDATA1_A
| GPSR6_SSI_SDATA0
| GPSR6_SSI_WS0129 | GPSR6_SSI_SCK0129);
| GPSR6_SSI_WS0129
| GPSR6_SSI_SCK0129);
pfc_reg_write(PFC_GPSR7, GPSR7_HDMI1_CEC
| GPSR7_HDMI0_CEC | GPSR7_AVS2 | GPSR7_AVS1);
| GPSR7_HDMI0_CEC
| GPSR7_AVS2
| GPSR7_AVS1);
/* initialize POC control register */
pfc_reg_write(PFC_POCCTRL0, POC_SD3_DS_33V
@ -1071,7 +1096,9 @@ void pfc_init_h3_v1(void)
| POC_SD0_DAT3_33V
| POC_SD0_DAT2_33V
| POC_SD0_DAT1_33V
| POC_SD0_DAT0_33V | POC_SD0_CMD_33V | POC_SD0_CLK_33V);
| POC_SD0_DAT0_33V
| POC_SD0_CMD_33V
| POC_SD0_CLK_33V);
/* initialize DRV control register */
reg = mmio_read_32(PFC_DRVCTRL0);

50
drivers/staging/renesas/rcar/pfc/H3/pfc_init_h3_v2.c
View File

@ -833,7 +833,8 @@ void pfc_init_h3_v2(void)
| MOD_SEL0_DRIF2_A
| MOD_SEL0_DRIF1_A
| MOD_SEL0_DRIF0_A
| MOD_SEL0_CANFD0_A | MOD_SEL0_ADG_A_A);
| MOD_SEL0_CANFD0_A
| MOD_SEL0_ADG_A_A);
pfc_reg_write(PFC_MOD_SEL1, MOD_SEL1_TSIF1_A
| MOD_SEL1_TSIF0_A
| MOD_SEL1_TIMER_TMU_A
@ -853,7 +854,9 @@ void pfc_init_h3_v2(void)
| MOD_SEL1_PWM6_A
| MOD_SEL1_PWM5_A
| MOD_SEL1_PWM4_A
| MOD_SEL1_PWM3_A | MOD_SEL1_PWM2_A | MOD_SEL1_PWM1_A);
| MOD_SEL1_PWM3_A
| MOD_SEL1_PWM2_A
| MOD_SEL1_PWM1_A);
pfc_reg_write(PFC_MOD_SEL2, MOD_SEL2_I2C_5_A
| MOD_SEL2_I2C_3_A
| MOD_SEL2_I2C_0_A
@ -864,7 +867,9 @@ void pfc_init_h3_v2(void)
| MOD_SEL2_SSI2_A
| MOD_SEL2_SSI9_A
| MOD_SEL2_TIMER_TMU2_A
| MOD_SEL2_ADG_B_A | MOD_SEL2_ADG_C_A | MOD_SEL2_VIN4_A);
| MOD_SEL2_ADG_B_A
| MOD_SEL2_ADG_C_A
| MOD_SEL2_VIN4_A);
/* initialize peripheral function select */
pfc_reg_write(PFC_IPSR0, IPSR_28_FUNC(0)
@ -1019,7 +1024,10 @@ void pfc_init_h3_v2(void)
| GPSR0_D14
| GPSR0_D13
| GPSR0_D12
| GPSR0_D11 | GPSR0_D10 | GPSR0_D9 | GPSR0_D8);
| GPSR0_D11
| GPSR0_D10
| GPSR0_D9
| GPSR0_D8);
pfc_reg_write(PFC_GPSR1, GPSR1_CLKOUT
| GPSR1_EX_WAIT0_A
| GPSR1_A19
@ -1033,7 +1041,11 @@ void pfc_init_h3_v2(void)
| GPSR1_A7
| GPSR1_A6
| GPSR1_A5
| GPSR1_A4 | GPSR1_A3 | GPSR1_A2 | GPSR1_A1 | GPSR1_A0);
| GPSR1_A4
| GPSR1_A3
| GPSR1_A2
| GPSR1_A1
| GPSR1_A0);
pfc_reg_write(PFC_GPSR2, GPSR2_AVB_AVTP_CAPTURE_A
| GPSR2_AVB_AVTP_MATCH_A
| GPSR2_AVB_LINK
@ -1043,7 +1055,10 @@ void pfc_init_h3_v2(void)
| GPSR2_PWM1_A
| GPSR2_IRQ5
| GPSR2_IRQ4
| GPSR2_IRQ3 | GPSR2_IRQ2 | GPSR2_IRQ1 | GPSR2_IRQ0);
| GPSR2_IRQ3
| GPSR2_IRQ2
| GPSR2_IRQ1
| GPSR2_IRQ0);
pfc_reg_write(PFC_GPSR3, GPSR3_SD0_WP
| GPSR3_SD0_CD
| GPSR3_SD1_DAT3
@ -1053,7 +1068,9 @@ void pfc_init_h3_v2(void)
| GPSR3_SD0_DAT3
| GPSR3_SD0_DAT2
| GPSR3_SD0_DAT1
| GPSR3_SD0_DAT0 | GPSR3_SD0_CMD | GPSR3_SD0_CLK);
| GPSR3_SD0_DAT0
| GPSR3_SD0_CMD
| GPSR3_SD0_CLK);
pfc_reg_write(PFC_GPSR4, GPSR4_SD3_DAT7
| GPSR4_SD3_DAT6
| GPSR4_SD3_DAT3
@ -1066,7 +1083,9 @@ void pfc_init_h3_v2(void)
| GPSR4_SD2_DAT3
| GPSR4_SD2_DAT2
| GPSR4_SD2_DAT1
| GPSR4_SD2_DAT0 | GPSR4_SD2_CMD | GPSR4_SD2_CLK);
| GPSR4_SD2_DAT0
| GPSR4_SD2_CMD
| GPSR4_SD2_CLK);
pfc_reg_write(PFC_GPSR5, GPSR5_MSIOF0_SS2
| GPSR5_MSIOF0_SS1
| GPSR5_MSIOF0_SYNC
@ -1081,7 +1100,9 @@ void pfc_init_h3_v2(void)
| GPSR5_RTS1_TANS
| GPSR5_CTS1
| GPSR5_TX1_A
| GPSR5_RX1_A | GPSR5_RTS0_TANS | GPSR5_SCK0);
| GPSR5_RX1_A
| GPSR5_RTS0_TANS
| GPSR5_SCK0);
pfc_reg_write(PFC_GPSR6, GPSR6_USB30_OVC
| GPSR6_USB30_PWEN
| GPSR6_USB1_OVC
@ -1101,9 +1122,12 @@ void pfc_init_h3_v2(void)
| GPSR6_SSI_SCK4
| GPSR6_SSI_SDATA1_A
| GPSR6_SSI_SDATA0
| GPSR6_SSI_WS0129 | GPSR6_SSI_SCK0129);
| GPSR6_SSI_WS0129
| GPSR6_SSI_SCK0129);
pfc_reg_write(PFC_GPSR7, GPSR7_HDMI1_CEC
| GPSR7_HDMI0_CEC | GPSR7_AVS2 | GPSR7_AVS1);
| GPSR7_HDMI0_CEC
| GPSR7_AVS2
| GPSR7_AVS1);
/* initialize POC control register */
pfc_reg_write(PFC_POCCTRL0, POC_SD3_DS_33V
@ -1120,7 +1144,9 @@ void pfc_init_h3_v2(void)
| POC_SD0_DAT3_33V
| POC_SD0_DAT2_33V
| POC_SD0_DAT1_33V
| POC_SD0_DAT0_33V | POC_SD0_CMD_33V | POC_SD0_CLK_33V);
| POC_SD0_DAT0_33V
| POC_SD0_CMD_33V
| POC_SD0_CLK_33V);
/* initialize DRV control register */
reg = mmio_read_32(PFC_DRVCTRL0);

54
drivers/staging/renesas/rcar/pfc/M3/pfc_init_m3.c
View File

@ -867,7 +867,9 @@ static void StartRtDma0_Descriptor(void)
/* Set transfer parameter, Start transfer */
mmio_write_32(RTDMAC_RDMCHCR(RTDMAC_CH), RDMCHCR_DPM_INFINITE
| RDMCHCR_RPT_TCR
| RDMCHCR_TS_2 | RDMCHCR_RS_AUTO | RDMCHCR_DE);
| RDMCHCR_TS_2
| RDMCHCR_RS_AUTO
| RDMCHCR_DE);
}
}
@ -913,7 +915,8 @@ void pfc_init_m3(void)
| MOD_SEL0_DRIF2_A
| MOD_SEL0_DRIF1_A
| MOD_SEL0_DRIF0_A
| MOD_SEL0_CANFD0_A | MOD_SEL0_ADG_A_A);
| MOD_SEL0_CANFD0_A
| MOD_SEL0_ADG_A_A);
pfc_reg_write(PFC_MOD_SEL1, MOD_SEL1_TSIF1_A
| MOD_SEL1_TSIF0_A
| MOD_SEL1_TIMER_TMU_A
@ -933,7 +936,9 @@ void pfc_init_m3(void)
| MOD_SEL1_PWM6_A
| MOD_SEL1_PWM5_A
| MOD_SEL1_PWM4_A
| MOD_SEL1_PWM3_A | MOD_SEL1_PWM2_A | MOD_SEL1_PWM1_A);
| MOD_SEL1_PWM3_A
| MOD_SEL1_PWM2_A
| MOD_SEL1_PWM1_A);
pfc_reg_write(PFC_MOD_SEL2, MOD_SEL2_I2C_5_A
| MOD_SEL2_I2C_3_A
| MOD_SEL2_I2C_0_A
@ -944,7 +949,9 @@ void pfc_init_m3(void)
| MOD_SEL2_SSI2_A
| MOD_SEL2_SSI9_A
| MOD_SEL2_TIMER_TMU2_A
| MOD_SEL2_ADG_B_A | MOD_SEL2_ADG_C_A | MOD_SEL2_VIN4_A);
| MOD_SEL2_ADG_B_A
| MOD_SEL2_ADG_C_A
| MOD_SEL2_VIN4_A);
/* initialize peripheral function select */
pfc_reg_write(PFC_IPSR0, IPSR_28_FUNC(0)
@ -1099,7 +1106,10 @@ void pfc_init_m3(void)
| GPSR0_D14
| GPSR0_D13
| GPSR0_D12
| GPSR0_D11 | GPSR0_D10 | GPSR0_D9 | GPSR0_D8);
| GPSR0_D11
| GPSR0_D10
| GPSR0_D9
| GPSR0_D8);
pfc_reg_write(PFC_GPSR1, GPSR1_CLKOUT
| GPSR1_EX_WAIT0_A
| GPSR1_A19
@ -1113,7 +1123,11 @@ void pfc_init_m3(void)
| GPSR1_A7
| GPSR1_A6
| GPSR1_A5
| GPSR1_A4 | GPSR1_A3 | GPSR1_A2 | GPSR1_A1 | GPSR1_A0);
| GPSR1_A4
| GPSR1_A3
| GPSR1_A2
| GPSR1_A1
| GPSR1_A0);
pfc_reg_write(PFC_GPSR2, GPSR2_AVB_AVTP_CAPTURE_A
| GPSR2_AVB_AVTP_MATCH_A
| GPSR2_AVB_LINK
@ -1123,7 +1137,10 @@ void pfc_init_m3(void)
| GPSR2_PWM1_A
| GPSR2_IRQ5
| GPSR2_IRQ4
| GPSR2_IRQ3 | GPSR2_IRQ2 | GPSR2_IRQ1 | GPSR2_IRQ0);
| GPSR2_IRQ3
| GPSR2_IRQ2
| GPSR2_IRQ1
| GPSR2_IRQ0);
pfc_reg_write(PFC_GPSR3, GPSR3_SD0_WP
| GPSR3_SD0_CD
| GPSR3_SD1_DAT3
@ -1133,7 +1150,9 @@ void pfc_init_m3(void)
| GPSR3_SD0_DAT3
| GPSR3_SD0_DAT2
| GPSR3_SD0_DAT1
| GPSR3_SD0_DAT0 | GPSR3_SD0_CMD | GPSR3_SD0_CLK);
| GPSR3_SD0_DAT0
| GPSR3_SD0_CMD
| GPSR3_SD0_CLK);
pfc_reg_write(PFC_GPSR4, GPSR4_SD3_DAT7
| GPSR4_SD3_DAT6
| GPSR4_SD3_DAT3
@ -1146,7 +1165,9 @@ void pfc_init_m3(void)
| GPSR4_SD2_DAT3
| GPSR4_SD2_DAT2
| GPSR4_SD2_DAT1
| GPSR4_SD2_DAT0 | GPSR4_SD2_CMD | GPSR4_SD2_CLK);
| GPSR4_SD2_DAT0
| GPSR4_SD2_CMD
| GPSR4_SD2_CLK);
pfc_reg_write(PFC_GPSR5, GPSR5_MSIOF0_SS2
| GPSR5_MSIOF0_SS1
| GPSR5_MSIOF0_SYNC
@ -1161,7 +1182,9 @@ void pfc_init_m3(void)
| GPSR5_RTS1_TANS
| GPSR5_CTS1
| GPSR5_TX1_A
| GPSR5_RX1_A | GPSR5_RTS0_TANS | GPSR5_SCK0);
| GPSR5_RX1_A
| GPSR5_RTS0_TANS
| GPSR5_SCK0);
pfc_reg_write(PFC_GPSR6, GPSR6_USB30_OVC
| GPSR6_USB30_PWEN
| GPSR6_USB1_OVC
@ -1181,9 +1204,12 @@ void pfc_init_m3(void)
| GPSR6_SSI_SCK4
| GPSR6_SSI_SDATA1_A
| GPSR6_SSI_SDATA0
| GPSR6_SSI_WS0129 | GPSR6_SSI_SCK0129);
| GPSR6_SSI_WS0129
| GPSR6_SSI_SCK0129);
pfc_reg_write(PFC_GPSR7, GPSR7_HDMI1_CEC
| GPSR7_HDMI0_CEC | GPSR7_AVS2 | GPSR7_AVS1);
| GPSR7_HDMI0_CEC
| GPSR7_AVS2
| GPSR7_AVS1);
/* initialize POC control register */
pfc_reg_write(PFC_POCCTRL0, POC_SD3_DS_33V
@ -1200,7 +1226,9 @@ void pfc_init_m3(void)
| POC_SD0_DAT3_33V
| POC_SD0_DAT2_33V
| POC_SD0_DAT1_33V
| POC_SD0_DAT0_33V | POC_SD0_CMD_33V | POC_SD0_CLK_33V);
| POC_SD0_DAT0_33V
| POC_SD0_CMD_33V
| POC_SD0_CLK_33V);
/* initialize DRV control register */
reg = mmio_read_32(PFC_DRVCTRL0);

50
drivers/staging/renesas/rcar/pfc/M3N/pfc_init_m3n.c
View File

@ -821,7 +821,8 @@ void pfc_init_m3n(void)
| MOD_SEL0_DRIF2_A
| MOD_SEL0_DRIF1_A
| MOD_SEL0_DRIF0_A
| MOD_SEL0_CANFD0_A | MOD_SEL0_ADG_A_A);
| MOD_SEL0_CANFD0_A
| MOD_SEL0_ADG_A_A);
pfc_reg_write(PFC_MOD_SEL1, MOD_SEL1_TSIF1_A
| MOD_SEL1_TSIF0_A
| MOD_SEL1_TIMER_TMU_A
@ -841,7 +842,9 @@ void pfc_init_m3n(void)
| MOD_SEL1_PWM6_A
| MOD_SEL1_PWM5_A
| MOD_SEL1_PWM4_A
| MOD_SEL1_PWM3_A | MOD_SEL1_PWM2_A | MOD_SEL1_PWM1_A);
| MOD_SEL1_PWM3_A
| MOD_SEL1_PWM2_A
| MOD_SEL1_PWM1_A);
pfc_reg_write(PFC_MOD_SEL2, MOD_SEL2_I2C_5_A
| MOD_SEL2_I2C_3_A
| MOD_SEL2_I2C_0_A
@ -852,7 +855,9 @@ void pfc_init_m3n(void)
| MOD_SEL2_SSI2_A
| MOD_SEL2_SSI9_A
| MOD_SEL2_TIMER_TMU2_A
| MOD_SEL2_ADG_B_A | MOD_SEL2_ADG_C_A | MOD_SEL2_VIN4_A);
| MOD_SEL2_ADG_B_A
| MOD_SEL2_ADG_C_A
| MOD_SEL2_VIN4_A);
/* initialize peripheral function select */
pfc_reg_write(PFC_IPSR0, IPSR_28_FUNC(0)
@ -1007,7 +1012,10 @@ void pfc_init_m3n(void)
| GPSR0_D14
| GPSR0_D13
| GPSR0_D12
| GPSR0_D11 | GPSR0_D10 | GPSR0_D9 | GPSR0_D8);
| GPSR0_D11
| GPSR0_D10
| GPSR0_D9
| GPSR0_D8);
pfc_reg_write(PFC_GPSR1, GPSR1_CLKOUT
| GPSR1_EX_WAIT0_A
| GPSR1_A19
@ -1021,7 +1029,11 @@ void pfc_init_m3n(void)
| GPSR1_A7
| GPSR1_A6
| GPSR1_A5
| GPSR1_A4 | GPSR1_A3 | GPSR1_A2 | GPSR1_A1 | GPSR1_A0);
| GPSR1_A4
| GPSR1_A3
| GPSR1_A2
| GPSR1_A1
| GPSR1_A0);
pfc_reg_write(PFC_GPSR2, GPSR2_AVB_AVTP_CAPTURE_A
| GPSR2_AVB_AVTP_MATCH_A
| GPSR2_AVB_LINK
@ -1031,7 +1043,10 @@ void pfc_init_m3n(void)
| GPSR2_PWM1_A
| GPSR2_IRQ5
| GPSR2_IRQ4
| GPSR2_IRQ3 | GPSR2_IRQ2 | GPSR2_IRQ1 | GPSR2_IRQ0);
| GPSR2_IRQ3
| GPSR2_IRQ2
| GPSR2_IRQ1
| GPSR2_IRQ0);
pfc_reg_write(PFC_GPSR3, GPSR3_SD0_WP
| GPSR3_SD0_CD
| GPSR3_SD1_DAT3
@ -1041,7 +1056,9 @@ void pfc_init_m3n(void)
| GPSR3_SD0_DAT3
| GPSR3_SD0_DAT2
| GPSR3_SD0_DAT1
| GPSR3_SD0_DAT0 | GPSR3_SD0_CMD | GPSR3_SD0_CLK);
| GPSR3_SD0_DAT0
| GPSR3_SD0_CMD
| GPSR3_SD0_CLK);
pfc_reg_write(PFC_GPSR4, GPSR4_SD3_DAT7
| GPSR4_SD3_DAT6
| GPSR4_SD3_DAT3
@ -1054,7 +1071,9 @@ void pfc_init_m3n(void)
| GPSR4_SD2_DAT3
| GPSR4_SD2_DAT2
| GPSR4_SD2_DAT1
| GPSR4_SD2_DAT0 | GPSR4_SD2_CMD | GPSR4_SD2_CLK);
| GPSR4_SD2_DAT0
| GPSR4_SD2_CMD
| GPSR4_SD2_CLK);
pfc_reg_write(PFC_GPSR5, GPSR5_MSIOF0_SS2
| GPSR5_MSIOF0_SS1
| GPSR5_MSIOF0_SYNC
@ -1069,7 +1088,9 @@ void pfc_init_m3n(void)
| GPSR5_RTS1_TANS
| GPSR5_CTS1
| GPSR5_TX1_A
| GPSR5_RX1_A | GPSR5_RTS0_TANS | GPSR5_SCK0);
| GPSR5_RX1_A
| GPSR5_RTS0_TANS
| GPSR5_SCK0);
pfc_reg_write(PFC_GPSR6, GPSR6_USB30_OVC
| GPSR6_USB30_PWEN
| GPSR6_USB1_OVC
@ -1089,9 +1110,12 @@ void pfc_init_m3n(void)
| GPSR6_SSI_SCK4
| GPSR6_SSI_SDATA1_A
| GPSR6_SSI_SDATA0
| GPSR6_SSI_WS0129 | GPSR6_SSI_SCK0129);
| GPSR6_SSI_WS0129
| GPSR6_SSI_SCK0129);
pfc_reg_write(PFC_GPSR7, GPSR7_HDMI1_CEC
| GPSR7_HDMI0_CEC | GPSR7_AVS2 | GPSR7_AVS1);
| GPSR7_HDMI0_CEC
| GPSR7_AVS2
| GPSR7_AVS1);
/* initialize POC control register */
pfc_reg_write(PFC_POCCTRL0, POC_SD3_DS_33V
@ -1108,7 +1132,9 @@ void pfc_init_m3n(void)
| POC_SD0_DAT3_33V
| POC_SD0_DAT2_33V
| POC_SD0_DAT1_33V
| POC_SD0_DAT0_33V | POC_SD0_CMD_33V | POC_SD0_CLK_33V);
| POC_SD0_DAT0_33V
| POC_SD0_CMD_33V
| POC_SD0_CLK_33V);
/* initialize DRV control register */
reg = mmio_read_32(PFC_DRVCTRL0);

10
drivers/staging/renesas/rcar/qos/E3/qos_init_e3_v10.c
View File

@ -12,7 +12,7 @@
#include "../qos_reg.h"
#include "qos_init_e3_v10.h"
#define RCAR_QOS_VERSION "rev.0.02"
#define RCAR_QOS_VERSION "rev.0.05"
#define QOSCTRL_EARLYR (QOS_BASE1 + 0x0060U)
#define QOSCTRL_FSS (QOS_BASE1 + 0x0048U)
@ -134,14 +134,6 @@ void qos_init_e3_v10(void)
}
}
/* 3DG bus Leaf setting */
io_write_32(GPU_ACT_GRD, 0x00001234U);
io_write_32(GPU_ACT0, 0x00000000U);
io_write_32(GPU_ACT1, 0x00000000U);
io_write_32(GPU_ACT2, 0x00000000U);
io_write_32(GPU_ACT3, 0x00000000U);
io_write_32(GPU_ACT_GRD, 0x00000000U);
/* RT bus Leaf setting */
io_write_32(RT_ACT0, 0x00000000U);
io_write_32(RT_ACT1, 0x00000000U);

8
drivers/staging/renesas/rcar/qos/E3/qos_init_e3_v10_mstat390.h
View File

@ -27,20 +27,20 @@ static uint64_t mstat_fix[] = {
/* 0x0098, */ 0x0000000000000000UL,
/* 0x00a0, */ 0x000C08380000FFFFUL,
/* 0x00a8, */ 0x000C04110000FFFFUL,
/* 0x00b0, */ 0x000C04110000FFFFUL,
/* 0x00b0, */ 0x000C04150000FFFFUL,
/* 0x00b8, */ 0x0000000000000000UL,
/* 0x00c0, */ 0x000C08380000FFFFUL,
/* 0x00c8, */ 0x000C04110000FFFFUL,
/* 0x00d0, */ 0x000C04110000FFFFUL,
/* 0x00d0, */ 0x000C04150000FFFFUL,
/* 0x00d8, */ 0x0000000000000000UL,
/* 0x00e0, */ 0x0000000000000000UL,
/* 0x00e8, */ 0x0000000000000000UL,
/* 0x00f0, */ 0x001018580000FFFFUL,
/* 0x00f8, */ 0x000C04400000FFFFUL,
/* 0x00f8, */ 0x000C084F0000FFFFUL,
/* 0x0100, */ 0x0000000000000000UL,
/* 0x0108, */ 0x0000000000000000UL,
/* 0x0110, */ 0x001008580000FFFFUL,
/* 0x0118, */ 0x000C19660000FFFFUL,
/* 0x0118, */ 0x000C21E40000FFFFUL,
/* 0x0120, */ 0x0000000000000000UL,
/* 0x0128, */ 0x0000000000000000UL,
/* 0x0130, */ 0x0000000000000000UL,

8
drivers/staging/renesas/rcar/qos/E3/qos_init_e3_v10_mstat780.h
View File

@ -27,20 +27,20 @@ static uint64_t mstat_fix[] = {
/* 0x0098, */ 0x0000000000000000UL,
/* 0x00a0, */ 0x000C10700000FFFFUL,
/* 0x00a8, */ 0x000C08210000FFFFUL,
/* 0x00b0, */ 0x000C08210000FFFFUL,
/* 0x00b0, */ 0x000C082A0000FFFFUL,
/* 0x00b8, */ 0x0000000000000000UL,
/* 0x00c0, */ 0x000C10700000FFFFUL,
/* 0x00c8, */ 0x000C08210000FFFFUL,
/* 0x00d0, */ 0x000C08210000FFFFUL,
/* 0x00d0, */ 0x000C082A0000FFFFUL,
/* 0x00d8, */ 0x0000000000000000UL,
/* 0x00e0, */ 0x0000000000000000UL,
/* 0x00e8, */ 0x0000000000000000UL,
/* 0x00f0, */ 0x00102CAF0000FFFFUL,
/* 0x00f8, */ 0x000C087F0000FFFFUL,
/* 0x00f8, */ 0x000C0C9D0000FFFFUL,
/* 0x0100, */ 0x0000000000000000UL,
/* 0x0108, */ 0x0000000000000000UL,
/* 0x0110, */ 0x00100CAF0000FFFFUL,
/* 0x0118, */ 0x000C32CC0000FFFFUL,
/* 0x0118, */ 0x000C43C80000FFFFUL,
/* 0x0120, */ 0x0000000000000000UL,
/* 0x0128, */ 0x0000000000000000UL,
/* 0x0130, */ 0x0000000000000000UL,

3
drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v20.c
View File

@ -12,7 +12,8 @@
#include "../qos_reg.h"
#include "qos_init_h3_v20.h"
#define RCAR_QOS_VERSION "rev.0.19"
#define RCAR_QOS_VERSION "rev.0.20"
#define QOSWT_TIME_BANK0 (20000000U) /* unit:ns */

5
drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v30.c
View File

@ -12,7 +12,8 @@
#include "../qos_reg.h"
#include "qos_init_h3_v30.h"
#define RCAR_QOS_VERSION "rev.0.07"
#define RCAR_QOS_VERSION "rev.0.10"
#define QOSCTRL_FSS (QOS_BASE1 + 0x0048U)
@ -226,8 +227,6 @@ void qos_init_h3_v30(void)
io_write_32(AXI_TR3CR, 0x00010000U);
io_write_32(AXI_TR4CR, 0x00010000U);
/* 3DG bus Leaf setting */
/* RT bus Leaf setting */
io_write_32(RT_ACT0, 0x00000000U);
io_write_32(RT_ACT1, 0x00000000U);

6
drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v30_mstat195.h
View File

@ -36,12 +36,12 @@ static uint64_t mstat_fix[] = {
/* 0x00e0, */ 0x00100C090000FFFFUL,
/* 0x00e8, */ 0x0000000000000000UL,
/* 0x00f0, */ 0x001024090000FFFFUL,
/* 0x00f8, */ 0x000C08080000FFFFUL,
/* 0x00f8, */ 0x000C100D0000FFFFUL,
/* 0x0100, */ 0x0000000000000000UL,
/* 0x0108, */ 0x0000000000000000UL,
/* 0x0110, */ 0x00100C090000FFFFUL,
/* 0x0118, */ 0x000C18180000FFFFUL,
/* 0x0120, */ 0x000C18180000FFFFUL,
/* 0x0118, */ 0x000C1C1B0000FFFFUL,
/* 0x0120, */ 0x000C1C1B0000FFFFUL,
/* 0x0128, */ 0x0000000000000000UL,
/* 0x0130, */ 0x0000000000000000UL,
/* 0x0138, */ 0x00100C0B0000FFFFUL,

6
drivers/staging/renesas/rcar/qos/H3/qos_init_h3_v30_mstat390.h
View File

@ -36,12 +36,12 @@ static uint64_t mstat_fix[] = {
/* 0x00e0, */ 0x001014110000FFFFUL,
/* 0x00e8, */ 0x0000000000000000UL,
/* 0x00f0, */ 0x001044110000FFFFUL,
/* 0x00f8, */ 0x000C10100000FFFFUL,
/* 0x00f8, */ 0x000C1C1A0000FFFFUL,
/* 0x0100, */ 0x0000000000000000UL,
/* 0x0108, */ 0x0000000000000000UL,
/* 0x0110, */ 0x001014110000FFFFUL,
/* 0x0118, */ 0x000C302F0000FFFFUL,
/* 0x0120, */ 0x000C302F0000FFFFUL,
/* 0x0118, */ 0x000C38360000FFFFUL,
/* 0x0120, */ 0x000C38360000FFFFUL,
/* 0x0128, */ 0x0000000000000000UL,
/* 0x0130, */ 0x0000000000000000UL,
/* 0x0138, */ 0x001018150000FFFFUL,

11
drivers/staging/renesas/rcar/qos/H3/qos_init_h3n_v30.c
View File

@ -12,7 +12,8 @@
#include "../qos_reg.h"
#include "qos_init_h3n_v30.h"
#define RCAR_QOS_VERSION "rev.0.03"
#define RCAR_QOS_VERSION "rev.0.06"
#define QOSCTRL_FSS (QOS_BASE1 + 0x0048U)
@ -220,14 +221,6 @@ void qos_init_h3n_v30(void)
io_write_32(AXI_TR3CR, 0x00010000U);
io_write_32(AXI_TR4CR, 0x00010000U);
/* 3DG bus Leaf setting */
io_write_32(GPU_ACT_GRD, 0x00001234U);
io_write_32(GPU_ACT0, 0x00000000U);
io_write_32(GPU_ACT1, 0x00000000U);
io_write_32(GPU_ACT2, 0x00000000U);
io_write_32(GPU_ACT3, 0x00000000U);
io_write_32(GPU_ACT_GRD, 0x00000000U);
/* RT bus Leaf setting */
io_write_32(RT_ACT0, 0x00000000U);
io_write_32(RT_ACT1, 0x00000000U);

6
drivers/staging/renesas/rcar/qos/H3/qos_init_h3n_v30_mstat195.h
View File

@ -36,12 +36,12 @@ static uint64_t mstat_fix[] = {
/* 0x00e0, */ 0x00100C090000FFFFUL,
/* 0x00e8, */ 0x0000000000000000UL,
/* 0x00f0, */ 0x001024090000FFFFUL,
/* 0x00f8, */ 0x000C08080000FFFFUL,
/* 0x00f8, */ 0x000C100D0000FFFFUL,
/* 0x0100, */ 0x0000000000000000UL,
/* 0x0108, */ 0x0000000000000000UL,
/* 0x0110, */ 0x00100C090000FFFFUL,
/* 0x0118, */ 0x000C18180000FFFFUL,
/* 0x0120, */ 0x000C18180000FFFFUL,
/* 0x0118, */ 0x000C1C1B0000FFFFUL,
/* 0x0120, */ 0x000C1C1B0000FFFFUL,
/* 0x0128, */ 0x0000000000000000UL,
/* 0x0130, */ 0x0000000000000000UL,
/* 0x0138, */ 0x00100C0B0000FFFFUL,

6
drivers/staging/renesas/rcar/qos/H3/qos_init_h3n_v30_mstat390.h
View File

@ -36,12 +36,12 @@ static uint64_t mstat_fix[] = {
/* 0x00e0, */ 0x001014110000FFFFUL,
/* 0x00e8, */ 0x0000000000000000UL,
/* 0x00f0, */ 0x001044110000FFFFUL,
/* 0x00f8, */ 0x000C10100000FFFFUL,
/* 0x00f8, */ 0x000C1C1A0000FFFFUL,
/* 0x0100, */ 0x0000000000000000UL,
/* 0x0108, */ 0x0000000000000000UL,
/* 0x0110, */ 0x001014110000FFFFUL,
/* 0x0118, */ 0x000C302F0000FFFFUL,
/* 0x0120, */ 0x000C302F0000FFFFUL,
/* 0x0118, */ 0x000C38360000FFFFUL,
/* 0x0120, */ 0x000C38360000FFFFUL,
/* 0x0128, */ 0x0000000000000000UL,
/* 0x0130, */ 0x0000000000000000UL,
/* 0x0138, */ 0x001018150000FFFFUL,

3
drivers/staging/renesas/rcar/qos/M3/qos_init_m3_v11.c
View File

@ -12,7 +12,8 @@
#include "../qos_reg.h"
#include "qos_init_m3_v11.h"
#define RCAR_QOS_VERSION "rev.0.17"
#define RCAR_QOS_VERSION "rev.0.18"
#define QOSWT_TIME_BANK0 (20000000U) /* unit:ns */

10
drivers/staging/renesas/rcar/qos/M3N/qos_init_m3n_v10.c
View File

@ -12,7 +12,7 @@
#include "../qos_reg.h"
#include "qos_init_m3n_v10.h"
#define RCAR_QOS_VERSION "rev.0.06"
#define RCAR_QOS_VERSION "rev.0.08"
#define QOSCTRL_EARLYR (QOS_BASE1 + 0x0060U)
#define QOSCTRL_FSS (QOS_BASE1 + 0x0048U)
@ -198,14 +198,6 @@ void qos_init_m3n_v10(void)
#endif /* RCAR_REWT_TRAINING != RCAR_REWT_TRAINING_DISABLE */
}
/* 3DG bus Leaf setting */
io_write_32(GPU_ACT_GRD, 0x00001234U);
io_write_32(GPU_ACT0, 0x00000000U);
io_write_32(GPU_ACT1, 0x00000000U);
io_write_32(GPU_ACT2, 0x00000000U);
io_write_32(GPU_ACT3, 0x00000000U);
io_write_32(GPU_ACT_GRD, 0x00000000U);
/* RT bus Leaf setting */
io_write_32(RT_ACT0, 0x00000000U);
io_write_32(RT_ACT1, 0x00000000U);

4
drivers/staging/renesas/rcar/qos/M3N/qos_init_m3n_v10_mstat195.h
View File

@ -27,11 +27,11 @@ static uint64_t mstat_fix[] = {
/* 0x0098, */ 0x0000000000000000UL,
/* 0x00a0, */ 0x000C041D0000FFFFUL,
/* 0x00a8, */ 0x000C04090000FFFFUL,
/* 0x00b0, */ 0x000C04090000FFFFUL,
/* 0x00b0, */ 0x000C040B0000FFFFUL,
/* 0x00b8, */ 0x0000000000000000UL,
/* 0x00c0, */ 0x000C041D0000FFFFUL,
/* 0x00c8, */ 0x000C04090000FFFFUL,
/* 0x00d0, */ 0x000C04090000FFFFUL,
/* 0x00d0, */ 0x000C040B0000FFFFUL,
/* 0x00d8, */ 0x0000000000000000UL,
/* 0x00e0, */ 0x0000000000000000UL,
/* 0x00e8, */ 0x0000000000000000UL,

4
drivers/staging/renesas/rcar/qos/M3N/qos_init_m3n_v10_mstat390.h
View File

@ -27,11 +27,11 @@ static uint64_t mstat_fix[] = {
/* 0x0098, */ 0x0000000000000000UL,
/* 0x00a0, */ 0x000C08390000FFFFUL,
/* 0x00a8, */ 0x000C04110000FFFFUL,
/* 0x00b0, */ 0x000C04110000FFFFUL,
/* 0x00b0, */ 0x000C04150000FFFFUL,
/* 0x00b8, */ 0x0000000000000000UL,
/* 0x00c0, */ 0x000C08390000FFFFUL,
/* 0x00c8, */ 0x000C04110000FFFFUL,
/* 0x00d0, */ 0x000C04110000FFFFUL,
/* 0x00d0, */ 0x000C04150000FFFFUL,
/* 0x00d8, */ 0x0000000000000000UL,
/* 0x00e0, */ 0x0000000000000000UL,
/* 0x00e8, */ 0x0000000000000000UL,

11
drivers/staging/renesas/rcar/qos/qos_common.h
View File

@ -9,6 +9,15 @@
#define RCAR_REF_DEFAULT (0U)
/* define used for get_refperiod. */
/* REFPERIOD_CYCLE need smaller than QOSWT_WTSET0_CYCLEs */
/* refere to plat/renesas/rcar/ddr/ddr_a/ddr_init_e3.h for E3. */
#if (RCAR_REF_INT == RCAR_REF_DEFAULT) /* REF default */
#define REFPERIOD_CYCLE ((126 * BASE_SUB_SLOT_NUM * 1000U)/400) /* unit:ns */
#else /* REF option */
#define REFPERIOD_CYCLE ((252 * BASE_SUB_SLOT_NUM * 1000U)/400) /* unit:ns */
#endif
#if (RCAR_LSI == RCAR_E3)
/* define used for E3 */
#if (RCAR_REF_INT == RCAR_REF_DEFAULT) /* REF 3.9usec */
@ -19,7 +28,7 @@
#define OPERATING_FREQ_E3 (266U) /* MHz */
#define SL_INIT_SSLOTCLK_E3 (SUB_SLOT_CYCLE_E3 -1U)
#define QOSWT_WTSET0_CYCLE_E3 ((SUB_SLOT_CYCLE_E3 * BASE_SUB_SLOT_NUM * 1000U)/OPERATING_FREQ_E3) /* unit:ns */
/* #define QOSWT_WTSET0_CYCLE_E3 ((SUB_SLOT_CYCLE_E3 * BASE_SUB_SLOT_NUM * 1000U)/OPERATING_FREQ_E3) */ /* unit:ns */
#endif
#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_M3N)

33
drivers/staging/renesas/rcar/qos/qos_init.c
View File

@ -238,6 +238,7 @@ void rcar_qos_init(void)
#endif
}
#if !(RCAR_LSI == RCAR_E3)
uint32_t get_refperiod(void)
{
uint32_t refperiod = QOSWT_WTSET0_CYCLE;
@ -254,11 +255,9 @@ uint32_t get_refperiod(void)
case PRR_PRODUCT_11:
break;
case PRR_PRODUCT_20:
refperiod = QOSWT_WTSET0_CYCLE_H3_20;
break;
case PRR_PRODUCT_30:
default:
refperiod = QOSWT_WTSET0_CYCLE_H3_30;
refperiod = REFPERIOD_CYCLE;
break;
}
break;
@ -267,7 +266,7 @@ uint32_t get_refperiod(void)
switch (reg & PRR_CUT_MASK) {
case PRR_PRODUCT_30:
default:
refperiod = QOSWT_WTSET0_CYCLE_H3N;
refperiod = REFPERIOD_CYCLE;
break;
}
break;
@ -277,21 +276,16 @@ uint32_t get_refperiod(void)
switch (reg & PRR_CUT_MASK) {
case PRR_PRODUCT_10:
break;
case PRR_PRODUCT_20: /* M3 Cut 11 */
case PRR_PRODUCT_20: /* M3 Cut 11 */
default:
refperiod = QOSWT_WTSET0_CYCLE_M3_11;
refperiod = REFPERIOD_CYCLE;
break;
}
break;
#endif
#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_M3N)
case PRR_PRODUCT_M3N:
refperiod = QOSWT_WTSET0_CYCLE_M3N;
break;
#endif
#if (RCAR_LSI == RCAR_E3)
case PRR_PRODUCT_E3:
refperiod = QOSWT_WTSET0_CYCLE_E3;
refperiod = REFPERIOD_CYCLE;
break;
#endif
default:
@ -302,28 +296,25 @@ uint32_t get_refperiod(void)
/* H3 Cut 10 */
#elif RCAR_LSI_CUT == RCAR_CUT_11
/* H3 Cut 11 */
#elif RCAR_LSI_CUT == RCAR_CUT_20
/* H3 Cut 20 */
refperiod = QOSWT_WTSET0_CYCLE_H3_20;
#else
/* H3 Cut 20 */
/* H3 Cut 30 or later */
refperiod = QOSWT_WTSET0_CYCLE_H3_30;
refperiod = REFPERIOD_CYCLE;
#endif
#elif RCAR_LSI == RCAR_H3N
/* H3N Cut 30 or later */
refperiod = QOSWT_WTSET0_CYCLE_H3N;
refperiod = REFPERIOD_CYCLE;
#elif RCAR_LSI == RCAR_M3
#if RCAR_LSI_CUT == RCAR_CUT_10
/* M3 Cut 10 */
#else
/* M3 Cut 11 or later */
refperiod = QOSWT_WTSET0_CYCLE_M3_11;
refperiod = REFPERIOD_CYCLE;
#endif
#elif RCAR_LSI == RCAR_M3N /* for M3N */
refperiod = QOSWT_WTSET0_CYCLE_M3N;
#elif RCAR_LSI == RCAR_E3 /* for E3 */
refperiod = QOSWT_WTSET0_CYCLE_E3;
refperiod = REFPERIOD_CYCLE;
#endif
return refperiod;
}
#endif

6
plat/renesas/rcar/aarch64/plat_helpers.S
View File

@ -217,6 +217,8 @@ endfunc platform_mem_init
* ---------------------------------------------
*/
func plat_report_exception
/* Switch to SP_EL0 */
msr spsel, #0
#if IMAGE_BL2
mov w1, #FIQ_SP_EL0
cmp w0, w1
@ -326,11 +328,11 @@ func plat_reset_handler
ubfx w0, w0, 8, 8
/* H3? */
cmp w0, #0x4F
b.eq H3
b.eq RCARH3
/* set R-Car M3/M3N */
mov x2, #1
b CHK_A5x
H3:
RCARH3:
/* set R-Car H3 */
mov x2, #0
/* --------------------------------------------------------------------

6
plat/renesas/rcar/aarch64/platform_common.c
View File

@ -102,7 +102,7 @@ const uint8_t version_of_renesas[VERSION_OF_RENESAS_MAXLEN]
#endif
#if IMAGE_BL2
const mmap_region_t rcar_mmap[] = {
static const mmap_region_t rcar_mmap[] = {
MAP_FLASH0, /* 0x08000000 - 0x0BFFFFFF RPC area */
MAP_DRAM0, /* 0x40000000 - 0xBFFFFFFF DRAM area(Legacy) */
MAP_REG0, /* 0xE6000000 - 0xE62FFFFF SoC register area */
@ -116,7 +116,7 @@ const mmap_region_t rcar_mmap[] = {
#endif
#if IMAGE_BL31
const mmap_region_t rcar_mmap[] = {
static const mmap_region_t rcar_mmap[] = {
MAP_SHARED_RAM,
MAP_ATFW_CRASH,
MAP_ATFW_LOG,
@ -129,7 +129,7 @@ const mmap_region_t rcar_mmap[] = {
#endif
#if IMAGE_BL32
const mmap_region_t rcar_mmap[] = {
static const mmap_region_t rcar_mmap[] = {
MAP_DEVICE0,
MAP_DEVICE1,
{0}

48
plat/renesas/rcar/bl2_interrupt_error.c
View File

@ -24,7 +24,7 @@ void bl2_interrupt_error_id(uint32_t int_id)
ERROR("\n");
if (int_id >= SWDT_ERROR_ID) {
ERROR("Unhandled exception occurred.\n");
ERROR(" Exception type = FIQ_SP_ELX\n");
ERROR(" Exception type = FIQ_SP_EL0\n");
panic();
}
@ -32,11 +32,11 @@ void bl2_interrupt_error_id(uint32_t int_id)
gicv2_end_of_interrupt((uint32_t) int_id);
rcar_swdt_release();
ERROR("Unhandled exception occurred.\n");
ERROR(" Exception type = FIQ_SP_ELX\n");
ERROR(" SPSR_EL1 = 0x%x\n", (uint32_t) read_spsr_el1());
ERROR(" ELR_EL1 = 0x%x\n", (uint32_t) read_elr_el1());
ERROR(" ESR_EL1 = 0x%x\n", (uint32_t) read_esr_el1());
ERROR(" FAR_EL1 = 0x%x\n", (uint32_t) read_far_el1());
ERROR(" Exception type = FIQ_SP_EL0\n");
ERROR(" SPSR_EL3 = 0x%x\n", (uint32_t) read_spsr_el3());
ERROR(" ELR_EL3 = 0x%x\n", (uint32_t) read_elr_el3());
ERROR(" ESR_EL3 = 0x%x\n", (uint32_t) read_esr_el3());
ERROR(" FAR_EL3 = 0x%x\n", (uint32_t) read_far_el3());
ERROR("\n");
panic();
}
@ -78,27 +78,27 @@ void bl2_interrupt_error_type(uint32_t ex_type)
&interrupt_ex[ex_type][0]);
ERROR("%s", msg);
switch (ex_type) {
case SYNC_EXCEPTION_SP_ELX:
ERROR(" SPSR_EL1 = 0x%x\n", (uint32_t) read_spsr_el1());
ERROR(" ELR_EL1 = 0x%x\n", (uint32_t) read_elr_el1());
ERROR(" ESR_EL1 = 0x%x\n", (uint32_t) read_esr_el1());
ERROR(" FAR_EL1 = 0x%x\n", (uint32_t) read_far_el1());
case SYNC_EXCEPTION_SP_EL0:
ERROR(" SPSR_EL3 = 0x%x\n", (uint32_t) read_spsr_el3());
ERROR(" ELR_EL3 = 0x%x\n", (uint32_t) read_elr_el3());
ERROR(" ESR_EL3 = 0x%x\n", (uint32_t) read_esr_el3());
ERROR(" FAR_EL3 = 0x%x\n", (uint32_t) read_far_el3());
break;
case IRQ_SP_ELX:
ERROR(" SPSR_EL1 = 0x%x\n", (uint32_t) read_spsr_el1());
ERROR(" ELR_EL1 = 0x%x\n", (uint32_t) read_elr_el1());
ERROR(" IAR_EL1 = 0x%x\n", gicv2_acknowledge_interrupt());
case IRQ_SP_EL0:
ERROR(" SPSR_EL3 = 0x%x\n", (uint32_t) read_spsr_el3());
ERROR(" ELR_EL3 = 0x%x\n", (uint32_t) read_elr_el3());
ERROR(" IAR_EL3 = 0x%x\n", gicv2_acknowledge_interrupt());
break;
case FIQ_SP_ELX:
ERROR(" SPSR_EL1 = 0x%x\n", (uint32_t) read_spsr_el1());
ERROR(" ELR_EL1 = 0x%x\n", (uint32_t) read_elr_el1());
ERROR(" IAR_EL1 = 0x%x\n", gicv2_acknowledge_interrupt());
case FIQ_SP_EL0:
ERROR(" SPSR_EL3 = 0x%x\n", (uint32_t) read_spsr_el3());
ERROR(" ELR_EL3 = 0x%x\n", (uint32_t) read_elr_el3());
ERROR(" IAR_EL3 = 0x%x\n", gicv2_acknowledge_interrupt());
break;
case SERROR_SP_ELX:
ERROR(" SPSR_EL1 = 0x%x\n", (uint32_t) read_spsr_el1());
ERROR(" ELR_EL1 = 0x%x\n", (uint32_t) read_elr_el1());
ERROR(" ESR_EL1 = 0x%x\n", (uint32_t) read_esr_el1());
ERROR(" FAR_EL1 = 0x%x\n", (uint32_t) read_far_el1());
case SERROR_SP_EL0:
ERROR(" SPSR_EL3 = 0x%x\n", (uint32_t) read_spsr_el3());
ERROR(" ELR_EL3 = 0x%x\n", (uint32_t) read_elr_el3());
ERROR(" ESR_EL3 = 0x%x\n", (uint32_t) read_esr_el3());
ERROR(" FAR_EL3 = 0x%x\n", (uint32_t) read_far_el3());
break;
default:
break;

63
plat/renesas/rcar/bl2_plat_setup.c
View File

@ -61,6 +61,8 @@ extern void rcar_rpc_init(void);
extern void rcar_pfc_init(void);
extern void rcar_dma_init(void);
static void bl2_init_generic_timer(void);
/* R-Car Gen3 product check */
#if (RCAR_LSI == RCAR_H3) || (RCAR_LSI == RCAR_H3N)
#define TARGET_PRODUCT RCAR_PRODUCT_H3
@ -74,6 +76,8 @@ extern void rcar_dma_init(void);
#elif RCAR_LSI == RCAR_E3
#define TARGET_PRODUCT RCAR_PRODUCT_E3
#define TARGET_NAME "R-Car E3"
#elif RCAR_LSI == RCAR_AUTO
#define TARGET_NAME "R-Car H3/M3/M3N"
#endif
#if (RCAR_LSI == RCAR_E3)
@ -259,8 +263,10 @@ tlb:
product_cut == (RCAR_PRODUCT_M3N | RCAR_CUT_VER11)) {
mmio_write_32(IPMMUVI0_IMSCTLR, IMSCTLR_DISCACHE);
mmio_write_32(IPMMUPV0_IMSCTLR, IMSCTLR_DISCACHE);
} else if (product_cut == (RCAR_PRODUCT_E3 | RCAR_CUT_VER10)) {
} else if ((product_cut == (RCAR_PRODUCT_E3 | RCAR_CUT_VER10)) ||
(product_cut == (RCAR_PRODUCT_E3 | RCAR_CUT_VER11))) {
mmio_write_32(IPMMUVI0_IMSCTLR, IMSCTLR_DISCACHE);
mmio_write_32(IPMMUVP0_IMSCTLR, IMSCTLR_DISCACHE);
mmio_write_32(IPMMUPV0_IMSCTLR, IMSCTLR_DISCACHE);
}
@ -388,7 +394,7 @@ int bl2_plat_handle_post_image_load(unsigned int image_id)
return 0;
}
meminfo_t *bl2_plat_sec_mem_layout(void)
struct meminfo *bl2_plat_sec_mem_layout(void)
{
return &bl2_tzram_layout;
}
@ -624,6 +630,8 @@ void bl2_el3_early_platform_setup(u_register_t arg1, u_register_t arg2,
int fcnlnode;
#endif
bl2_init_generic_timer();
reg = mmio_read_32(RCAR_MODEMR);
boot_dev = reg & MODEMR_BOOT_DEV_MASK;
boot_cpu = reg & MODEMR_BOOT_CPU_MASK;
@ -899,7 +907,7 @@ void bl2_el3_plat_arch_setup(void)
#if RCAR_BL2_DCACHE == 1
NOTICE("BL2: D-Cache enable\n");
rcar_configure_mmu_el3(BL2_BASE,
RCAR_SYSRAM_LIMIT - BL2_BASE,
BL2_END - BL2_BASE,
BL2_RO_BASE, BL2_RO_LIMIT
#if USE_COHERENT_MEM
, BL2_COHERENT_RAM_BASE, BL2_COHERENT_RAM_LIMIT
@ -912,3 +920,52 @@ void bl2_platform_setup(void)
{
}
static void bl2_init_generic_timer(void)
{
#if RCAR_LSI == RCAR_E3
uint32_t reg_cntfid = EXTAL_EBISU;
#else /* RCAR_LSI == RCAR_E3 */
uint32_t reg;
uint32_t reg_cntfid;
uint32_t modemr;
uint32_t modemr_pll;
uint32_t board_type;
uint32_t board_rev;
uint32_t pll_table[] = {
EXTAL_MD14_MD13_TYPE_0, /* MD14/MD13 : 0b00 */
EXTAL_MD14_MD13_TYPE_1, /* MD14/MD13 : 0b01 */
EXTAL_MD14_MD13_TYPE_2, /* MD14/MD13 : 0b10 */
EXTAL_MD14_MD13_TYPE_3 /* MD14/MD13 : 0b11 */
};
modemr = mmio_read_32(RCAR_MODEMR);
modemr_pll = (modemr & MODEMR_BOOT_PLL_MASK);
/* Set frequency data in CNTFID0 */
reg_cntfid = pll_table[modemr_pll >> MODEMR_BOOT_PLL_SHIFT];
reg = mmio_read_32(RCAR_PRR) & (RCAR_PRODUCT_MASK | RCAR_CUT_MASK);
switch (modemr_pll) {
case MD14_MD13_TYPE_0:
rcar_get_board_type(&board_type, &board_rev);
if (BOARD_SALVATOR_XS == board_type) {
reg_cntfid = EXTAL_SALVATOR_XS;
}
break;
case MD14_MD13_TYPE_3:
if (RCAR_PRODUCT_H3_CUT10 == reg) {
reg_cntfid = reg_cntfid >> 1U;
}
break;
default:
/* none */
break;
}
#endif /* RCAR_LSI == RCAR_E3 */
/* Update memory mapped and register based freqency */
write_cntfrq_el0((u_register_t )reg_cntfid);
mmio_write_32(ARM_SYS_CNTCTL_BASE + (uintptr_t)CNTFID_OFF, reg_cntfid);
/* Enable counter */
mmio_setbits_32(RCAR_CNTC_BASE + (uintptr_t)CNTCR_OFF,
(uint32_t)CNTCR_EN);
}

3
plat/renesas/rcar/bl31_plat_setup.c
View File

@ -64,7 +64,7 @@ void plat_cci_disable(void)
cci_disable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr()));
}
entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type)
struct entry_point_info *bl31_plat_get_next_image_ep_info(uint32_t type)
{
bl2_to_bl31_params_mem_t *from_bl2 = (bl2_to_bl31_params_mem_t *)
PARAMS_BASE;
@ -100,6 +100,7 @@ void bl31_plat_arch_setup(void)
, BL31_COHERENT_RAM_BASE, BL31_COHERENT_RAM_LIMIT
#endif
);
rcar_pwrc_code_copy_to_system_ram();
}
void bl31_platform_setup(void)

10
plat/renesas/rcar/include/platform_def.h
View File

@ -79,7 +79,7 @@
* Cortex-A53
* L1:I/32KB(16KBx2way) D/32KB(8KBx4way) L2:512KB(32KBx16way)
*/
#define PLATFORM_CACHE_LINE_SIZE 128
#define PLATFORM_CACHE_LINE_SIZE 64
#define PLATFORM_CLUSTER_COUNT U(2)
#define PLATFORM_CLUSTER0_CORE_COUNT U(4)
#define PLATFORM_CLUSTER1_CORE_COUNT U(4)
@ -104,16 +104,16 @@
* size plus a little space for growth. */
#define RCAR_SYSRAM_BASE U(0xE6300000)
#if RCAR_LSI == RCAR_E3
#define RCAR_SYSRAM_LIMIT U(0xE6320000)
#define BL2_LIMIT U(0xE6320000)
#else
#define RCAR_SYSRAM_LIMIT U(0xE6360000)
#define BL2_LIMIT U(0xE6360000)
#endif
#define BL2_BASE U(0xE6304000)
#if RCAR_LSI == RCAR_E3
#define BL2_LIMIT U(0xE6318000)
#define BL2_IMAGE_LIMIT U(0xE6318000)
#else
#define BL2_LIMIT U(0xE632E800)
#define BL2_IMAGE_LIMIT U(0xE632E800)
#endif
#define RCAR_SYSRAM_SIZE (BL2_BASE - RCAR_SYSRAM_BASE)

4
plat/renesas/rcar/include/rcar_def.h
View File

@ -24,7 +24,7 @@
#define DEVICE_RCAR_SIZE U(0x00300000)
#define DEVICE_RCAR_BASE2 U(0xE6360000)
#define DEVICE_RCAR_SIZE2 U(0x19CA0000)
#define DEVICE_SRAM_BASE U(0xE6310000)
#define DEVICE_SRAM_BASE U(0xE6300000)
#define DEVICE_SRAM_SIZE U(0x00002000)
#define DEVICE_SRAM_STACK_BASE (DEVICE_SRAM_BASE + DEVICE_SRAM_SIZE)
#define DEVICE_SRAM_STACK_SIZE U(0x00001000)
@ -231,6 +231,8 @@
#define IPMMUMM_IMSCTLR_ENABLE (0xC0000000U)
#define IPMMUMM_IMAUXCTLR_NMERGE40_BIT (0x01000000U)
#define IMSCTLR_DISCACHE (0xE0000000U)
#define IPMMU_VP0_BASE (0xFE990000U)
#define IPMMUVP0_IMSCTLR (IPMMU_VP0_BASE + 0x0500U)
#define IPMMU_VI0_BASE (0xFEBD0000U)
#define IPMMUVI0_IMSCTLR (IPMMU_VI0_BASE + 0x0500U)
#define IPMMU_VI1_BASE (0xFEBE0000U)

2
plat/renesas/rcar/include/rcar_version.h
View File

@ -9,7 +9,7 @@
#include <arch_helpers.h>
#define VERSION_OF_RENESAS "1.0.22"
#define VERSION_OF_RENESAS "2.0.0"
#define VERSION_OF_RENESAS_MAXLEN (128)
extern const uint8_t version_of_renesas[VERSION_OF_RENESAS_MAXLEN];

10
plat/renesas/rcar/plat_pm.c
View File

@ -22,6 +22,7 @@
#include "pwrc.h"
#include "rcar_def.h"
#include "rcar_private.h"
#include "ulcb_cpld.h"
#define DVFS_SET_VID_0V (0x00)
#define P_ALL_OFF (0x80)
@ -41,10 +42,6 @@ extern void plat_rcar_gic_driver_init(void);
extern void plat_rcar_gic_init(void);
extern u_register_t rcar_boot_mpidr;
#if (RCAR_GEN3_ULCB == 1)
extern void rcar_cpld_reset_cpu(void);
#endif
static uintptr_t rcar_sec_entrypoint;
static void rcar_program_mailbox(uint64_t mpidr, uint64_t address)
@ -155,6 +152,7 @@ static void rcar_pwr_domain_suspend_finish(const psci_power_state_t
write_cntfrq_el0(plat_get_syscnt_freq2());
mmio_write_32(RCAR_CNTC_BASE + CNTCR_OFF, CNTCR_FCREQ(U(0)) | CNTCR_EN);
rcar_pwrc_setup();
rcar_pwrc_code_copy_to_system_ram();
#if RCAR_SYSTEM_SUSPEND
rcar_pwrc_init_suspend_to_ram();
@ -167,11 +165,9 @@ static void __dead2 rcar_system_off(void)
{
#if PMIC_ROHM_BD9571
#if PMIC_LEVEL_MODE
rcar_pwrc_code_copy_to_system_ram();
if (rcar_iic_dvfs_send(PMIC, DVFS_SET_VID, DVFS_SET_VID_0V))
ERROR("BL3-1:Failed the SYSTEM-OFF.\n");
#else
rcar_pwrc_code_copy_to_system_ram();
if (rcar_iic_dvfs_send(PMIC, BKUP_MODE_CNT, P_ALL_OFF))
ERROR("BL3-1:Failed the SYSTEM-RESET.\n");
#endif
@ -204,7 +200,6 @@ static void __dead2 rcar_system_reset(void)
uint8_t mode;
int32_t error;
rcar_pwrc_code_copy_to_system_ram();
error = rcar_iic_dvfs_send(PMIC, REG_KEEP10, KEEP10_MAGIC);
if (error) {
ERROR("Failed send KEEP10 magic ret=%d \n", error);
@ -227,7 +222,6 @@ static void __dead2 rcar_system_reset(void)
rcar_pwrc_set_suspend_to_ram();
done:
#else
rcar_pwrc_code_copy_to_system_ram();
if (rcar_iic_dvfs_send(PMIC, BKUP_MODE_CNT, P_ALL_OFF))
ERROR("BL3-1:Failed the SYSTEM-RESET.\n");
#endif

9
plat/renesas/rcar/platform.mk
View File

@ -4,13 +4,14 @@
# SPDX-License-Identifier: BSD-3-Clause
#
PROGRAMMABLE_RESET_ADDRESS := 0
PROGRAMMABLE_RESET_ADDRESS := 1
COLD_BOOT_SINGLE_CPU := 1
ARM_CCI_PRODUCT_ID := 500
TRUSTED_BOARD_BOOT := 1
RESET_TO_BL31 := 1
GENERATE_COT := 1
BL2_AT_EL3 := 1
ENABLE_SVE_FOR_NS := 0
$(eval $(call add_define,PLAT_EXTRA_LD_SCRIPT))
@ -310,6 +311,7 @@ PLAT_INCLUDES := -Iinclude/common/tbbr \
-Idrivers/staging/renesas/rcar/qos \
-Idrivers/renesas/rcar/iic_dvfs \
-Idrivers/renesas/rcar/board \
-Idrivers/renesas/rcar/cpld/ \
-Idrivers/renesas/rcar/avs \
-Idrivers/renesas/rcar/delay \
-Idrivers/renesas/rcar/rom \
@ -353,7 +355,7 @@ BL2_SOURCES += ${RCAR_GIC_SOURCES} \
drivers/renesas/rcar/rpc/rpc_driver.c \
drivers/renesas/rcar/dma/dma_driver.c \
drivers/renesas/rcar/avs/avs_driver.c \
drivers/renesas/rcar/delay/micro_delay.S \
drivers/renesas/rcar/delay/micro_delay.c \
drivers/renesas/rcar/emmc/emmc_interrupt.c \
drivers/renesas/rcar/emmc/emmc_utility.c \
drivers/renesas/rcar/emmc/emmc_mount.c \
@ -376,6 +378,7 @@ BL31_SOURCES += ${RCAR_GIC_SOURCES} \
plat/renesas/rcar/plat_pm.c \
drivers/renesas/rcar/console/rcar_console.S \
drivers/renesas/rcar/console/rcar_printf.c \
drivers/renesas/rcar/delay/micro_delay.c \
drivers/renesas/rcar/pwrc/call_sram.S \
drivers/renesas/rcar/pwrc/pwrc.c \
drivers/renesas/rcar/common.c \
@ -415,7 +418,7 @@ clean_srecord:
rm -f ${SREC_PATH}/bl2.srec ${SREC_PATH}/bl31.srec
.PHONY: rcar_srecord
rcar_srecord:
rcar_srecord: $(BL2_ELF_SRC) $(BL31_ELF_SRC)
@echo "generating srec: ${SREC_PATH}/bl2.srec"
$(Q)$(OC) -O srec --srec-forceS3 ${BL2_ELF_SRC} ${SREC_PATH}/bl2.srec
@echo "generating srec: ${SREC_PATH}/bl31.srec"