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Correct some typo errors in comment 

File: include/common/aarch64/el3_common_macros.S

Change-Id: I619401e961a3f627ad8864781b5f90bc747c3ddb
Signed-off-by: Qixiang Xu <qixiang.xu@arm.com>
This commit is contained in:
Qixiang Xu 2018-03-05 09:31:11 +08:00
parent 1f4d62df6c
commit 79c17995aa
1 changed files with 2 additions and 2 deletions
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include/common/aarch64/el3_common_macros.S
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@ -20,7 +20,7 @@
*
* SCTLR_EL3.I: Enable the instruction cache.
*
* SCTLR_EL3.SA: Enable Stack Aligment check. A SP alignment fault
* SCTLR_EL3.SA: Enable Stack Alignment check. A SP alignment fault
* exception is generated if a load or store instruction executed at
* EL3 uses the SP as the base address and the SP is not aligned to a
* 16-byte boundary.
@ -186,7 +186,7 @@
* XN (Execute-never). Set to zero so that this control has no
* effect on memory access permissions.
*
* SCTLR_EL3.SA: Set to zero to disable Stack Aligment check.
* SCTLR_EL3.SA: Set to zero to disable Stack Alignment check.
*
* SCTLR_EL3.A: Set to zero to disable Alignment fault checking.
* -------------------------------------------------------------