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@ -504,7 +504,7 @@ static void gen_rk3399_ctl_params_f0(struct timing_related_config
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(pdram_timing->tmod << 8) |
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(pdram_timing->tmod << 8) |
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pdram_timing->tmrd);
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pdram_timing->tmrd);
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mmio_clrsetbits_32(CTL_REG(i, 59), 0xffff << 16,
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mmio_clrsetbits_32(CTL_REG(i, 59), 0xffffu << 16,
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(pdram_timing->txsr -
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(pdram_timing->txsr -
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pdram_timing->trcd) << 16);
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pdram_timing->trcd) << 16);
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} else if (timing_config->dram_type == LPDDR4) {
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} else if (timing_config->dram_type == LPDDR4) {
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@ -513,7 +513,7 @@ static void gen_rk3399_ctl_params_f0(struct timing_related_config
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mmio_write_32(CTL_REG(i, 32),
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mmio_write_32(CTL_REG(i, 32),
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(pdram_timing->tmrd << 8) |
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(pdram_timing->tmrd << 8) |
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pdram_timing->tmrd);
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pdram_timing->tmrd);
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mmio_clrsetbits_32(CTL_REG(i, 59), 0xffff << 16,
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mmio_clrsetbits_32(CTL_REG(i, 59), 0xffffu << 16,
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pdram_timing->txsr << 16);
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pdram_timing->txsr << 16);
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} else {
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} else {
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mmio_write_32(CTL_REG(i, 5), pdram_timing->tinit1);
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mmio_write_32(CTL_REG(i, 5), pdram_timing->tinit1);
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@ -521,7 +521,7 @@ static void gen_rk3399_ctl_params_f0(struct timing_related_config
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mmio_write_32(CTL_REG(i, 32),
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mmio_write_32(CTL_REG(i, 32),
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(pdram_timing->tmrd << 8) |
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(pdram_timing->tmrd << 8) |
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pdram_timing->tmrd);
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pdram_timing->tmrd);
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mmio_clrsetbits_32(CTL_REG(i, 59), 0xffff << 16,
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mmio_clrsetbits_32(CTL_REG(i, 59), 0xffffu << 16,
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pdram_timing->txsr << 16);
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pdram_timing->txsr << 16);
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}
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}
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mmio_write_32(CTL_REG(i, 6), pdram_timing->tinit3);
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mmio_write_32(CTL_REG(i, 6), pdram_timing->tinit3);
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@ -531,7 +531,7 @@ static void gen_rk3399_ctl_params_f0(struct timing_related_config
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mmio_clrsetbits_32(CTL_REG(i, 23), (0x1f << 24),
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mmio_clrsetbits_32(CTL_REG(i, 23), (0x1f << 24),
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(pdram_timing->cwl << 24));
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(pdram_timing->cwl << 24));
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mmio_clrsetbits_32(CTL_REG(i, 24), 0x3f, pdram_timing->al);
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mmio_clrsetbits_32(CTL_REG(i, 24), 0x3f, pdram_timing->al);
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mmio_clrsetbits_32(CTL_REG(i, 26), 0xffff << 16,
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mmio_clrsetbits_32(CTL_REG(i, 26), 0xffffu << 16,
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(pdram_timing->trc << 24) |
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(pdram_timing->trc << 24) |
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(pdram_timing->trrd << 16));
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(pdram_timing->trrd << 16));
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mmio_write_32(CTL_REG(i, 27),
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mmio_write_32(CTL_REG(i, 27),
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@ -540,7 +540,7 @@ static void gen_rk3399_ctl_params_f0(struct timing_related_config
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(pdram_timing->twtr << 8) |
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(pdram_timing->twtr << 8) |
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pdram_timing->tras_min);
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pdram_timing->tras_min);
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mmio_clrsetbits_32(CTL_REG(i, 31), 0xff << 24,
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mmio_clrsetbits_32(CTL_REG(i, 31), 0xffu << 24,
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max(4, pdram_timing->trtp) << 24);
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max(4, pdram_timing->trtp) << 24);
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mmio_write_32(CTL_REG(i, 33), (pdram_timing->tcke << 24) |
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mmio_write_32(CTL_REG(i, 33), (pdram_timing->tcke << 24) |
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pdram_timing->tras_max);
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pdram_timing->tras_max);
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@ -560,7 +560,7 @@ static void gen_rk3399_ctl_params_f0(struct timing_related_config
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((pdram_timing->trefi - 8) << 16) |
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((pdram_timing->trefi - 8) << 16) |
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pdram_timing->trfc);
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pdram_timing->trfc);
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mmio_clrsetbits_32(CTL_REG(i, 52), 0xffff, pdram_timing->txp);
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mmio_clrsetbits_32(CTL_REG(i, 52), 0xffff, pdram_timing->txp);
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mmio_clrsetbits_32(CTL_REG(i, 53), 0xffff << 16,
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mmio_clrsetbits_32(CTL_REG(i, 53), 0xffffu << 16,
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pdram_timing->txpdll << 16);
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pdram_timing->txpdll << 16);
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mmio_clrsetbits_32(CTL_REG(i, 55), 0xf << 24,
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mmio_clrsetbits_32(CTL_REG(i, 55), 0xf << 24,
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pdram_timing->tcscke << 24);
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pdram_timing->tcscke << 24);
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@ -571,7 +571,7 @@ static void gen_rk3399_ctl_params_f0(struct timing_related_config
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(pdram_timing->tckehcs << 8) |
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(pdram_timing->tckehcs << 8) |
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pdram_timing->tckelcs);
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pdram_timing->tckelcs);
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mmio_clrsetbits_32(CTL_REG(i, 60), 0xffff, pdram_timing->txsnr);
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mmio_clrsetbits_32(CTL_REG(i, 60), 0xffff, pdram_timing->txsnr);
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mmio_clrsetbits_32(CTL_REG(i, 62), 0xffff << 16,
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mmio_clrsetbits_32(CTL_REG(i, 62), 0xffffu << 16,
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(pdram_timing->tckehcmd << 24) |
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(pdram_timing->tckehcmd << 24) |
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(pdram_timing->tckelcmd << 16));
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(pdram_timing->tckelcmd << 16));
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mmio_write_32(CTL_REG(i, 63),
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mmio_write_32(CTL_REG(i, 63),
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@ -601,7 +601,7 @@ static void gen_rk3399_ctl_params_f0(struct timing_related_config
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pdram_timing->mr[2]);
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pdram_timing->mr[2]);
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mmio_clrsetbits_32(CTL_REG(i, 138), 0xffff,
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mmio_clrsetbits_32(CTL_REG(i, 138), 0xffff,
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pdram_timing->mr[3]);
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pdram_timing->mr[3]);
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mmio_clrsetbits_32(CTL_REG(i, 139), 0xff << 24,
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mmio_clrsetbits_32(CTL_REG(i, 139), 0xffu << 24,
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pdram_timing->mr11 << 24);
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pdram_timing->mr11 << 24);
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mmio_write_32(CTL_REG(i, 147),
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mmio_write_32(CTL_REG(i, 147),
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(pdram_timing->mr[1] << 16) |
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(pdram_timing->mr[1] << 16) |
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@ -610,20 +610,20 @@ static void gen_rk3399_ctl_params_f0(struct timing_related_config
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pdram_timing->mr[2]);
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pdram_timing->mr[2]);
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mmio_clrsetbits_32(CTL_REG(i, 152), 0xffff,
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mmio_clrsetbits_32(CTL_REG(i, 152), 0xffff,
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pdram_timing->mr[3]);
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pdram_timing->mr[3]);
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mmio_clrsetbits_32(CTL_REG(i, 153), 0xff << 24,
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mmio_clrsetbits_32(CTL_REG(i, 153), 0xffu << 24,
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pdram_timing->mr11 << 24);
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pdram_timing->mr11 << 24);
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if (timing_config->dram_type == LPDDR4) {
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if (timing_config->dram_type == LPDDR4) {
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mmio_clrsetbits_32(CTL_REG(i, 140), 0xffff << 16,
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mmio_clrsetbits_32(CTL_REG(i, 140), 0xffffu << 16,
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pdram_timing->mr12 << 16);
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pdram_timing->mr12 << 16);
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mmio_clrsetbits_32(CTL_REG(i, 142), 0xffff << 16,
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mmio_clrsetbits_32(CTL_REG(i, 142), 0xffffu << 16,
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pdram_timing->mr14 << 16);
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pdram_timing->mr14 << 16);
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mmio_clrsetbits_32(CTL_REG(i, 145), 0xffff << 16,
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mmio_clrsetbits_32(CTL_REG(i, 145), 0xffffu << 16,
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pdram_timing->mr22 << 16);
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pdram_timing->mr22 << 16);
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mmio_clrsetbits_32(CTL_REG(i, 154), 0xffff << 16,
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mmio_clrsetbits_32(CTL_REG(i, 154), 0xffffu << 16,
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pdram_timing->mr12 << 16);
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pdram_timing->mr12 << 16);
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mmio_clrsetbits_32(CTL_REG(i, 156), 0xffff << 16,
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mmio_clrsetbits_32(CTL_REG(i, 156), 0xffffu << 16,
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pdram_timing->mr14 << 16);
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pdram_timing->mr14 << 16);
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mmio_clrsetbits_32(CTL_REG(i, 159), 0xffff << 16,
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mmio_clrsetbits_32(CTL_REG(i, 159), 0xffffu << 16,
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pdram_timing->mr22 << 16);
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pdram_timing->mr22 << 16);
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}
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}
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mmio_clrsetbits_32(CTL_REG(i, 179), 0xfff << 8,
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mmio_clrsetbits_32(CTL_REG(i, 179), 0xfff << 8,
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@ -655,7 +655,7 @@ static void gen_rk3399_ctl_params_f0(struct timing_related_config
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<< 8) | get_rdlat_adj(timing_config->dram_type,
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<< 8) | get_rdlat_adj(timing_config->dram_type,
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pdram_timing->cl);
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pdram_timing->cl);
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mmio_clrsetbits_32(CTL_REG(i, 284), 0xffff, tmp);
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mmio_clrsetbits_32(CTL_REG(i, 284), 0xffff, tmp);
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mmio_clrsetbits_32(CTL_REG(i, 82), 0xffff << 16,
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mmio_clrsetbits_32(CTL_REG(i, 82), 0xffffu << 16,
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(4 * pdram_timing->trefi) << 16);
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(4 * pdram_timing->trefi) << 16);
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mmio_clrsetbits_32(CTL_REG(i, 83), 0xffff,
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mmio_clrsetbits_32(CTL_REG(i, 83), 0xffff,
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@ -748,13 +748,13 @@ static void gen_rk3399_ctl_params_f1(struct timing_related_config
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tmp += pdram_timing->txsnr + (pdram_timing->tmrd * 3) +
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tmp += pdram_timing->txsnr + (pdram_timing->tmrd * 3) +
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pdram_timing->tmod + pdram_timing->tzqinit;
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pdram_timing->tmod + pdram_timing->tzqinit;
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mmio_write_32(CTL_REG(i, 9), tmp);
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mmio_write_32(CTL_REG(i, 9), tmp);
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mmio_clrsetbits_32(CTL_REG(i, 22), 0xffff << 16,
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mmio_clrsetbits_32(CTL_REG(i, 22), 0xffffu << 16,
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pdram_timing->tdllk << 16);
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pdram_timing->tdllk << 16);
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mmio_clrsetbits_32(CTL_REG(i, 34), 0xffffff00,
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mmio_clrsetbits_32(CTL_REG(i, 34), 0xffffff00,
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(pdram_timing->tmod << 24) |
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(pdram_timing->tmod << 24) |
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(pdram_timing->tmrd << 16) |
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(pdram_timing->tmrd << 16) |
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(pdram_timing->trtp << 8));
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(pdram_timing->trtp << 8));
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mmio_clrsetbits_32(CTL_REG(i, 60), 0xffff << 16,
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mmio_clrsetbits_32(CTL_REG(i, 60), 0xffffu << 16,
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(pdram_timing->txsr -
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(pdram_timing->txsr -
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pdram_timing->trcd) << 16);
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pdram_timing->trcd) << 16);
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} else if (timing_config->dram_type == LPDDR4) {
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} else if (timing_config->dram_type == LPDDR4) {
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@ -764,7 +764,7 @@ static void gen_rk3399_ctl_params_f1(struct timing_related_config
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(pdram_timing->tmrd << 24) |
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(pdram_timing->tmrd << 24) |
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(pdram_timing->tmrd << 16) |
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(pdram_timing->tmrd << 16) |
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(pdram_timing->trtp << 8));
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(pdram_timing->trtp << 8));
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mmio_clrsetbits_32(CTL_REG(i, 60), 0xffff << 16,
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mmio_clrsetbits_32(CTL_REG(i, 60), 0xffffu << 16,
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pdram_timing->txsr << 16);
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pdram_timing->txsr << 16);
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} else {
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} else {
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mmio_write_32(CTL_REG(i, 9), pdram_timing->tinit1);
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mmio_write_32(CTL_REG(i, 9), pdram_timing->tinit1);
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@ -773,7 +773,7 @@ static void gen_rk3399_ctl_params_f1(struct timing_related_config
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(pdram_timing->tmrd << 24) |
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(pdram_timing->tmrd << 24) |
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(pdram_timing->tmrd << 16) |
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(pdram_timing->tmrd << 16) |
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(pdram_timing->trtp << 8));
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(pdram_timing->trtp << 8));
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mmio_clrsetbits_32(CTL_REG(i, 60), 0xffff << 16,
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mmio_clrsetbits_32(CTL_REG(i, 60), 0xffffu << 16,
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pdram_timing->txsr << 16);
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pdram_timing->txsr << 16);
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}
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}
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mmio_write_32(CTL_REG(i, 10), pdram_timing->tinit3);
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mmio_write_32(CTL_REG(i, 10), pdram_timing->tinit3);
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@ -796,7 +796,7 @@ static void gen_rk3399_ctl_params_f1(struct timing_related_config
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pdram_timing->tras_max);
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pdram_timing->tras_max);
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mmio_clrsetbits_32(CTL_REG(i, 36), 0xff,
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mmio_clrsetbits_32(CTL_REG(i, 36), 0xff,
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max(1, pdram_timing->tckesr));
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max(1, pdram_timing->tckesr));
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mmio_clrsetbits_32(CTL_REG(i, 39), (0xff << 24),
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mmio_clrsetbits_32(CTL_REG(i, 39), (0xffu << 24),
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(pdram_timing->trcd << 24));
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(pdram_timing->trcd << 24));
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mmio_clrsetbits_32(CTL_REG(i, 40), 0x3f, pdram_timing->twr);
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mmio_clrsetbits_32(CTL_REG(i, 40), 0x3f, pdram_timing->twr);
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mmio_clrsetbits_32(CTL_REG(i, 42), 0x1f << 24,
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mmio_clrsetbits_32(CTL_REG(i, 42), 0x1f << 24,
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@ -809,7 +809,7 @@ static void gen_rk3399_ctl_params_f1(struct timing_related_config
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mmio_write_32(CTL_REG(i, 49),
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mmio_write_32(CTL_REG(i, 49),
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((pdram_timing->trefi - 8) << 16) |
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((pdram_timing->trefi - 8) << 16) |
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pdram_timing->trfc);
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pdram_timing->trfc);
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mmio_clrsetbits_32(CTL_REG(i, 52), 0xffff << 16,
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mmio_clrsetbits_32(CTL_REG(i, 52), 0xffffu << 16,
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pdram_timing->txp << 16);
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pdram_timing->txp << 16);
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mmio_clrsetbits_32(CTL_REG(i, 54), 0xffff,
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mmio_clrsetbits_32(CTL_REG(i, 54), 0xffff,
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pdram_timing->txpdll);
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pdram_timing->txpdll);
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@ -821,7 +821,7 @@ static void gen_rk3399_ctl_params_f1(struct timing_related_config
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pdram_timing->tcscke);
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pdram_timing->tcscke);
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mmio_clrsetbits_32(CTL_REG(i, 58), 0xf, pdram_timing->tzqcke);
|
|
|
|
mmio_clrsetbits_32(CTL_REG(i, 58), 0xf, pdram_timing->tzqcke);
|
|
|
|
mmio_clrsetbits_32(CTL_REG(i, 61), 0xffff, pdram_timing->txsnr);
|
|
|
|
mmio_clrsetbits_32(CTL_REG(i, 61), 0xffff, pdram_timing->txsnr);
|
|
|
|
mmio_clrsetbits_32(CTL_REG(i, 64), 0xffff << 16,
|
|
|
|
mmio_clrsetbits_32(CTL_REG(i, 64), 0xffffu << 16,
|
|
|
|
(pdram_timing->tckehcmd << 24) |
|
|
|
|
(pdram_timing->tckehcmd << 24) |
|
|
|
|
(pdram_timing->tckelcmd << 16));
|
|
|
|
(pdram_timing->tckelcmd << 16));
|
|
|
|
mmio_write_32(CTL_REG(i, 65), (pdram_timing->tckelpd << 24) |
|
|
|
|
mmio_write_32(CTL_REG(i, 65), (pdram_timing->tckelpd << 24) |
|
|
|
@ -831,7 +831,7 @@ static void gen_rk3399_ctl_params_f1(struct timing_related_config
|
|
|
|
mmio_clrsetbits_32(CTL_REG(i, 66), 0xfff,
|
|
|
|
mmio_clrsetbits_32(CTL_REG(i, 66), 0xfff,
|
|
|
|
(pdram_timing->tcmdcke << 8) |
|
|
|
|
(pdram_timing->tcmdcke << 8) |
|
|
|
|
pdram_timing->tcsckeh);
|
|
|
|
pdram_timing->tcsckeh);
|
|
|
|
mmio_clrsetbits_32(CTL_REG(i, 92), (0xff << 24),
|
|
|
|
mmio_clrsetbits_32(CTL_REG(i, 92), (0xffu << 24),
|
|
|
|
(pdram_timing->tcksre << 24));
|
|
|
|
(pdram_timing->tcksre << 24));
|
|
|
|
mmio_clrsetbits_32(CTL_REG(i, 93), 0xff,
|
|
|
|
mmio_clrsetbits_32(CTL_REG(i, 93), 0xff,
|
|
|
|
pdram_timing->tcksrx);
|
|
|
|
pdram_timing->tcksrx);
|
|
|
@ -845,18 +845,18 @@ static void gen_rk3399_ctl_params_f1(struct timing_related_config
|
|
|
|
pdram_timing->tfc_long);
|
|
|
|
pdram_timing->tfc_long);
|
|
|
|
mmio_clrsetbits_32(CTL_REG(i, 127), 0xffff,
|
|
|
|
mmio_clrsetbits_32(CTL_REG(i, 127), 0xffff,
|
|
|
|
pdram_timing->tvref_long);
|
|
|
|
pdram_timing->tvref_long);
|
|
|
|
mmio_clrsetbits_32(CTL_REG(i, 134), 0xffff << 16,
|
|
|
|
mmio_clrsetbits_32(CTL_REG(i, 134), 0xffffu << 16,
|
|
|
|
pdram_timing->mr[0] << 16);
|
|
|
|
pdram_timing->mr[0] << 16);
|
|
|
|
mmio_write_32(CTL_REG(i, 135), (pdram_timing->mr[2] << 16) |
|
|
|
|
mmio_write_32(CTL_REG(i, 135), (pdram_timing->mr[2] << 16) |
|
|
|
|
pdram_timing->mr[1]);
|
|
|
|
pdram_timing->mr[1]);
|
|
|
|
mmio_clrsetbits_32(CTL_REG(i, 138), 0xffff << 16,
|
|
|
|
mmio_clrsetbits_32(CTL_REG(i, 138), 0xffffu << 16,
|
|
|
|
pdram_timing->mr[3] << 16);
|
|
|
|
pdram_timing->mr[3] << 16);
|
|
|
|
mmio_clrsetbits_32(CTL_REG(i, 140), 0xff, pdram_timing->mr11);
|
|
|
|
mmio_clrsetbits_32(CTL_REG(i, 140), 0xff, pdram_timing->mr11);
|
|
|
|
mmio_clrsetbits_32(CTL_REG(i, 148), 0xffff << 16,
|
|
|
|
mmio_clrsetbits_32(CTL_REG(i, 148), 0xffffu << 16,
|
|
|
|
pdram_timing->mr[0] << 16);
|
|
|
|
pdram_timing->mr[0] << 16);
|
|
|
|
mmio_write_32(CTL_REG(i, 149), (pdram_timing->mr[2] << 16) |
|
|
|
|
mmio_write_32(CTL_REG(i, 149), (pdram_timing->mr[2] << 16) |
|
|
|
|
pdram_timing->mr[1]);
|
|
|
|
pdram_timing->mr[1]);
|
|
|
|
mmio_clrsetbits_32(CTL_REG(i, 152), 0xffff << 16,
|
|
|
|
mmio_clrsetbits_32(CTL_REG(i, 152), 0xffffu << 16,
|
|
|
|
pdram_timing->mr[3] << 16);
|
|
|
|
pdram_timing->mr[3] << 16);
|
|
|
|
mmio_clrsetbits_32(CTL_REG(i, 154), 0xff, pdram_timing->mr11);
|
|
|
|
mmio_clrsetbits_32(CTL_REG(i, 154), 0xff, pdram_timing->mr11);
|
|
|
|
if (timing_config->dram_type == LPDDR4) {
|
|
|
|
if (timing_config->dram_type == LPDDR4) {
|
|
|
@ -907,7 +907,7 @@ static void gen_rk3399_ctl_params_f1(struct timing_related_config
|
|
|
|
mmio_clrsetbits_32(CTL_REG(i, 84), 0xffff,
|
|
|
|
mmio_clrsetbits_32(CTL_REG(i, 84), 0xffff,
|
|
|
|
(4 * pdram_timing->trefi) & 0xffff);
|
|
|
|
(4 * pdram_timing->trefi) & 0xffff);
|
|
|
|
|
|
|
|
|
|
|
|
mmio_clrsetbits_32(CTL_REG(i, 84), 0xffff << 16,
|
|
|
|
mmio_clrsetbits_32(CTL_REG(i, 84), 0xffffu << 16,
|
|
|
|
((2 * pdram_timing->trefi) & 0xffff) << 16);
|
|
|
|
((2 * pdram_timing->trefi) & 0xffff) << 16);
|
|
|
|
|
|
|
|
|
|
|
|
if ((timing_config->dram_type == LPDDR3) ||
|
|
|
|
if ((timing_config->dram_type == LPDDR3) ||
|
|
|
@ -936,12 +936,12 @@ static void gen_rk3399_ctl_params_f1(struct timing_related_config
|
|
|
|
mmio_clrsetbits_32(CTL_REG(i, 215), 0x3f << 16,
|
|
|
|
mmio_clrsetbits_32(CTL_REG(i, 215), 0x3f << 16,
|
|
|
|
(tmp & 0x3f) << 16);
|
|
|
|
(tmp & 0x3f) << 16);
|
|
|
|
|
|
|
|
|
|
|
|
mmio_clrsetbits_32(CTL_REG(i, 275), 0xff << 24,
|
|
|
|
mmio_clrsetbits_32(CTL_REG(i, 275), 0xffu << 24,
|
|
|
|
(get_pi_tdfi_phy_rdlat(pdram_timing,
|
|
|
|
(get_pi_tdfi_phy_rdlat(pdram_timing,
|
|
|
|
timing_config) &
|
|
|
|
timing_config) &
|
|
|
|
0xff) << 24);
|
|
|
|
0xff) << 24);
|
|
|
|
|
|
|
|
|
|
|
|
mmio_clrsetbits_32(CTL_REG(i, 284), 0xffff << 16,
|
|
|
|
mmio_clrsetbits_32(CTL_REG(i, 284), 0xffffu << 16,
|
|
|
|
((2 * pdram_timing->trefi) & 0xffff) << 16);
|
|
|
|
((2 * pdram_timing->trefi) & 0xffff) << 16);
|
|
|
|
|
|
|
|
|
|
|
|
mmio_clrsetbits_32(CTL_REG(i, 289), 0xffff,
|
|
|
|
mmio_clrsetbits_32(CTL_REG(i, 289), 0xffff,
|
|
|
@ -973,7 +973,7 @@ static void gen_rk3399_ctl_params_f1(struct timing_related_config
|
|
|
|
tmp = tmp1 - 2;
|
|
|
|
tmp = tmp1 - 2;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
mmio_clrsetbits_32(CTL_REG(i, 314), 0xff << 24, tmp << 24);
|
|
|
|
mmio_clrsetbits_32(CTL_REG(i, 314), 0xffu << 24, tmp << 24);
|
|
|
|
|
|
|
|
|
|
|
|
/* CTL_314 TDFI_RDCSLAT_F1:RW:16:8 */
|
|
|
|
/* CTL_314 TDFI_RDCSLAT_F1:RW:16:8 */
|
|
|
|
if ((timing_config->freq <= TDFI_LAT_THRESHOLD_FREQ) &&
|
|
|
|
if ((timing_config->freq <= TDFI_LAT_THRESHOLD_FREQ) &&
|
|
|
@ -1036,7 +1036,7 @@ static void gen_rk3399_pi_params_f0(struct timing_related_config *timing_config,
|
|
|
|
tmp = 2 * pdram_timing->trefi;
|
|
|
|
tmp = 2 * pdram_timing->trefi;
|
|
|
|
mmio_clrsetbits_32(PI_REG(i, 3), 0xffff, tmp);
|
|
|
|
mmio_clrsetbits_32(PI_REG(i, 3), 0xffff, tmp);
|
|
|
|
/* PI_07 PI_TDFI_PHYUPD_RESP_F0:RW:16:16 */
|
|
|
|
/* PI_07 PI_TDFI_PHYUPD_RESP_F0:RW:16:16 */
|
|
|
|
mmio_clrsetbits_32(PI_REG(i, 7), 0xffff << 16, tmp << 16);
|
|
|
|
mmio_clrsetbits_32(PI_REG(i, 7), 0xffffu << 16, tmp << 16);
|
|
|
|
|
|
|
|
|
|
|
|
/* PI_42 PI_TDELAY_RDWR_2_BUS_IDLE_F0:RW:0:8 */
|
|
|
|
/* PI_42 PI_TDELAY_RDWR_2_BUS_IDLE_F0:RW:0:8 */
|
|
|
|
if (timing_config->dram_type == LPDDR4)
|
|
|
|
if (timing_config->dram_type == LPDDR4)
|
|
|
@ -1060,14 +1060,14 @@ static void gen_rk3399_pi_params_f0(struct timing_related_config *timing_config,
|
|
|
|
mmio_clrsetbits_32(PI_REG(i, 43), 0x7f << 16,
|
|
|
|
mmio_clrsetbits_32(PI_REG(i, 43), 0x7f << 16,
|
|
|
|
(pdram_timing->cl * 2) << 16);
|
|
|
|
(pdram_timing->cl * 2) << 16);
|
|
|
|
/* PI_46 PI_TREF_F0:RW:16:16 */
|
|
|
|
/* PI_46 PI_TREF_F0:RW:16:16 */
|
|
|
|
mmio_clrsetbits_32(PI_REG(i, 46), 0xffff << 16,
|
|
|
|
mmio_clrsetbits_32(PI_REG(i, 46), 0xffffu << 16,
|
|
|
|
pdram_timing->trefi << 16);
|
|
|
|
pdram_timing->trefi << 16);
|
|
|
|
/* PI_46 PI_TRFC_F0:RW:0:10 */
|
|
|
|
/* PI_46 PI_TRFC_F0:RW:0:10 */
|
|
|
|
mmio_clrsetbits_32(PI_REG(i, 46), 0x3ff, pdram_timing->trfc);
|
|
|
|
mmio_clrsetbits_32(PI_REG(i, 46), 0x3ff, pdram_timing->trfc);
|
|
|
|
/* PI_66 PI_TODTL_2CMD_F0:RW:24:8 */
|
|
|
|
/* PI_66 PI_TODTL_2CMD_F0:RW:24:8 */
|
|
|
|
if (timing_config->dram_type == LPDDR3) {
|
|
|
|
if (timing_config->dram_type == LPDDR3) {
|
|
|
|
tmp = get_pi_todtoff_max(pdram_timing, timing_config);
|
|
|
|
tmp = get_pi_todtoff_max(pdram_timing, timing_config);
|
|
|
|
mmio_clrsetbits_32(PI_REG(i, 66), 0xff << 24,
|
|
|
|
mmio_clrsetbits_32(PI_REG(i, 66), 0xffu << 24,
|
|
|
|
tmp << 24);
|
|
|
|
tmp << 24);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
/* PI_72 PI_WR_TO_ODTH_F0:RW:16:6 */
|
|
|
|
/* PI_72 PI_WR_TO_ODTH_F0:RW:16:6 */
|
|
|
@ -1148,19 +1148,19 @@ static void gen_rk3399_pi_params_f0(struct timing_related_config *timing_config,
|
|
|
|
/* PI_133 PI_MR1_DATA_F0_1:RW+:0:16 */
|
|
|
|
/* PI_133 PI_MR1_DATA_F0_1:RW+:0:16 */
|
|
|
|
mmio_clrsetbits_32(PI_REG(i, 133), 0xffff, pdram_timing->mr[1]);
|
|
|
|
mmio_clrsetbits_32(PI_REG(i, 133), 0xffff, pdram_timing->mr[1]);
|
|
|
|
/* PI_140 PI_MR1_DATA_F0_2:RW+:16:16 */
|
|
|
|
/* PI_140 PI_MR1_DATA_F0_2:RW+:16:16 */
|
|
|
|
mmio_clrsetbits_32(PI_REG(i, 140), 0xffff << 16,
|
|
|
|
mmio_clrsetbits_32(PI_REG(i, 140), 0xffffu << 16,
|
|
|
|
pdram_timing->mr[1] << 16);
|
|
|
|
pdram_timing->mr[1] << 16);
|
|
|
|
/* PI_148 PI_MR1_DATA_F0_3:RW+:0:16 */
|
|
|
|
/* PI_148 PI_MR1_DATA_F0_3:RW+:0:16 */
|
|
|
|
mmio_clrsetbits_32(PI_REG(i, 148), 0xffff, pdram_timing->mr[1]);
|
|
|
|
mmio_clrsetbits_32(PI_REG(i, 148), 0xffff, pdram_timing->mr[1]);
|
|
|
|
/* PI_126 PI_MR2_DATA_F0_0:RW+:0:16 */
|
|
|
|
/* PI_126 PI_MR2_DATA_F0_0:RW+:0:16 */
|
|
|
|
mmio_clrsetbits_32(PI_REG(i, 126), 0xffff, pdram_timing->mr[2]);
|
|
|
|
mmio_clrsetbits_32(PI_REG(i, 126), 0xffff, pdram_timing->mr[2]);
|
|
|
|
/* PI_133 PI_MR2_DATA_F0_1:RW+:16:16 */
|
|
|
|
/* PI_133 PI_MR2_DATA_F0_1:RW+:16:16 */
|
|
|
|
mmio_clrsetbits_32(PI_REG(i, 133), 0xffff << 16,
|
|
|
|
mmio_clrsetbits_32(PI_REG(i, 133), 0xffffu << 16,
|
|
|
|
pdram_timing->mr[2] << 16);
|
|
|
|
pdram_timing->mr[2] << 16);
|
|
|
|
/* PI_141 PI_MR2_DATA_F0_2:RW+:0:16 */
|
|
|
|
/* PI_141 PI_MR2_DATA_F0_2:RW+:0:16 */
|
|
|
|
mmio_clrsetbits_32(PI_REG(i, 141), 0xffff, pdram_timing->mr[2]);
|
|
|
|
mmio_clrsetbits_32(PI_REG(i, 141), 0xffff, pdram_timing->mr[2]);
|
|
|
|
/* PI_148 PI_MR2_DATA_F0_3:RW+:16:16 */
|
|
|
|
/* PI_148 PI_MR2_DATA_F0_3:RW+:16:16 */
|
|
|
|
mmio_clrsetbits_32(PI_REG(i, 148), 0xffff << 16,
|
|
|
|
mmio_clrsetbits_32(PI_REG(i, 148), 0xffffu << 16,
|
|
|
|
pdram_timing->mr[2] << 16);
|
|
|
|
pdram_timing->mr[2] << 16);
|
|
|
|
/* PI_156 PI_TFC_F0:RW:0:10 */
|
|
|
|
/* PI_156 PI_TFC_F0:RW:0:10 */
|
|
|
|
mmio_clrsetbits_32(PI_REG(i, 156), 0x3ff,
|
|
|
|
mmio_clrsetbits_32(PI_REG(i, 156), 0x3ff,
|
|
|
@ -1177,10 +1177,10 @@ static void gen_rk3399_pi_params_f0(struct timing_related_config *timing_config,
|
|
|
|
/* PI_158 PI_TRP_F0:RW:0:8 */
|
|
|
|
/* PI_158 PI_TRP_F0:RW:0:8 */
|
|
|
|
mmio_clrsetbits_32(PI_REG(i, 158), 0xff, pdram_timing->trp);
|
|
|
|
mmio_clrsetbits_32(PI_REG(i, 158), 0xff, pdram_timing->trp);
|
|
|
|
/* PI_157 PI_TRTP_F0:RW:24:8 */
|
|
|
|
/* PI_157 PI_TRTP_F0:RW:24:8 */
|
|
|
|
mmio_clrsetbits_32(PI_REG(i, 157), 0xff << 24,
|
|
|
|
mmio_clrsetbits_32(PI_REG(i, 157), 0xffu << 24,
|
|
|
|
pdram_timing->trtp << 24);
|
|
|
|
pdram_timing->trtp << 24);
|
|
|
|
/* PI_159 PI_TRAS_MIN_F0:RW:24:8 */
|
|
|
|
/* PI_159 PI_TRAS_MIN_F0:RW:24:8 */
|
|
|
|
mmio_clrsetbits_32(PI_REG(i, 159), 0xff << 24,
|
|
|
|
mmio_clrsetbits_32(PI_REG(i, 159), 0xffu << 24,
|
|
|
|
pdram_timing->tras_min << 24);
|
|
|
|
pdram_timing->tras_min << 24);
|
|
|
|
/* PI_159 PI_TRAS_MAX_F0:RW:0:17 */
|
|
|
|
/* PI_159 PI_TRAS_MAX_F0:RW:0:17 */
|
|
|
|
tmp = pdram_timing->tras_max * 99 / 100;
|
|
|
|
tmp = pdram_timing->tras_max * 99 / 100;
|
|
|
@ -1237,7 +1237,7 @@ static void gen_rk3399_pi_params_f1(struct timing_related_config *timing_config,
|
|
|
|
mmio_clrsetbits_32(PI_REG(i, 44), 0x7f << 8,
|
|
|
|
mmio_clrsetbits_32(PI_REG(i, 44), 0x7f << 8,
|
|
|
|
(pdram_timing->cl * 2) << 8);
|
|
|
|
(pdram_timing->cl * 2) << 8);
|
|
|
|
/* PI_47 PI_TREF_F1:RW:16:16 */
|
|
|
|
/* PI_47 PI_TREF_F1:RW:16:16 */
|
|
|
|
mmio_clrsetbits_32(PI_REG(i, 47), 0xffff << 16,
|
|
|
|
mmio_clrsetbits_32(PI_REG(i, 47), 0xffffu << 16,
|
|
|
|
pdram_timing->trefi << 16);
|
|
|
|
pdram_timing->trefi << 16);
|
|
|
|
/* PI_47 PI_TRFC_F1:RW:0:10 */
|
|
|
|
/* PI_47 PI_TRFC_F1:RW:0:10 */
|
|
|
|
mmio_clrsetbits_32(PI_REG(i, 47), 0x3ff, pdram_timing->trfc);
|
|
|
|
mmio_clrsetbits_32(PI_REG(i, 47), 0x3ff, pdram_timing->trfc);
|
|
|
@ -1278,10 +1278,10 @@ static void gen_rk3399_pi_params_f1(struct timing_related_config *timing_config,
|
|
|
|
mmio_clrsetbits_32(PI_REG(i, 73), 0x3f << 16, tmp << 16);
|
|
|
|
mmio_clrsetbits_32(PI_REG(i, 73), 0x3f << 16, tmp << 16);
|
|
|
|
/*P I_89 PI_RDLAT_ADJ_F1:RW:24:8 */
|
|
|
|
/*P I_89 PI_RDLAT_ADJ_F1:RW:24:8 */
|
|
|
|
tmp = get_pi_rdlat_adj(pdram_timing);
|
|
|
|
tmp = get_pi_rdlat_adj(pdram_timing);
|
|
|
|
mmio_clrsetbits_32(PI_REG(i, 89), 0xff << 24, tmp << 24);
|
|
|
|
mmio_clrsetbits_32(PI_REG(i, 89), 0xffu << 24, tmp << 24);
|
|
|
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/* PI_90 PI_WRLAT_ADJ_F1:RW:24:8 */
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/* PI_90 PI_WRLAT_ADJ_F1:RW:24:8 */
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tmp = get_pi_wrlat_adj(pdram_timing, timing_config);
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tmp = get_pi_wrlat_adj(pdram_timing, timing_config);
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mmio_clrsetbits_32(PI_REG(i, 90), 0xff << 24, tmp << 24);
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mmio_clrsetbits_32(PI_REG(i, 90), 0xffu << 24, tmp << 24);
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/* PI_91 PI_TDFI_WRCSLAT_F1:RW:24:8 */
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/* PI_91 PI_TDFI_WRCSLAT_F1:RW:24:8 */
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tmp1 = tmp;
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tmp1 = tmp;
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if (tmp1 == 0)
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if (tmp1 == 0)
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@ -1290,7 +1290,7 @@ static void gen_rk3399_pi_params_f1(struct timing_related_config *timing_config,
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tmp = tmp1 - 1;
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tmp = tmp1 - 1;
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else
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else
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tmp = tmp1 - 5;
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tmp = tmp1 - 5;
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mmio_clrsetbits_32(PI_REG(i, 91), 0xff << 24, tmp << 24);
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mmio_clrsetbits_32(PI_REG(i, 91), 0xffu << 24, tmp << 24);
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/*PI_96 PI_TDFI_CALVL_CAPTURE_F1:RW:16:10 */
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/*PI_96 PI_TDFI_CALVL_CAPTURE_F1:RW:16:10 */
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/* tadr=20ns */
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/* tadr=20ns */
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tmp1 = 20000 / (1000000 / pdram_timing->mhz) + 1;
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tmp1 = 20000 / (1000000 / pdram_timing->mhz) + 1;
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@ -1333,12 +1333,12 @@ static void gen_rk3399_pi_params_f1(struct timing_related_config *timing_config,
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mmio_clrsetbits_32(PI_REG(i, 150), 0xffff << 8,
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mmio_clrsetbits_32(PI_REG(i, 150), 0xffff << 8,
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pdram_timing->mr[1] << 8);
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pdram_timing->mr[1] << 8);
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/* PI_128 PI_MR2_DATA_F1_0:RW+:16:16 */
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/* PI_128 PI_MR2_DATA_F1_0:RW+:16:16 */
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mmio_clrsetbits_32(PI_REG(i, 128), 0xffff << 16,
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mmio_clrsetbits_32(PI_REG(i, 128), 0xffffu << 16,
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pdram_timing->mr[2] << 16);
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pdram_timing->mr[2] << 16);
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/* PI_136 PI_MR2_DATA_F1_1:RW+:0:16 */
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/* PI_136 PI_MR2_DATA_F1_1:RW+:0:16 */
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mmio_clrsetbits_32(PI_REG(i, 136), 0xffff, pdram_timing->mr[2]);
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mmio_clrsetbits_32(PI_REG(i, 136), 0xffff, pdram_timing->mr[2]);
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/* PI_143 PI_MR2_DATA_F1_2:RW+:16:16 */
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/* PI_143 PI_MR2_DATA_F1_2:RW+:16:16 */
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mmio_clrsetbits_32(PI_REG(i, 143), 0xffff << 16,
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mmio_clrsetbits_32(PI_REG(i, 143), 0xffffu << 16,
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pdram_timing->mr[2] << 16);
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pdram_timing->mr[2] << 16);
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/* PI_151 PI_MR2_DATA_F1_3:RW+:0:16 */
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/* PI_151 PI_MR2_DATA_F1_3:RW+:0:16 */
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mmio_clrsetbits_32(PI_REG(i, 151), 0xffff, pdram_timing->mr[2]);
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mmio_clrsetbits_32(PI_REG(i, 151), 0xffff, pdram_timing->mr[2]);
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@ -1351,7 +1351,7 @@ static void gen_rk3399_pi_params_f1(struct timing_related_config *timing_config,
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/* PI_162 PI_TWTR_F1:RW:0:6 */
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/* PI_162 PI_TWTR_F1:RW:0:6 */
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mmio_clrsetbits_32(PI_REG(i, 162), 0x3f, pdram_timing->twtr);
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mmio_clrsetbits_32(PI_REG(i, 162), 0x3f, pdram_timing->twtr);
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/* PI_161 PI_TRCD_F1:RW:24:8 */
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/* PI_161 PI_TRCD_F1:RW:24:8 */
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mmio_clrsetbits_32(PI_REG(i, 161), 0xff << 24,
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mmio_clrsetbits_32(PI_REG(i, 161), 0xffu << 24,
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pdram_timing->trcd << 24);
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pdram_timing->trcd << 24);
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/* PI_161 PI_TRP_F1:RW:16:8 */
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/* PI_161 PI_TRP_F1:RW:16:8 */
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mmio_clrsetbits_32(PI_REG(i, 161), 0xff << 16,
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mmio_clrsetbits_32(PI_REG(i, 161), 0xff << 16,
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@ -1360,7 +1360,7 @@ static void gen_rk3399_pi_params_f1(struct timing_related_config *timing_config,
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mmio_clrsetbits_32(PI_REG(i, 161), 0xff << 8,
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mmio_clrsetbits_32(PI_REG(i, 161), 0xff << 8,
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pdram_timing->trtp << 8);
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pdram_timing->trtp << 8);
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/* PI_163 PI_TRAS_MIN_F1:RW:24:8 */
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/* PI_163 PI_TRAS_MIN_F1:RW:24:8 */
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mmio_clrsetbits_32(PI_REG(i, 163), 0xff << 24,
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mmio_clrsetbits_32(PI_REG(i, 163), 0xffu << 24,
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pdram_timing->tras_min << 24);
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pdram_timing->tras_min << 24);
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/* PI_163 PI_TRAS_MAX_F1:RW:0:17 */
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/* PI_163 PI_TRAS_MAX_F1:RW:0:17 */
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mmio_clrsetbits_32(PI_REG(i, 163), 0x1ffff,
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mmio_clrsetbits_32(PI_REG(i, 163), 0x1ffff,
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|
@ -1765,7 +1765,7 @@ uint32_t exit_low_power(void)
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0x40) {
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0x40) {
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|
|
while (mmio_read_32(CTL_REG(i, 200)) & 0x1)
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|
|
while (mmio_read_32(CTL_REG(i, 200)) & 0x1)
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|
;
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|
;
|
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mmio_clrsetbits_32(CTL_REG(i, 93), 0xff << 24,
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|
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|
mmio_clrsetbits_32(CTL_REG(i, 93), 0xffu << 24,
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|
|
0x69 << 24);
|
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|
0x69 << 24);
|
|
|
|
while (((mmio_read_32(CTL_REG(i, 100)) >> 24) & 0x7f) !=
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|
|
|
while (((mmio_read_32(CTL_REG(i, 100)) >> 24) & 0x7f) !=
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|
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|
0x40)
|
|
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|
0x40)
|
|
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|