Tegra: topology: fix MISRA defects for Rule 4.6
This patch uses int32_t to replace ints, to fix Rule 4.6 of the MISRA standard. Change-Id: I20ac6185929eced684b43da3ef1f8cd5fbddc83d Signed-off-by: Anthony Zhou <anzhou@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
This commit is contained in:
parent
82e73ae703
commit
7aba390fd0
|
@ -18,15 +18,15 @@
|
||||||
* to convert an MPIDR to a unique linear index. An error code (-1) is returned
|
* to convert an MPIDR to a unique linear index. An error code (-1) is returned
|
||||||
* in case the MPIDR is invalid.
|
* in case the MPIDR is invalid.
|
||||||
******************************************************************************/
|
******************************************************************************/
|
||||||
int plat_core_pos_by_mpidr(u_register_t mpidr)
|
int32_t plat_core_pos_by_mpidr(u_register_t mpidr)
|
||||||
{
|
{
|
||||||
u_register_t cluster_id, cpu_id;
|
u_register_t cluster_id, cpu_id;
|
||||||
int result;
|
int32_t result;
|
||||||
|
|
||||||
cluster_id = (mpidr >> (u_register_t)MPIDR_AFF1_SHIFT) & (u_register_t)MPIDR_AFFLVL_MASK;
|
cluster_id = (mpidr >> (u_register_t)MPIDR_AFF1_SHIFT) & (u_register_t)MPIDR_AFFLVL_MASK;
|
||||||
cpu_id = (mpidr >> (u_register_t)MPIDR_AFF0_SHIFT) & (u_register_t)MPIDR_AFFLVL_MASK;
|
cpu_id = (mpidr >> (u_register_t)MPIDR_AFF0_SHIFT) & (u_register_t)MPIDR_AFFLVL_MASK;
|
||||||
|
|
||||||
result = (int)cpu_id + ((int)cluster_id * 4);
|
result = (int32_t)cpu_id + ((int32_t)cluster_id * 4);
|
||||||
|
|
||||||
if (cluster_id >= (u_register_t)PLATFORM_CLUSTER_COUNT) {
|
if (cluster_id >= (u_register_t)PLATFORM_CLUSTER_COUNT) {
|
||||||
result = PSCI_E_NOT_PRESENT;
|
result = PSCI_E_NOT_PRESENT;
|
||||||
|
|
Loading…
Reference in New Issue