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uniphier: make all BL images completely position-independent 

This platform supports multiple SoCs. The next SoC will still keep
quite similar architecture, but the memory base will be changed.

The ENABLE_PIE improves the maintainability and usability. You can reuse
a single set of BL images for other SoC/board without re-compiling TF-A
at all. This will also keep the code cleaner because it avoids #ifdef
around various base addresses.

By defining ENABLE_PIE, BL2_AT_EL3, BL31, and BL32 (TSP) are really
position-independent now. You can load them anywhere irrespective of
their link address.

Change-Id: I8d5e3124ee30012f5b3bfa278b0baff8efd2fff7
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
This commit is contained in:
Masahiro Yamada 2020-01-17 13:46:48 +09:00
parent c64873ab94
commit 7af2131787
6 changed files with 77 additions and 35 deletions
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34
plat/socionext/uniphier/include/platform_def.h
View File

@ -28,16 +28,36 @@
#define PLAT_MAX_OFF_STATE U(2)
#define PLAT_MAX_RET_STATE U(1)
#define BL2_BASE ULL(0x80000000)
#define BL2_LIMIT ULL(0x80080000)
#define UNIPHIER_BL2_OFFSET UL(0x00000000)
#define UNIPHIER_BL2_MAX_SIZE UL(0x00080000)
/* 0x80080000-0x81000000: reserved for DSP */
/* 0x00080000-0x01000000: reserved for DSP */
#define BL31_BASE ULL(0x81000000)
#define BL31_LIMIT ULL(0x81080000)
#define UNIPHIER_BL31_OFFSET UL(0x01000000)
#define UNIPHIER_BL31_MAX_SIZE UL(0x00080000)
#define BL32_BASE ULL(0x81080000)
#define BL32_LIMIT ULL(0x81180000)
#define UNIPHIER_BL32_OFFSET UL(0x01080000)
#define UNIPHIER_BL32_MAX_SIZE UL(0x00100000)
/*
* The link addresses are determined by UNIPHIER_MEM_BASE + offset.
* When ENABLE_PIE is set, all the TF images can be loaded anywhere, so
* UNIPHIER_MEM_BASE is arbitrary.
*
* When ENABLE_PIE is unset, UNIPHIER_MEM_BASE should be chosen so that
* BL2_BASE matches to the physical address where BL2 is loaded, that is,
* UNIPHIER_MEM_BASE should be the base address of the DRAM region.
*/
#define UNIPHIER_MEM_BASE UL(0x00000000)
#define BL2_BASE (UNIPHIER_MEM_BASE + UNIPHIER_BL2_OFFSET)
#define BL2_LIMIT (BL2_BASE + UNIPHIER_BL2_MAX_SIZE)
#define BL31_BASE (UNIPHIER_MEM_BASE + UNIPHIER_BL31_OFFSET)
#define BL31_LIMIT (BL31_BASE + UNIPHIER_BL31_MAX_SIZE)
#define BL32_BASE (UNIPHIER_MEM_BASE + UNIPHIER_BL32_OFFSET)
#define BL32_LIMIT (BL32_BASE + UNIPHIER_BL32_MAX_SIZE)
#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32)
#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32)

3
plat/socionext/uniphier/platform.mk
View File

@ -9,6 +9,9 @@ override COLD_BOOT_SINGLE_CPU := 1
override PROGRAMMABLE_RESET_ADDRESS := 1
override USE_COHERENT_MEM := 1
override ENABLE_SVE_FOR_NS := 0
# Disabling ENABLE_PIE saves memory footprint a lot, but you need to adjust
# UNIPHIER_MEM_BASE so that all TF images are loaded at their link addresses.
override ENABLE_PIE := 1
# Cortex-A53 revision r0p4-51rel0

10
plat/socionext/uniphier/uniphier.h
View File

@ -42,8 +42,9 @@ int uniphier_nand_init(struct io_block_dev_spec **block_dev_spec);
int uniphier_usb_init(unsigned int soc,
struct io_block_dev_spec **block_dev_spec);
int uniphier_io_setup(unsigned int soc);
int uniphier_io_setup(unsigned int soc, uintptr_t mem_base);
void uniphier_init_image_descs(uintptr_t mem_base);
struct image_info;
struct image_info *uniphier_get_image_info(unsigned int image_id);
@ -67,11 +68,4 @@ void uniphier_gic_pcpu_init(void);
unsigned int uniphier_calc_core_pos(u_register_t mpidr);
#define UNIPHIER_BL33_BASE 0x84000000
#define UNIPHIER_BL33_MAX_SIZE 0x00100000
#define UNIPHIER_SCP_BASE ((UNIPHIER_BL33_BASE) + \
(UNIPHIER_BL33_MAX_SIZE))
#define UNIPHIER_SCP_MAX_SIZE 0x00020000
#endif /* UNIPHIER_H */

18
plat/socionext/uniphier/uniphier_bl2_setup.c
View File

@ -21,9 +21,10 @@
#include "uniphier.h"
#define UNIPHIER_IMAGE_BUF_BASE 0x84300000UL
#define UNIPHIER_IMAGE_BUF_OFFSET 0x04300000UL
#define UNIPHIER_IMAGE_BUF_SIZE 0x00100000UL
static uintptr_t uniphier_mem_base = UNIPHIER_MEM_BASE;
static int uniphier_bl2_kick_scp;
void bl2_el3_early_platform_setup(u_register_t x0, u_register_t x1,
@ -41,13 +42,16 @@ void bl2_el3_plat_arch_setup(void)
uniphier_mmap_setup();
enable_mmu_el3(0);
/* add relocation offset (run-time-address - link-address) */
uniphier_mem_base += BL_CODE_BASE - BL2_BASE;
soc = uniphier_get_soc_id();
if (soc == UNIPHIER_SOC_UNKNOWN) {
ERROR("unsupported SoC\n");
plat_error_handler(-ENOTSUP);
}
ret = uniphier_io_setup(soc);
ret = uniphier_io_setup(soc, uniphier_mem_base);
if (ret) {
ERROR("failed to setup io devices\n");
plat_error_handler(ret);
@ -110,19 +114,19 @@ bl_params_t *plat_get_next_bl_params(void)
void bl2_plat_preload_setup(void)
{
#ifdef UNIPHIER_DECOMPRESS_GZIP
uintptr_t buf_base = uniphier_mem_base + UNIPHIER_IMAGE_BUF_OFFSET;
int ret;
ret = mmap_add_dynamic_region(UNIPHIER_IMAGE_BUF_BASE,
UNIPHIER_IMAGE_BUF_BASE,
ret = mmap_add_dynamic_region(buf_base, buf_base,
UNIPHIER_IMAGE_BUF_SIZE,
MT_MEMORY | MT_RW | MT_NS);
if (ret)
plat_error_handler(ret);
image_decompress_init(UNIPHIER_IMAGE_BUF_BASE,
UNIPHIER_IMAGE_BUF_SIZE,
gunzip);
image_decompress_init(buf_base, UNIPHIER_IMAGE_BUF_SIZE, gunzip);
#endif
uniphier_init_image_descs(uniphier_mem_base);
}
int bl2_plat_handle_pre_image_load(unsigned int image_id)

41
plat/socionext/uniphier/uniphier_image_desc.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -13,13 +13,19 @@
#include "uniphier.h"
#define UNIPHIER_BL33_OFFSET 0x04000000UL
#define UNIPHIER_BL33_MAX_SIZE 0x00100000UL
#define UNIPHIER_SCP_OFFSET 0x04100000UL
#define UNIPHIER_SCP_MAX_SIZE 0x00020000UL
static struct bl_mem_params_node uniphier_image_descs[] = {
{
.image_id = SCP_BL2_IMAGE_ID,
SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
VERSION_2, image_info_t, 0),
.image_info.image_base = UNIPHIER_SCP_BASE,
.image_info.image_base = UNIPHIER_SCP_OFFSET,
.image_info.image_max_size = UNIPHIER_SCP_MAX_SIZE,
SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
@ -33,13 +39,13 @@ static struct bl_mem_params_node uniphier_image_descs[] = {
SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
VERSION_2, image_info_t, 0),
.image_info.image_base = BL31_BASE,
.image_info.image_max_size = BL31_LIMIT - BL31_BASE,
.image_info.image_base = UNIPHIER_BL31_OFFSET,
.image_info.image_max_size = UNIPHIER_BL31_MAX_SIZE,
SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
VERSION_2, entry_point_info_t,
SECURE | EXECUTABLE | EP_FIRST_EXE),
.ep_info.pc = BL31_BASE,
.ep_info.pc = UNIPHIER_BL31_OFFSET,
.ep_info.spsr = SPSR_64(MODE_EL3, MODE_SP_ELX,
DISABLE_ALL_EXCEPTIONS),
@ -55,13 +61,13 @@ static struct bl_mem_params_node uniphier_image_descs[] = {
SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
VERSION_2, image_info_t, 0),
.image_info.image_base = BL32_BASE,
.image_info.image_max_size = BL32_LIMIT - BL32_BASE,
.image_info.image_base = UNIPHIER_BL32_OFFSET,
.image_info.image_max_size = UNIPHIER_BL32_MAX_SIZE,
SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
VERSION_2, entry_point_info_t,
SECURE | EXECUTABLE),
.ep_info.pc = BL32_BASE,
.ep_info.pc = UNIPHIER_BL32_OFFSET,
.ep_info.spsr = SPSR_64(MODE_EL3, MODE_SP_ELX,
DISABLE_ALL_EXCEPTIONS),
@ -73,13 +79,13 @@ static struct bl_mem_params_node uniphier_image_descs[] = {
SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
VERSION_2, image_info_t, 0),
.image_info.image_base = UNIPHIER_BL33_BASE,
.image_info.image_base = UNIPHIER_BL33_OFFSET,
.image_info.image_max_size = UNIPHIER_BL33_MAX_SIZE,
SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
VERSION_2, entry_point_info_t,
NON_SECURE | EXECUTABLE),
.ep_info.pc = UNIPHIER_BL33_BASE,
.ep_info.pc = UNIPHIER_BL33_OFFSET,
.ep_info.spsr = SPSR_64(MODE_EL2, MODE_SP_ELX,
DISABLE_ALL_EXCEPTIONS),
@ -88,6 +94,21 @@ static struct bl_mem_params_node uniphier_image_descs[] = {
};
REGISTER_BL_IMAGE_DESCS(uniphier_image_descs)
/*
* image_info.image_base and ep_info.pc are the offset from the memory base.
* When ENABLE_PIE is set, we never know the real memory base at link-time.
* Fix-up the addresses by adding the run-time detected base.
*/
void uniphier_init_image_descs(uintptr_t mem_base)
{
int i;
for (i = 0; i < ARRAY_SIZE(uniphier_image_descs); i++) {
uniphier_image_descs[i].image_info.image_base += mem_base;
uniphier_image_descs[i].ep_info.pc += mem_base;
}
}
struct image_info *uniphier_get_image_info(unsigned int image_id)
{
struct bl_mem_params_node *desc;

6
plat/socionext/uniphier/uniphier_io_storage.c
View File

@ -26,7 +26,7 @@
#define UNIPHIER_OCM_REGION_BASE 0x30000000ULL
#define UNIPHIER_OCM_REGION_SIZE 0x00040000ULL
#define UNIPHIER_BLOCK_BUF_BASE 0x84200000UL
#define UNIPHIER_BLOCK_BUF_OFFSET 0x04200000UL
#define UNIPHIER_BLOCK_BUF_SIZE 0x00100000UL
static const io_dev_connector_t *uniphier_fip_dev_con;
@ -317,7 +317,7 @@ static int (* const uniphier_io_setup_table[])(unsigned int, size_t) = {
[UNIPHIER_BOOT_DEVICE_USB] = uniphier_io_usb_setup,
};
int uniphier_io_setup(unsigned int soc_id)
int uniphier_io_setup(unsigned int soc_id, uintptr_t mem_base)
{
int (*io_setup)(unsigned int soc_id, size_t buffer_offset);
unsigned int boot_dev;
@ -328,7 +328,7 @@ int uniphier_io_setup(unsigned int soc_id)
return -EINVAL;
io_setup = uniphier_io_setup_table[boot_dev];
ret = io_setup(soc_id, UNIPHIER_BLOCK_BUF_BASE);
ret = io_setup(soc_id, mem_base + UNIPHIER_BLOCK_BUF_OFFSET);
if (ret)
return ret;