TF-A: Add support for Measured Boot driver
This patch adds support for Measured Boot driver functionality in common Arm platform code. Change-Id: If049dcf8d847c39023b77c0d805a8cf5b8bcaa3e Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
This commit is contained in:
Alexei Fedorov
parent
1f7307232f
commit
7b4e1fbb8f
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@ -23,6 +23,9 @@ struct tbbr_dyn_config_t {
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uint32_t disable_auth;
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void *mbedtls_heap_addr;
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size_t mbedtls_heap_size;
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#if MEASURED_BOOT
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uint8_t bl2_hash_data[TCG_DIGEST_SIZE];
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#endif
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};
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extern struct tbbr_dyn_config_t tbbr_dyn_config;
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@ -81,7 +81,7 @@
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ARM_SCP_TZC_DRAM1_SIZE)
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#define ARM_SCP_TZC_DRAM1_SIZE PLAT_ARM_SCP_TZC_DRAM1_SIZE
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#define ARM_SCP_TZC_DRAM1_END (ARM_SCP_TZC_DRAM1_BASE + \
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ARM_SCP_TZC_DRAM1_SIZE - 1)
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ARM_SCP_TZC_DRAM1_SIZE - 1U)
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/*
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* Define a 2MB region within the TZC secured DRAM for use by EL3 runtime
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@ -92,7 +92,7 @@
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#define ARM_EL3_TZC_DRAM1_BASE (ARM_SCP_TZC_DRAM1_BASE - ARM_EL3_TZC_DRAM1_SIZE)
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#define ARM_EL3_TZC_DRAM1_SIZE UL(0x00200000) /* 2 MB */
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#define ARM_EL3_TZC_DRAM1_END (ARM_EL3_TZC_DRAM1_BASE + \
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ARM_EL3_TZC_DRAM1_SIZE - 1)
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ARM_EL3_TZC_DRAM1_SIZE - 1U)
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#define ARM_AP_TZC_DRAM1_BASE (ARM_DRAM1_BASE + \
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ARM_DRAM1_SIZE - \
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@ -101,7 +101,7 @@
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(ARM_SCP_TZC_DRAM1_SIZE + \
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ARM_EL3_TZC_DRAM1_SIZE))
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#define ARM_AP_TZC_DRAM1_END (ARM_AP_TZC_DRAM1_BASE + \
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ARM_AP_TZC_DRAM1_SIZE - 1)
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ARM_AP_TZC_DRAM1_SIZE - 1U)
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/* Define the Access permissions for Secure peripherals to NS_DRAM */
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#if ARM_CRYPTOCELL_INTEG
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@ -148,17 +148,17 @@
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#define ARM_NS_DRAM1_SIZE (ARM_DRAM1_SIZE - \
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ARM_TZC_DRAM1_SIZE)
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#define ARM_NS_DRAM1_END (ARM_NS_DRAM1_BASE + \
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ARM_NS_DRAM1_SIZE - 1)
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ARM_NS_DRAM1_SIZE - 1U)
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#define ARM_DRAM1_BASE ULL(0x80000000)
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#define ARM_DRAM1_SIZE ULL(0x80000000)
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#define ARM_DRAM1_END (ARM_DRAM1_BASE + \
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ARM_DRAM1_SIZE - 1)
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ARM_DRAM1_SIZE - 1U)
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#define ARM_DRAM2_BASE PLAT_ARM_DRAM2_BASE
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#define ARM_DRAM2_SIZE PLAT_ARM_DRAM2_SIZE
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#define ARM_DRAM2_END (ARM_DRAM2_BASE + \
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ARM_DRAM2_SIZE - 1)
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ARM_DRAM2_SIZE - 1U)
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#define ARM_IRQ_SEC_PHY_TIMER 29
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@ -235,8 +235,20 @@ int arm_get_mbedtls_heap(void **heap_addr, size_t *heap_size);
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#if MEASURED_BOOT
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/* Measured boot related functions */
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void arm_bl1_set_bl2_hash(image_desc_t *image_desc);
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void arm_bl1_set_bl2_hash(const image_desc_t *image_desc);
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void arm_bl2_get_hash(void *data);
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int arm_set_tos_fw_info(uintptr_t config_base, uintptr_t log_addr,
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size_t log_size);
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int arm_set_nt_fw_info(uintptr_t config_base,
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/*
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* Currently OP-TEE does not support reading DTBs from Secure memory
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* and this option should be removed when feature is supported.
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*/
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#ifdef SPD_opteed
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uintptr_t log_addr,
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#endif
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size_t log_size, uintptr_t *ns_log_addr);
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#endif /* MEASURED_BOOT */
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/*
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* Free the memory storing initialization code only used during an images boot
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@ -175,6 +175,14 @@ __dead2 void bl1_plat_fwu_done(void *client_cookie, void *reserved);
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int bl1_plat_handle_pre_image_load(unsigned int image_id);
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int bl1_plat_handle_post_image_load(unsigned int image_id);
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#if MEASURED_BOOT
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/*
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* Calculates and writes BL2 hash data to the platform's defined location.
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* For ARM platforms the data are written to TB_FW_CONFIG DTB.
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*/
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void bl1_plat_set_bl2_hash(const image_desc_t *image_desc);
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#endif
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/*******************************************************************************
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* Mandatory BL2 functions
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******************************************************************************/
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@ -190,11 +198,13 @@ struct meminfo *bl2_plat_sec_mem_layout(void);
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int bl2_plat_handle_pre_image_load(unsigned int image_id);
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int bl2_plat_handle_post_image_load(unsigned int image_id);
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/*******************************************************************************
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* Optional BL2 functions (may be overridden)
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******************************************************************************/
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#if MEASURED_BOOT
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/* Read TCG_DIGEST_SIZE bytes of BL2 hash data */
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void bl2_plat_get_hash(void *data);
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#endif
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/*******************************************************************************
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* Mandatory BL2 at EL3 functions: Must be implemented if BL2_AT_EL3 image is
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@ -204,7 +214,6 @@ void bl2_el3_early_platform_setup(u_register_t arg0, u_register_t arg1,
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u_register_t arg2, u_register_t arg3);
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void bl2_el3_plat_arch_setup(void);
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/*******************************************************************************
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* Optional BL2 at EL3 functions (may be overridden)
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******************************************************************************/
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@ -37,6 +37,9 @@ CASSERT(BL2_BASE >= ARM_FW_CONFIG_LIMIT, assert_bl2_base_overflows);
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#pragma weak bl2_platform_setup
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#pragma weak bl2_plat_arch_setup
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#pragma weak bl2_plat_sec_mem_layout
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#if MEASURED_BOOT
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#pragma weak bl2_plat_get_hash
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#endif
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#define MAP_BL2_TOTAL MAP_REGION_FLAT( \
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bl2_tzram_layout.total_base, \
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@ -225,3 +228,11 @@ int bl2_plat_handle_post_image_load(unsigned int image_id)
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{
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return arm_bl2_plat_handle_post_image_load(image_id);
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}
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#if MEASURED_BOOT
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/* Read TCG_DIGEST_SIZE bytes of BL2 hash data */
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void bl2_plat_get_hash(void *data)
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{
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arm_bl2_get_hash(data);
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}
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#endif
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@ -23,6 +23,7 @@
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#include <lib/fconf/fconf.h>
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#include <lib/fconf/fconf_dyn_cfg_getter.h>
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#include <lib/fconf/fconf_tbbr_getter.h>
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#include <plat/arm/common/arm_dyn_cfg_helpers.h>
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#include <plat/arm/common/plat_arm.h>
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@ -98,13 +99,14 @@ void arm_bl1_set_mbedtls_heap(void)
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tb_fw_cfg_dtb = tb_fw_config_info->config_addr;
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if ((tb_fw_cfg_dtb != 0UL) && (mbedtls_heap_addr != NULL)) {
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/* As libfdt use void *, we can't avoid this cast */
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/* As libfdt uses void *, we can't avoid this cast */
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void *dtb = (void *)tb_fw_cfg_dtb;
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err = arm_set_dtb_mbedtls_heap_info(dtb,
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mbedtls_heap_addr, mbedtls_heap_size);
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if (err < 0) {
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ERROR("BL1: unable to write shared Mbed TLS heap information to DTB\n");
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ERROR("%swrite shared Mbed TLS heap information%s",
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"BL1: unable to ", " to DTB\n");
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panic();
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}
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#if !MEASURED_BOOT
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@ -124,13 +126,13 @@ void arm_bl1_set_mbedtls_heap(void)
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#if MEASURED_BOOT
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/*
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* Puts the BL2 hash data to TB_FW_CONFIG DTB.
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* Calculates and writes BL2 hash data to TB_FW_CONFIG DTB.
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* Executed only from BL1.
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*/
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void arm_bl1_set_bl2_hash(image_desc_t *image_desc)
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void arm_bl1_set_bl2_hash(const image_desc_t *image_desc)
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{
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unsigned char hash_data[MBEDTLS_MD_MAX_SIZE];
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image_info_t image_info = image_desc->image_info;
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const image_info_t image_info = image_desc->image_info;
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uintptr_t tb_fw_cfg_dtb;
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int err;
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const struct dyn_cfg_dtb_info_t *tb_fw_config_info;
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@ -154,13 +156,15 @@ void arm_bl1_set_bl2_hash(image_desc_t *image_desc)
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(void *)image_info.image_base,
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image_info.image_size, hash_data);
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if (err != 0) {
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ERROR("BL1: unable to calculate BL2 hash\n");
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ERROR("%scalculate%s\n", "BL1: unable to ",
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" BL2 hash");
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panic();
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}
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err = arm_set_bl2_hash_info((void *)tb_fw_cfg_dtb, hash_data);
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if (err < 0) {
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ERROR("BL1: unable to write BL2 hash data to DTB\n");
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ERROR("%swrite%sdata%s\n", "BL1: unable to ",
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" BL2 hash ", "to DTB\n");
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panic();
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}
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@ -171,6 +175,21 @@ void arm_bl1_set_bl2_hash(image_desc_t *image_desc)
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*/
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flush_dcache_range(tb_fw_cfg_dtb, fdt_totalsize((void *)tb_fw_cfg_dtb));
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}
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/*
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* Reads TCG_DIGEST_SIZE bytes of BL2 hash data from the DTB.
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* Executed only from BL2.
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*/
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void arm_bl2_get_hash(void *data)
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{
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const void *bl2_hash;
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assert(data != NULL);
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/* Retrieve TCG_DIGEST_SIZE bytes of BL2 hash data from the DTB */
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bl2_hash = FCONF_GET_PROPERTY(tbbr, dyn_config, bl2_hash_data);
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(void)memcpy(data, bl2_hash, TCG_DIGEST_SIZE);
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}
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#endif /* MEASURED_BOOT */
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#endif /* TRUSTED_BOARD_BOOT */
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@ -202,14 +221,15 @@ void arm_bl2_dyn_cfg_init(void)
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/* Get the config load address and size from TB_FW_CONFIG */
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cfg_mem_params = get_bl_mem_params_node(config_ids[i]);
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if (cfg_mem_params == NULL) {
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VERBOSE("Couldn't find HW_CONFIG in bl_mem_params_node\n");
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VERBOSE("%sHW_CONFIG in bl_mem_params_node\n",
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"Couldn't find ");
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continue;
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}
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dtb_info = FCONF_GET_PROPERTY(dyn_cfg, dtb, config_ids[i]);
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if (dtb_info == NULL) {
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VERBOSE("Couldn't find config_id %d load info in TB_FW_CONFIG\n",
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config_ids[i]);
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VERBOSE("%sconfig_id %d load info in TB_FW_CONFIG\n",
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"Couldn't find ", config_ids[i]);
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continue;
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}
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@ -223,30 +243,32 @@ void arm_bl2_dyn_cfg_init(void)
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*/
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if (config_ids[i] != HW_CONFIG_ID) {
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if (check_uptr_overflow(image_base, image_size))
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if (check_uptr_overflow(image_base, image_size)) {
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continue;
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}
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#ifdef BL31_BASE
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/* Ensure the configs don't overlap with BL31 */
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if ((image_base >= BL31_BASE) &&
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(image_base <= BL31_LIMIT))
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(image_base <= BL31_LIMIT)) {
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continue;
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}
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#endif
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/* Ensure the configs are loaded in a valid address */
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if (image_base < ARM_BL_RAM_BASE)
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if (image_base < ARM_BL_RAM_BASE) {
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continue;
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}
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#ifdef BL32_BASE
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/*
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* If BL32 is present, ensure that the configs don't
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* overlap with it.
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*/
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if ((image_base >= BL32_BASE) &&
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(image_base <= BL32_LIMIT))
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(image_base <= BL32_LIMIT)) {
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continue;
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}
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#endif
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}
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cfg_mem_params->image_info.image_base = image_base;
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cfg_mem_params->image_info.image_max_size = (uint32_t)image_size;
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@ -6,9 +6,13 @@
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#include <assert.h>
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#if MEASURED_BOOT
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#include <common/desc_image_load.h>
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#endif
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#include <common/fdt_wrappers.h>
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#include <libfdt.h>
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#include <common/fdt_wrappers.h>
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#include <plat/arm/common/arm_dyn_cfg_helpers.h>
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#include <plat/arm/common/plat_arm.h>
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@ -17,6 +21,15 @@
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#if MEASURED_BOOT
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#define DTB_PROP_BL2_HASH_DATA "bl2_hash_data"
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#ifdef SPD_opteed
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/*
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* Currently OP-TEE does not support reading DTBs from Secure memory
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* and this property should be removed when this feature is supported.
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*/
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#define DTB_PROP_HW_SM_LOG_ADDR "tpm_event_log_sm_addr"
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#endif
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#define DTB_PROP_HW_LOG_ADDR "tpm_event_log_addr"
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#define DTB_PROP_HW_LOG_SIZE "tpm_event_log_size"
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static int dtb_root = -1;
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#endif /* MEASURED_BOOT */
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@ -37,18 +50,19 @@ int arm_dyn_tb_fw_cfg_init(void *dtb, int *node)
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/* Check if the pointer to DT is correct */
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if (fdt_check_header(dtb) != 0) {
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WARN("Invalid DTB file passed as TB_FW_CONFIG\n");
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WARN("Invalid DTB file passed as%s\n", " TB_FW_CONFIG");
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return -1;
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}
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/* Assert the node offset point to "arm,tb_fw" compatible property */
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*node = fdt_node_offset_by_compatible(dtb, -1, "arm,tb_fw");
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if (*node < 0) {
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WARN("The compatible property `arm,tb_fw` not found in the config\n");
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WARN("The compatible property '%s' not%s", "arm,tb_fw",
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" found in the config\n");
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return -1;
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}
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VERBOSE("Dyn cfg: Found \"arm,tb_fw\" in the config\n");
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VERBOSE("Dyn cfg: '%s'%s", "arm,tb_fw", " found in the config\n");
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return 0;
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}
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@ -76,7 +90,8 @@ int arm_set_dtb_mbedtls_heap_info(void *dtb, void *heap_addr, size_t heap_size)
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*/
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int err = arm_dyn_tb_fw_cfg_init(dtb, &dtb_root);
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if (err < 0) {
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ERROR("Invalid TB_FW_CONFIG loaded. Unable to get root node\n");
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ERROR("Invalid%s loaded. Unable to get root node\n",
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" TB_FW_CONFIG");
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return -1;
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}
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@ -90,16 +105,16 @@ int arm_set_dtb_mbedtls_heap_info(void *dtb, void *heap_addr, size_t heap_size)
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err = fdtw_write_inplace_cells(dtb, dtb_root,
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DTB_PROP_MBEDTLS_HEAP_ADDR, 2, &heap_addr);
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if (err < 0) {
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ERROR("Unable to write DTB property %s\n",
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DTB_PROP_MBEDTLS_HEAP_ADDR);
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ERROR("%sDTB property '%s'\n",
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"Unable to write ", DTB_PROP_MBEDTLS_HEAP_ADDR);
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return -1;
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}
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err = fdtw_write_inplace_cells(dtb, dtb_root,
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DTB_PROP_MBEDTLS_HEAP_SIZE, 1, &heap_size);
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if (err < 0) {
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ERROR("Unable to write DTB property %s\n",
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DTB_PROP_MBEDTLS_HEAP_SIZE);
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ERROR("%sDTB property '%s'\n",
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"Unable to write ", DTB_PROP_MBEDTLS_HEAP_SIZE);
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return -1;
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}
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@ -124,7 +139,165 @@ int arm_set_bl2_hash_info(void *dtb, void *data)
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/*
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* Write the BL2 hash data in the DTB.
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*/
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return fdtw_write_inplace_bytes(dtb, dtb_root, DTB_PROP_BL2_HASH_DATA,
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return fdtw_write_inplace_bytes(dtb, dtb_root,
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DTB_PROP_BL2_HASH_DATA,
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TCG_DIGEST_SIZE, data);
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}
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/*
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* Write the Event Log address and its size in the DTB.
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*
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* This function is supposed to be called only by BL2.
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*
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* Returns:
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* 0 = success
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* < 0 = error
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*/
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static int arm_set_event_log_info(uintptr_t config_base,
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#ifdef SPD_opteed
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uintptr_t sm_log_addr,
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#endif
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uintptr_t log_addr, size_t log_size)
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{
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/* As libfdt uses void *, we can't avoid this cast */
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void *dtb = (void *)config_base;
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const char *compatible = "arm,tpm_event_log";
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int err, node;
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/*
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||||
* Verify that the DTB is valid, before attempting to write to it,
|
||||
* and get the DTB root node.
|
||||
*/
|
||||
|
||||
/* Check if the pointer to DT is correct */
|
||||
err = fdt_check_header(dtb);
|
||||
if (err < 0) {
|
||||
WARN("Invalid DTB file passed\n");
|
||||
return err;
|
||||
}
|
||||
|
||||
/* Assert the node offset point to compatible property */
|
||||
node = fdt_node_offset_by_compatible(dtb, -1, compatible);
|
||||
if (node < 0) {
|
||||
WARN("The compatible property '%s' not%s", compatible,
|
||||
" found in the config\n");
|
||||
return node;
|
||||
}
|
||||
|
||||
VERBOSE("Dyn cfg: '%s'%s", compatible, " found in the config\n");
|
||||
|
||||
#ifdef SPD_opteed
|
||||
if (sm_log_addr != 0UL) {
|
||||
err = fdtw_write_inplace_cells(dtb, node,
|
||||
DTB_PROP_HW_SM_LOG_ADDR, 2, &sm_log_addr);
|
||||
if (err < 0) {
|
||||
ERROR("%sDTB property '%s'\n",
|
||||
"Unable to write ", DTB_PROP_HW_SM_LOG_ADDR);
|
||||
return err;
|
||||
}
|
||||
}
|
||||
#endif
|
||||
err = fdtw_write_inplace_cells(dtb, node,
|
||||
DTB_PROP_HW_LOG_ADDR, 2, &log_addr);
|
||||
if (err < 0) {
|
||||
ERROR("%sDTB property '%s'\n",
|
||||
"Unable to write ", DTB_PROP_HW_LOG_ADDR);
|
||||
return err;
|
||||
}
|
||||
|
||||
err = fdtw_write_inplace_cells(dtb, node,
|
||||
DTB_PROP_HW_LOG_SIZE, 1, &log_size);
|
||||
if (err < 0) {
|
||||
ERROR("%sDTB property '%s'\n",
|
||||
"Unable to write ", DTB_PROP_HW_LOG_SIZE);
|
||||
} else {
|
||||
/*
|
||||
* Ensure that the info written to the DTB is visible
|
||||
* to other images.
|
||||
*/
|
||||
flush_dcache_range(config_base, fdt_totalsize(dtb));
|
||||
}
|
||||
|
||||
return err;
|
||||
}
|
||||
|
||||
/*
|
||||
* This function writes the Event Log address and its size
|
||||
* in the TOS_FW_CONFIG DTB.
|
||||
*
|
||||
* This function is supposed to be called only by BL2.
|
||||
*
|
||||
* Returns:
|
||||
* 0 = success
|
||||
* < 0 = error
|
||||
*/
|
||||
int arm_set_tos_fw_info(uintptr_t config_base, uintptr_t log_addr,
|
||||
size_t log_size)
|
||||
{
|
||||
int err;
|
||||
|
||||
assert(config_base != 0UL);
|
||||
assert(log_addr != 0UL);
|
||||
|
||||
/* Write the Event Log address and its size in the DTB */
|
||||
err = arm_set_event_log_info(config_base,
|
||||
#ifdef SPD_opteed
|
||||
0UL,
|
||||
#endif
|
||||
log_addr, log_size);
|
||||
if (err < 0) {
|
||||
ERROR("%sEvent Log data to TOS_FW_CONFIG\n",
|
||||
"Unable to write ");
|
||||
}
|
||||
|
||||
return err;
|
||||
}
|
||||
|
||||
/*
|
||||
* This function writes the Event Log address and its size
|
||||
* in the NT_FW_CONFIG DTB.
|
||||
*
|
||||
* This function is supposed to be called only by BL2.
|
||||
*
|
||||
* Returns:
|
||||
* 0 = success
|
||||
* < 0 = error
|
||||
*/
|
||||
int arm_set_nt_fw_info(uintptr_t config_base,
|
||||
#ifdef SPD_opteed
|
||||
uintptr_t log_addr,
|
||||
#endif
|
||||
size_t log_size, uintptr_t *ns_log_addr)
|
||||
{
|
||||
uintptr_t ns_addr;
|
||||
const bl_mem_params_node_t *cfg_mem_params;
|
||||
int err;
|
||||
|
||||
assert(config_base != 0UL);
|
||||
assert(ns_log_addr != NULL);
|
||||
|
||||
/* Get the config load address and size from NT_FW_CONFIG */
|
||||
cfg_mem_params = get_bl_mem_params_node(NT_FW_CONFIG_ID);
|
||||
assert(cfg_mem_params != NULL);
|
||||
|
||||
/* Calculate Event Log address in Non-secure memory */
|
||||
ns_addr = cfg_mem_params->image_info.image_base +
|
||||
cfg_mem_params->image_info.image_max_size;
|
||||
|
||||
/* Check for memory space */
|
||||
if ((uint64_t)(ns_addr + log_size) > ARM_NS_DRAM1_END) {
|
||||
return -1;
|
||||
}
|
||||
|
||||
/* Write the Event Log address and its size in the DTB */
|
||||
err = arm_set_event_log_info(config_base,
|
||||
#ifdef SPD_opteed
|
||||
log_addr,
|
||||
#endif
|
||||
ns_addr, log_size);
|
||||
|
||||
/* Return Event Log address in Non-secure memory */
|
||||
*ns_log_addr = (err < 0) ? 0UL : ns_addr;
|
||||
return err;
|
||||
}
|
||||
#endif /* MEASURED_BOOT */
|
||||
|
|
|
|||
Loading…
Reference in New Issue