Merge changes from topic "fdt_wrappers_rework" into integration
* changes: arm_fpga: Read UART address from DT arm_fpga: Read GICD and GICR base addresses from DT arm_fpga: Read generic timer counter frequency from DT arm_fpga: Use Generic UART
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commit
7bf5832c3d
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@ -108,8 +108,6 @@ endfunc plat_fpga_calc_core_pos
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func plat_crash_console_init
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mov_imm x0, PLAT_FPGA_CRASH_UART_BASE
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mov_imm x1, PLAT_FPGA_CRASH_UART_CLK_IN_HZ
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mov_imm x2, PLAT_FPGA_CONSOLE_BAUDRATE
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b console_pl011_core_init
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endfunc plat_crash_console_init
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@ -5,8 +5,11 @@
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*/
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#include <assert.h>
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#include <lib/mmio.h>
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#include <common/fdt_wrappers.h>
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#include <drivers/generic_delay_timer.h>
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#include <lib/mmio.h>
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#include <libfdt.h>
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#include <plat/common/platform.h>
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#include <platform_def.h>
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@ -76,7 +79,16 @@ entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type)
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unsigned int plat_get_syscnt_freq2(void)
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{
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return FPGA_TIMER_FREQUENCY;
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const void *fdt = (void *)(uintptr_t)FPGA_PRELOADED_DTB_BASE;
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int node;
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node = fdt_node_offset_by_compatible(fdt, 0, "arm,armv8-timer");
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if (node < 0) {
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return FPGA_DEFAULT_TIMER_FREQUENCY;
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}
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return fdt_read_uint32_default(fdt, node, "clock-frequency",
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FPGA_DEFAULT_TIMER_FREQUENCY);
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}
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void bl31_plat_enable_mmu(uint32_t flags)
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@ -4,8 +4,12 @@
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <drivers/console.h>
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#include <stddef.h>
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#include <stdint.h>
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#include <common/fdt_wrappers.h>
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#include <drivers/arm/pl011.h>
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#include <drivers/console.h>
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#include <platform_def.h>
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@ -13,10 +17,21 @@ static console_t console;
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void fpga_console_init(void)
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{
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(void)console_pl011_register(PLAT_FPGA_BOOT_UART_BASE,
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PLAT_FPGA_BOOT_UART_CLK_IN_HZ,
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PLAT_FPGA_CONSOLE_BAUDRATE,
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&console);
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const void *fdt = (void *)(uintptr_t)FPGA_PRELOADED_DTB_BASE;
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uintptr_t base_addr = PLAT_FPGA_CRASH_UART_BASE;
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int node;
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/*
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* Try to read the UART base address from the DT, by chasing the
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* stdout-path property of the chosen node.
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* If this does not work, use the crash console address as a fallback.
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*/
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node = fdt_get_stdout_node_offset(fdt);
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if (node >= 0) {
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fdt_get_reg_props_by_index(fdt, node, 0, &base_addr, NULL);
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}
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(void)console_pl011_register(base_addr, 0, 0, &console);
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console_set_scope(&console, CONSOLE_FLAG_BOOT |
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CONSOLE_FLAG_RUNTIME);
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@ -23,18 +23,16 @@
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#define FPGA_MAX_PE_PER_CPU 4
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#define FPGA_PRIMARY_CPU 0x0
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/*******************************************************************************
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* FPGA image memory map related constants
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******************************************************************************/
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/* UART base address and clock frequency, as configured by the image */
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#define PLAT_FPGA_BOOT_UART_BASE 0x7ff80000
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#define PLAT_FPGA_BOOT_UART_CLK_IN_HZ 10000000
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/*
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* UART base address, just for the crash console, as a fallback.
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* The actual console UART address is taken from the DT.
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*/
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#define PLAT_FPGA_CRASH_UART_BASE 0x7ff80000
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#define PLAT_FPGA_CRASH_UART_BASE PLAT_FPGA_BOOT_UART_BASE
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#define PLAT_FPGA_CRASH_UART_CLK_IN_HZ PLAT_FPGA_BOOT_UART_CLK_IN_HZ
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#define FPGA_TIMER_FREQUENCY 10000000
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#define FPGA_DEFAULT_TIMER_FREQUENCY 10000000
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#endif
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@ -4,9 +4,13 @@
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <common/debug.h>
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#include <common/fdt_wrappers.h>
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#include <drivers/arm/gicv3.h>
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#include <drivers/arm/gic_common.h>
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#include <libfdt.h>
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#include <platform_def.h>
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#include <plat/common/platform.h>
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#include <platform_def.h>
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@ -22,9 +26,7 @@ static unsigned int fpga_mpidr_to_core_pos(unsigned long mpidr)
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return (unsigned int)plat_core_pos_by_mpidr(mpidr);
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}
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static const gicv3_driver_data_t fpga_gicv3_driver_data = {
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.gicd_base = GICD_BASE,
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.gicr_base = GICR_BASE,
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static gicv3_driver_data_t fpga_gicv3_driver_data = {
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.interrupt_props = fpga_interrupt_props,
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.interrupt_props_num = ARRAY_SIZE(fpga_interrupt_props),
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.rdistif_num = PLATFORM_CORE_COUNT,
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@ -34,6 +36,30 @@ static const gicv3_driver_data_t fpga_gicv3_driver_data = {
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void plat_fpga_gic_init(void)
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{
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const void *fdt = (void *)(uintptr_t)FPGA_PRELOADED_DTB_BASE;
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int node, ret;
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node = fdt_node_offset_by_compatible(fdt, 0, "arm,gic-v3");
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if (node < 0) {
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WARN("No \"arm,gic-v3\" compatible node found in DT, no GIC support.\n");
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return;
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}
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/* TODO: Assuming only empty "ranges;" properties up the bus path. */
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ret = fdt_get_reg_props_by_index(fdt, node, 0,
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&fpga_gicv3_driver_data.gicd_base, NULL);
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if (ret < 0) {
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WARN("Could not read GIC distributor address from DT.\n");
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return;
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}
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ret = fdt_get_reg_props_by_index(fdt, node, 1,
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&fpga_gicv3_driver_data.gicr_base, NULL);
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if (ret < 0) {
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WARN("Could not read GIC redistributor address from DT.\n");
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return;
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}
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gicv3_driver_init(&fpga_gicv3_driver_data);
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gicv3_distif_init();
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gicv3_rdistif_init(plat_my_core_pos());
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@ -35,9 +35,6 @@
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#define BL31_LIMIT UL(0x01000000)
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#endif
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#define GICD_BASE 0x30000000
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#define GICR_BASE 0x30040000
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#define PLAT_SDEI_NORMAL_PRI 0x70
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#define ARM_IRQ_SEC_PHY_TIMER 29
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@ -87,6 +84,4 @@
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#define PLAT_FPGA_HOLD_STATE_WAIT 0
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#define PLAT_FPGA_HOLD_STATE_GO 1
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#define PLAT_FPGA_CONSOLE_BAUDRATE 38400
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#endif
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@ -4,6 +4,8 @@
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# SPDX-License-Identifier: BSD-3-Clause
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#
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include lib/libfdt/libfdt.mk
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RESET_TO_BL31 := 1
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ifeq (${RESET_TO_BL31}, 0)
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$(error "This is a BL31-only port; RESET_TO_BL31 must be enabled")
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@ -38,6 +40,8 @@ USE_COHERENT_MEM := 0
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# This can be overridden depending on CPU(s) used in the FPGA image
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HW_ASSISTED_COHERENCY := 1
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PL011_GENERIC_UART := 1
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FPGA_CPU_LIBS := lib/cpus/${ARCH}/aem_generic.S
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# select a different set of CPU files, depending on whether we compile for
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@ -80,7 +84,8 @@ PLAT_INCLUDES := -Iplat/arm/board/arm_fpga/include
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PLAT_BL_COMMON_SOURCES := plat/arm/board/arm_fpga/${ARCH}/fpga_helpers.S
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BL31_SOURCES += drivers/delay_timer/delay_timer.c \
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BL31_SOURCES += common/fdt_wrappers.c \
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drivers/delay_timer/delay_timer.c \
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drivers/delay_timer/generic_delay_timer.c \
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drivers/arm/pl011/${ARCH}/pl011_console.S \
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plat/common/plat_psci_common.c \
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