nxp: nv storage api on platforms
NV storage API(s) for NXP platforms, supported on: - flexspi-nor - SecMon - General Purpose Registers at Low-Power section, retains their content if backed by coined battery. Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com> Change-Id: Id65dee4f28e7d6d2024407030039de33ebe0fa05
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#
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# Copyright 2020 NXP
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#
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# SPDX-License-Identifier: BSD-3-Clause
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#
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# NXP Non-Volatile data flag storage used and then cleared by SW on boot-up
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$(eval $(call add_define,NXP_NV_SW_MAINT_LAST_EXEC_DATA))
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ifeq ($(NXP_COINED_BB),yes)
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$(eval $(call add_define,NXP_COINED_BB))
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# BL2 : To read the reset cause from LP SECMON GPR register
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# BL31: To write the reset cause to LP SECMON GPR register
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$(eval $(call SET_NXP_MAKE_FLAG,SNVS_NEEDED,BL_COMM))
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# BL2: DDR training data is stored on Flexspi NOR.
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ifneq (${BOOT_MODE},flexspi_nor)
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$(eval $(call SET_NXP_MAKE_FLAG,XSPI_NEEDED,BL2))
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endif
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else
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$(eval $(call add_define_val,DEFAULT_NV_STORAGE_BASE_ADDR,'${BL2_BIN_XSPI_NOR_END_ADDRESS} - 2 * ${NXP_XSPI_NOR_UNIT_SIZE}'))
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$(eval $(call SET_NXP_MAKE_FLAG,XSPI_NEEDED,BL_COMM))
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endif
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NV_STORAGE_INCLUDES += -I${PLAT_COMMON_PATH}/nv_storage
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NV_STORAGE_SOURCES += ${PLAT_COMMON_PATH}/nv_storage/plat_nv_storage.c
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/*
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* Copyright 2021 NXP
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*
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*/
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#include <assert.h>
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#include <errno.h>
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#include <stddef.h>
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#include <stdint.h>
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#include <stdio.h>
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#include <stdlib.h>
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#include <string.h>
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#include <common/debug.h>
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#ifndef NXP_COINED_BB
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#include <flash_info.h>
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#include <fspi.h>
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#include <fspi_api.h>
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#endif
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#include <lib/mmio.h>
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#ifdef NXP_COINED_BB
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#include <snvs.h>
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#else
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#include <xspi_error_codes.h>
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#endif
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#include <plat_nv_storage.h>
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/*This structure will be a static structure and
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* will be populated as first step of BL2 booting-up.
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* fspi_strorage.c . To be located in the fspi driver folder.
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*/
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static nv_app_data_t nv_app_data;
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int read_nv_app_data(void)
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{
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int ret = 0;
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#ifdef NXP_COINED_BB
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uint8_t *nv_app_data_array = (uint8_t *) &nv_app_data;
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uint8_t offset = 0U;
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ret = snvs_read_app_data();
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do {
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nv_app_data_array[offset] = snvs_read_app_data_bit(offset);
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offset++;
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} while (offset < APP_DATA_MAX_OFFSET);
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snvs_clear_app_data();
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#else
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uintptr_t nv_base_addr = NV_STORAGE_BASE_ADDR;
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ret = fspi_init(NXP_FLEXSPI_ADDR, NXP_FLEXSPI_FLASH_ADDR);
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if (ret != XSPI_SUCCESS) {
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ERROR("Failed to initialized driver flexspi-nor.\n");
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ERROR("exiting warm-reset request.\n");
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return -ENODEV;
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}
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xspi_read(nv_base_addr,
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(uint32_t *)&nv_app_data, sizeof(nv_app_data_t));
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xspi_sector_erase((uint32_t) nv_base_addr,
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F_SECTOR_ERASE_SZ);
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#endif
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return ret;
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}
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int wr_nv_app_data(int data_offset,
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uint8_t *data,
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int data_size)
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{
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int ret = 0;
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#ifdef NXP_COINED_BB
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#if !TRUSTED_BOARD_BOOT
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snvs_disable_zeroize_lp_gpr();
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#endif
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/* In case LP SecMon General purpose register,
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* only 1 bit flags can be saved.
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*/
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if ((data_size > 1) || (*data != DEFAULT_SET_VALUE)) {
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ERROR("Only binary value is allowed to be written.\n");
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ERROR("Use flash instead of SNVS GPR as NV location.\n");
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return -ENODEV;
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}
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snvs_write_app_data_bit(data_offset);
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#else
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uint8_t read_val[sizeof(nv_app_data_t)];
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uint8_t ready_to_write_val[sizeof(nv_app_data_t)];
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uintptr_t nv_base_addr = NV_STORAGE_BASE_ADDR;
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assert((nv_base_addr + data_offset + data_size) > (nv_base_addr + F_SECTOR_ERASE_SZ));
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ret = fspi_init(NXP_FLEXSPI_ADDR, NXP_FLEXSPI_FLASH_ADDR);
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if (ret != XSPI_SUCCESS) {
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ERROR("Failed to initialized driver flexspi-nor.\n");
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ERROR("exiting warm-reset request.\n");
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return -ENODEV;
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}
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ret = xspi_read(nv_base_addr + data_offset, (uint32_t *)read_val, data_size);
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memset(ready_to_write_val, READY_TO_WRITE_VALUE, ARRAY_SIZE(ready_to_write_val));
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if (memcmp(read_val, ready_to_write_val, data_size) == 0) {
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xspi_write(nv_base_addr + data_offset, data, data_size);
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}
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#endif
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return ret;
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}
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const nv_app_data_t *get_nv_data(void)
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{
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return (const nv_app_data_t *) &nv_app_data;
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}
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/*
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* Copyright 2021 NXP
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*
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*/
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#ifndef PLAT_NV_STRG_H
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#define PLAT_NV_STRG_H
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#define DEFAULT_SET_VALUE 0xA1
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#define READY_TO_WRITE_VALUE 0xFF
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#ifndef NV_STORAGE_BASE_ADDR
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#define NV_STORAGE_BASE_ADDR DEFAULT_NV_STORAGE_BASE_ADDR
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#endif
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typedef struct {
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uint8_t warm_rst_flag;
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uint8_t wdt_rst_flag;
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uint8_t dummy[2];
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} nv_app_data_t;
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/*below enum and above structure should be in-sync. */
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enum app_data_offset {
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WARM_RESET_FLAG_OFFSET,
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WDT_RESET_FLAG_OFFSET,
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APP_DATA_MAX_OFFSET,
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};
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int read_nv_app_data(void);
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int wr_nv_app_data(int data_offset,
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uint8_t *data,
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int data_size);
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const nv_app_data_t *get_nv_data(void);
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#endif /* PLAT_NV_STRG_H */
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