Merge changes from topic "rpi_cpu_off" into integration
* changes: rpi: Implement PSCI CPU_OFF rpi: rpi3_pwr_domain_on(): Use MMIO accessor rpi: move plat_helpers.S to common
This commit is contained in:
Manish Pandey
TrustedFirmware Code Review
commit
7c49d39828
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -20,6 +20,7 @@
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.globl plat_reset_handler
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.globl plat_rpi3_calc_core_pos
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.globl plat_secondary_cold_boot_setup
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.globl plat_rpi_get_model
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/* -----------------------------------------------------
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* unsigned int plat_my_core_pos(void)
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@ -56,27 +57,29 @@ endfunc plat_rpi3_calc_core_pos
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func plat_is_my_cpu_primary
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mrs x0, mpidr_el1
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and x0, x0, #(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)
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cmp x0, #RPI4_PRIMARY_CPU
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cmp x0, #RPI_PRIMARY_CPU
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cset w0, eq
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ret
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endfunc plat_is_my_cpu_primary
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/* -----------------------------------------------------
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* void plat_secondary_cold_boot_setup (void);
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* void plat_wait_for_warm_boot (void);
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*
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* This function performs any platform specific actions
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* needed for a secondary cpu after a cold reset e.g
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* mark the cpu's presence, mechanism to place it in a
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* holding pen etc.
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* needed for a CPU to be put into holding pen to wait
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* for a warm boot request.
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* The function will never return.
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* -----------------------------------------------------
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*/
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func plat_secondary_cold_boot_setup
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/* Calculate address of our hold entry */
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func plat_wait_for_warm_boot
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/*
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* Calculate address of our hold entry.
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* As the function will never return, there is no need to save LR.
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*/
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bl plat_my_core_pos
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lsl x0, x0, #3
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mov_imm x2, PLAT_RPI3_TM_HOLD_BASE
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add x0, x0, x2
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/*
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* This code runs way before requesting the warmboot of this core,
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* so it is possible to clear the mailbox before getting a request
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@ -96,6 +99,19 @@ poll_mailbox:
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mov_imm x0, PLAT_RPI3_TM_ENTRYPOINT
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ldr x1, [x0]
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br x1
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endfunc plat_wait_for_warm_boot
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/* -----------------------------------------------------
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* void plat_secondary_cold_boot_setup (void);
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*
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* This function performs any platform specific actions
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* needed for a secondary cpu after a cold reset e.g
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* mark the cpu's presence, mechanism to place it in a
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* holding pen etc.
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* -----------------------------------------------------
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*/
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func plat_secondary_cold_boot_setup
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b plat_wait_for_warm_boot
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endfunc plat_secondary_cold_boot_setup
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/* ---------------------------------------------------------------------
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@ -110,9 +126,24 @@ endfunc plat_secondary_cold_boot_setup
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* ---------------------------------------------------------------------
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*/
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func plat_get_my_entrypoint
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/* TODO: support warm boot */
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mov x0, #0
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ret
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mov x1, x30
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bl plat_is_my_cpu_primary
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/*
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* Secondaries always cold boot.
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*/
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cbz w0, 1f
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/*
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* Primaries warm boot if they are requested
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* to power off.
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*/
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mov_imm x0, PLAT_RPI3_TM_HOLD_BASE
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ldr x0, [x0]
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cmp x0, PLAT_RPI3_TM_HOLD_STATE_BSP_OFF
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adr x0, plat_wait_for_warm_boot
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csel x0, x0, xzr, eq
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ret x1
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1: mov x0, #0
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ret x1
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endfunc plat_get_my_entrypoint
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/* ---------------------------------------------
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@ -164,11 +195,38 @@ func plat_crash_console_flush
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b console_16550_core_flush
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endfunc plat_crash_console_flush
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/* ---------------------------------------------
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* int plat_rpi_get_model()
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* Macro to determine whether we are running on
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* a Raspberry Pi 3 or 4. Just checks the MIDR for
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* being either a Cortex-A72 or a Cortex-A53.
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* Out : return 4 if RPi4, 3 otherwise.
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* Clobber list : x0
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* ---------------------------------------------
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*/
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.macro _plat_rpi_get_model
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mrs x0, midr_el1
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and x0, x0, #0xf0 /* Isolate low byte of part number */
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cmp w0, #0x80 /* Cortex-A72 (RPi4) is 0xd08, A53 is 0xd03 */
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mov w0, #3
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csinc w0, w0, w0, ne
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.endm
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func plat_rpi_get_model
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_plat_rpi_get_model
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ret
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endfunc plat_rpi_get_model
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/* ---------------------------------------------
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* void plat_reset_handler(void);
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* ---------------------------------------------
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*/
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func plat_reset_handler
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/* L2 cache setup only needed on RPi4 */
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_plat_rpi_get_model
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cmp w0, #4
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b.ne 1f
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/* ------------------------------------------------
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* Set L2 read/write cache latency:
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* - L2 Data RAM latency: 3 cycles (0b010)
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@ -181,5 +239,6 @@ func plat_reset_handler
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msr CORTEX_A72_L2CTLR_EL1, x0
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isb
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1:
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ret
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endfunc plat_reset_handler
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@ -36,4 +36,6 @@ void plat_rpi3_io_setup(void);
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/* VideoCore firmware commands */
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int rpi3_vc_hardware_get_board_revision(uint32_t *revision);
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int plat_rpi_get_model(void);
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#endif /* RPI3_PRIVATE_H */
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@ -140,11 +140,14 @@ static int rpi3_pwr_domain_on(u_register_t mpidr)
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{
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int rc = PSCI_E_SUCCESS;
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unsigned int pos = plat_core_pos_by_mpidr(mpidr);
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uint64_t *hold_base = (uint64_t *)PLAT_RPI3_TM_HOLD_BASE;
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uintptr_t hold_base = PLAT_RPI3_TM_HOLD_BASE;
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assert(pos < PLATFORM_CORE_COUNT);
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hold_base[pos] = PLAT_RPI3_TM_HOLD_STATE_GO;
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hold_base += pos * PLAT_RPI3_TM_HOLD_ENTRY_SIZE;
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mmio_write_64(hold_base, PLAT_RPI3_TM_HOLD_STATE_GO);
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/* No cache maintenance here, hold_base is mapped as device memory. */
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/* Make sure that the write has completed */
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dsb();
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@ -171,6 +174,32 @@ static void rpi3_pwr_domain_on_finish(const psci_power_state_t *target_state)
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#endif
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}
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static void __dead2 rpi3_pwr_down_wfi(
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const psci_power_state_t *target_state)
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{
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uintptr_t hold_base = PLAT_RPI3_TM_HOLD_BASE;
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unsigned int pos = plat_my_core_pos();
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if (pos == 0) {
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/*
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* The secondaries will always be in a wait
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* for warm boot on reset, but the BSP needs
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* to be able to distinguish between waiting
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* for warm boot (e.g. after psci_off, waiting
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* for psci_on) and a cold boot.
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*/
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mmio_write_64(hold_base, PLAT_RPI3_TM_HOLD_STATE_BSP_OFF);
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/* No cache maintenance here, we run with caches off already. */
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dsb();
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isb();
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}
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write_rmr_el3(RMR_EL3_RR_BIT | RMR_EL3_AA64_BIT);
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while (1)
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;
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}
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/*******************************************************************************
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* Platform handlers for system reset and system off.
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******************************************************************************/
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@ -236,6 +265,7 @@ static const plat_psci_ops_t plat_rpi3_psci_pm_ops = {
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.pwr_domain_pwr_down_wfi = rpi3_pwr_domain_pwr_down_wfi,
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.pwr_domain_on = rpi3_pwr_domain_on,
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.pwr_domain_on_finish = rpi3_pwr_domain_on_finish,
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.pwr_domain_pwr_down_wfi = rpi3_pwr_down_wfi,
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.system_off = rpi3_system_off,
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.system_reset = rpi3_system_reset,
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.validate_power_state = rpi3_validate_power_state,
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@ -1,163 +0,0 @@
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/*
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* Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <assert_macros.S>
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#include <platform_def.h>
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.globl plat_crash_console_flush
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.globl plat_crash_console_init
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.globl plat_crash_console_putc
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.globl platform_mem_init
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.globl plat_get_my_entrypoint
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.globl plat_is_my_cpu_primary
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.globl plat_my_core_pos
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.globl plat_rpi3_calc_core_pos
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.globl plat_secondary_cold_boot_setup
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/* -----------------------------------------------------
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* unsigned int plat_my_core_pos(void)
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*
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* This function uses the plat_rpi3_calc_core_pos()
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* definition to get the index of the calling CPU.
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* -----------------------------------------------------
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*/
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func plat_my_core_pos
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mrs x0, mpidr_el1
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b plat_rpi3_calc_core_pos
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endfunc plat_my_core_pos
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/* -----------------------------------------------------
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* unsigned int plat_rpi3_calc_core_pos(u_register_t mpidr);
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*
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* CorePos = (ClusterId * 4) + CoreId
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* -----------------------------------------------------
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*/
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func plat_rpi3_calc_core_pos
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and x1, x0, #MPIDR_CPU_MASK
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and x0, x0, #MPIDR_CLUSTER_MASK
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add x0, x1, x0, LSR #6
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ret
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endfunc plat_rpi3_calc_core_pos
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/* -----------------------------------------------------
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* unsigned int plat_is_my_cpu_primary (void);
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*
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* Find out whether the current cpu is the primary
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* cpu.
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* -----------------------------------------------------
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*/
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func plat_is_my_cpu_primary
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mrs x0, mpidr_el1
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and x0, x0, #(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)
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cmp x0, #RPI3_PRIMARY_CPU
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cset w0, eq
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ret
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endfunc plat_is_my_cpu_primary
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/* -----------------------------------------------------
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* void plat_secondary_cold_boot_setup (void);
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*
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* This function performs any platform specific actions
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* needed for a secondary cpu after a cold reset e.g
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* mark the cpu's presence, mechanism to place it in a
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* holding pen etc.
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* -----------------------------------------------------
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*/
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func plat_secondary_cold_boot_setup
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/* Calculate address of our hold entry */
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bl plat_my_core_pos
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lsl x0, x0, #3
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mov_imm x2, PLAT_RPI3_TM_HOLD_BASE
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add x0, x0, x2
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/*
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* This code runs way before requesting the warmboot of this core,
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* so it is possible to clear the mailbox before getting a request
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* to boot.
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*/
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mov x1, PLAT_RPI3_TM_HOLD_STATE_WAIT
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str x1,[x0]
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/* Wait until we have a go */
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poll_mailbox:
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wfe
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ldr x1, [x0]
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cmp x1, PLAT_RPI3_TM_HOLD_STATE_GO
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bne poll_mailbox
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/* Jump to the provided entrypoint */
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mov_imm x0, PLAT_RPI3_TM_ENTRYPOINT
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ldr x1, [x0]
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br x1
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endfunc plat_secondary_cold_boot_setup
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/* ---------------------------------------------------------------------
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* uintptr_t plat_get_my_entrypoint (void);
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*
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* Main job of this routine is to distinguish between a cold and a warm
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* boot.
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*
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* This functions returns:
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* - 0 for a cold boot.
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* - Any other value for a warm boot.
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* ---------------------------------------------------------------------
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*/
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func plat_get_my_entrypoint
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/* TODO: support warm boot */
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mov x0, #0
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ret
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endfunc plat_get_my_entrypoint
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/* ---------------------------------------------
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* void platform_mem_init (void);
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*
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* No need to carry out any memory initialization.
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* ---------------------------------------------
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*/
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func platform_mem_init
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ret
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endfunc platform_mem_init
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/* ---------------------------------------------
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* int plat_crash_console_init(void)
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* Function to initialize the crash console
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* without a C Runtime to print crash report.
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* Clobber list : x0 - x3
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* ---------------------------------------------
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*/
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func plat_crash_console_init
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mov_imm x0, PLAT_RPI_MINI_UART_BASE
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mov x1, xzr
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mov x2, xzr
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b console_16550_core_init
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endfunc plat_crash_console_init
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/* ---------------------------------------------
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* int plat_crash_console_putc(int c)
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* Function to print a character on the crash
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* console without a C Runtime.
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* Clobber list : x1, x2
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* ---------------------------------------------
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*/
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func plat_crash_console_putc
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mov_imm x1, PLAT_RPI_MINI_UART_BASE
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b console_16550_core_putc
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endfunc plat_crash_console_putc
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/* ---------------------------------------------
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* int plat_crash_console_flush()
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* Function to force a write of all buffered
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* data that hasn't been output.
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* Out : return -1 on error else return 0.
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* Clobber list : x0, x1
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* ---------------------------------------------
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*/
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func plat_crash_console_flush
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mov_imm x0, PLAT_RPI_MINI_UART_BASE
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b console_16550_core_flush
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endfunc plat_crash_console_flush
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@ -24,7 +24,7 @@
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#define PLATFORM_CLUSTER0_CORE_COUNT PLATFORM_MAX_CPUS_PER_CLUSTER
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#define PLATFORM_CORE_COUNT PLATFORM_CLUSTER0_CORE_COUNT
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#define RPI3_PRIMARY_CPU U(0)
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#define RPI_PRIMARY_CPU U(0)
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#define PLAT_MAX_PWR_LVL MPIDR_AFFLVL1
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#define PLAT_NUM_PWR_DOMAINS (PLATFORM_CLUSTER_COUNT + \
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@ -153,6 +153,7 @@
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#define PLAT_RPI3_TM_HOLD_STATE_WAIT ULL(0)
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#define PLAT_RPI3_TM_HOLD_STATE_GO ULL(1)
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#define PLAT_RPI3_TM_HOLD_STATE_BSP_OFF ULL(2)
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/*
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* BL1 specific defines.
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|
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@ -15,6 +15,7 @@ PLAT_BL_COMMON_SOURCES := drivers/ti/uart/aarch64/16550_console.S \
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drivers/gpio/gpio.c \
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drivers/delay_timer/delay_timer.c \
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drivers/rpi3/gpio/rpi3_gpio.c \
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plat/rpi/common/aarch64/plat_helpers.S \
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plat/rpi/common/rpi3_common.c \
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${XLAT_TABLES_LIB_SRCS}
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@ -23,7 +24,6 @@ BL1_SOURCES += drivers/io/io_fip.c \
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drivers/io/io_storage.c \
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lib/cpus/aarch64/cortex_a53.S \
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plat/common/aarch64/platform_mp_stack.S \
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plat/rpi/rpi3/aarch64/plat_helpers.S \
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plat/rpi/rpi3/rpi3_bl1_setup.c \
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plat/rpi/common/rpi3_io_storage.c \
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drivers/rpi3/mailbox/rpi3_mbox.c \
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@ -38,7 +38,6 @@ BL2_SOURCES += common/desc_image_load.c \
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drivers/mmc/mmc.c \
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drivers/rpi3/sdhost/rpi3_sdhost.c \
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plat/common/aarch64/platform_mp_stack.S \
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plat/rpi/rpi3/aarch64/plat_helpers.S \
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plat/rpi/rpi3/aarch64/rpi3_bl2_mem_params_desc.c \
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plat/rpi/rpi3/rpi3_bl2_setup.c \
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plat/rpi/common/rpi3_image_load.c \
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@ -46,7 +45,6 @@ BL2_SOURCES += common/desc_image_load.c \
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BL31_SOURCES += lib/cpus/aarch64/cortex_a53.S \
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plat/common/plat_psci_common.c \
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plat/rpi/rpi3/aarch64/plat_helpers.S \
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plat/rpi/rpi3/rpi3_bl31_setup.c \
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plat/rpi/common/rpi3_pm.c \
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plat/rpi/common/rpi3_topology.c \
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|
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@ -24,7 +24,7 @@
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#define PLATFORM_CLUSTER0_CORE_COUNT PLATFORM_MAX_CPUS_PER_CLUSTER
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#define PLATFORM_CORE_COUNT PLATFORM_CLUSTER0_CORE_COUNT
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|
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#define RPI4_PRIMARY_CPU U(0)
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#define RPI_PRIMARY_CPU U(0)
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#define PLAT_MAX_PWR_LVL MPIDR_AFFLVL1
|
||||
#define PLAT_NUM_PWR_DOMAINS (PLATFORM_CLUSTER_COUNT + \
|
||||
|
|
@ -93,6 +93,7 @@
|
|||
|
||||
#define PLAT_RPI3_TM_HOLD_STATE_WAIT ULL(0)
|
||||
#define PLAT_RPI3_TM_HOLD_STATE_GO ULL(1)
|
||||
#define PLAT_RPI3_TM_HOLD_STATE_BSP_OFF ULL(2)
|
||||
|
||||
/*
|
||||
* BL31 specific defines.
|
||||
|
|
|
|||
|
|
@ -16,7 +16,7 @@ PLAT_BL_COMMON_SOURCES := drivers/ti/uart/aarch64/16550_console.S \
|
|||
${XLAT_TABLES_LIB_SRCS}
|
||||
|
||||
BL31_SOURCES += lib/cpus/aarch64/cortex_a72.S \
|
||||
plat/rpi/rpi4/aarch64/plat_helpers.S \
|
||||
plat/rpi/common/aarch64/plat_helpers.S \
|
||||
plat/rpi/rpi4/aarch64/armstub8_header.S \
|
||||
drivers/arm/gic/common/gic_common.c \
|
||||
drivers/arm/gic/v2/gicv2_helpers.c \
|
||||
|
|
|
|||
Loading…
Reference in New Issue