docs: nxp soc-lx2160a based platforms
Addition of documents for platforms based on NXP SoC LX2160A. Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com> Change-Id: I39ac5a9eb0b668d26301a0a24a1e6bf87f245f02
This commit is contained in:
Pankaj Gupta
Joanna Farley
parent
9dc2534fd7
commit
7c78e4f7df
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@ -27,6 +27,7 @@ Platform Ports
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imx8
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imx8m
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ls1043a
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nxp/index
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poplar
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qemu
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qemu-sbsa
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@ -0,0 +1,17 @@
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NXP Reference Development Platforms
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===================================
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.. toctree::
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:maxdepth: 1
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:caption: Contents
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nxp-layerscape
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nxp-ls-fuse-prov
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nxp-ls-tbbr
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This chapter holds documentation related to NXP reference development platforms.
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It includes details on image flashing, fuse provisioning and trusted board boot-up.
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--------------
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*Copyright (c) 2021, NXP Limited. All rights reserved.*
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@ -0,0 +1,232 @@
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NXP SoCs - Overview
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=====================
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.. section-numbering::
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:suffix: .
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The QorIQ family of ARM based SoCs that are supported on TF-A are:
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1. LX2160ARDB:
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Platform Name:
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a. lx2160ardb (Board details can be fetched from the link: `lx2160ardb`_)
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Table of supported boot-modes by each platform & platform that needs FIP-DDR:
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-----------------------------------------------------------------------------
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+---+-----------------+-------+--------+-------+-------+-------+-------------+--------------+-----------------+
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| | BOOT_MODE-->| sd | qspi | nor | nand | emmc | flexspi_nor | flexspi_nand | fip_ddr needed |
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| | | | | | | | | | |
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| | PLAT | | | | | | | | |
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+===+=================+=======+========+=======+=======+=======+=============+==============+=================+
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| 1.| lx2160ardb | yes | | | | yes | yes | | yes |
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+---+-----------------+-------+--------+-------+-------+-------+-------------+--------------+-----------------+
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Boot Sequence
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-------------
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::
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+ Secure World | Normal World
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+ EL0 |
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+ |
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+ EL1 BL32(Tee OS) | kernel
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+ ^ | | ^
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+ | | | |
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+ EL2 | | | BL33(u-boot)
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+ | | | ^
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+ | v | /
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+ EL3 BootROM --> BL2 --> BL31 ---------------/
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+
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Boot Sequence with FIP-DDR
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--------------------------
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::
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+ Secure World | Normal World
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+ EL0 |
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+ |
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+ EL1 fip-ddr BL32(Tee OS) | kernel
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+ ^ | ^ | | ^
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+ | | | | | |
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+ EL2 | | | | | BL33(u-boot)
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+ | | | | | ^
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+ | v | v | /
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+ EL3 BootROM --> BL2 -----> BL31 ---------------/
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+
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How to build
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=============
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Code Locations
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--------------
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- OP-TEE:
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`link <https://source.codeaurora.org/external/qoriq/qoriq-components/optee_os>`__
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- U-Boot:
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`link <https://source.codeaurora.org/external/qoriq/qoriq-components/u-boot>`__
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- RCW:
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`link <https://source.codeaurora.org/external/qoriq/qoriq-components/rcw>`__
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- ddr-phy-binary: Required by platforms that need fip-ddr.
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`link <https:://github.com/NXP/ddr-phy-binary>`__
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- cst: Required for TBBR.
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`link <https:://source.codeaurora.org/external/qoriq/qoriq-components/cst>`__
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Build Procedure
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---------------
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- Fetch all the above repositories into local host.
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- Prepare AARCH64 toolchain and set the environment variable "CROSS_COMPILE".
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.. code:: shell
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export CROSS_COMPILE=.../bin/aarch64-linux-gnu-
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- Build RCW. Refer README from the respective cloned folder for more details.
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- Build u-boot and OPTee firstly, and get binary images: u-boot.bin and tee.bin.
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For u-boot you can use the <platform>_tfa_defconfig for build.
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- Copy/clone the repo "ddr-phy-binary" to the tfa directory for platform needing ddr-fip.
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- Below are the steps to build TF-A images for the supported platforms.
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Compilation steps without BL32
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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BUILD BL2:
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-To compile
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.. code:: shell
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make PLAT=$PLAT \
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BOOT_MODE=<platform_supported_boot_mode> \
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RCW=$RCW_BIN \
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pbl
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BUILD FIP:
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.. code:: shell
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make PLAT=$PLAT \
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BOOT_MODE=<platform_supported_boot_mode> \
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RCW=$RCW_BIN \
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BL33=$UBOOT_SECURE_BIN \
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pbl \
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fip
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Compilation steps with BL32
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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BUILD BL2:
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-To compile
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.. code:: shell
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make PLAT=$PLAT \
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BOOT_MODE=<platform_supported_boot_mode> \
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RCW=$RCW_BIN \
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BL32=$TEE_BIN SPD=opteed\
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pbl
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BUILD FIP:
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.. code:: shell
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make PLAT=$PLAT \
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BOOT_MODE=<platform_supported_boot_mode> \
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RCW=$RCW_BIN \
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BL32=$TEE_BIN SPD=opteed\
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BL33=$UBOOT_SECURE_BIN \
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pbl \
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fip
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BUILD fip-ddr (Mandatory for certain platforms, refer table above):
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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-To compile additional fip-ddr for selected platforms(Refer above table if the platform needs fip-ddr).
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.. code:: shell
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make PLAT=<platform_name> fip-ddr
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Deploy ATF Images
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=================
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Note: The size in the standard uboot commands for copy to nor, qspi, nand or sd
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should be modified based on the binary size of the image to be copied.
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- Deploy ATF images on flexspi-Nor flash Alt Bank from U-Boot prompt.
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-- Commands to flash images for bl2_xxx.pbl and fip.bin.
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.. code:: shell
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tftp 82000000 $path/bl2_flexspi_nor.pbl;
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i2c mw 66 50 20;sf probe 0:0; sf erase 0 +$filesize; sf write 0x82000000 0x0 $filesize;
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tftp 82000000 $path/fip.bin;
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i2c mw 66 50 20;sf probe 0:0; sf erase 0x100000 +$filesize; sf write 0x82000000 0x100000 $filesize;
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-- Next step is valid for platform where FIP-DDR is needed.
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.. code:: shell
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tftp 82000000 $path/ddr_fip.bin;
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i2c mw 66 50 20;sf probe 0:0; sf erase 0x800000 +$filesize; sf write 0x82000000 0x800000 $filesize;
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-- Then reset to alternate bank to boot up ATF.
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.. code:: shell
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qixisreset altbank;
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- Deploy ATF images on SD/eMMC from U-Boot prompt.
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-- file_size_in_block_sizeof_512 = (Size_of_bytes_tftp / 512)
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.. code:: shell
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mmc dev <idx>; (idx = 1 for eMMC; idx = 0 for SD)
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tftp 82000000 $path/bl2_<sd>_or_<emmc>.pbl;
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mmc write 82000000 8 <file_size_in_block_sizeof_512>;
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tftp 82000000 $path/fip.bin;
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mmc write 82000000 0x800 <file_size_in_block_sizeof_512>;
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-- Next step is valid for platform that needs FIP-DDR.
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.. code:: shell
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tftp 82000000 $path/ddr_fip.bin;
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mmc write 82000000 0x4000 <file_size_in_block_sizeof_512>;
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-- Then reset to sd/emmc to boot up ATF from sd/emmc as boot-source.
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.. code:: shell
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qixisreset <sd or emmc>;
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Trusted Board Boot:
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===================
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For TBBR, the binary name changes:
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+-------------+--------------------------+---------+-------------------+
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| Boot Type | BL2 | FIP | FIP-DDR |
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+=============+==========================+=========+===================+
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| Normal Boot | bl2_<boot_mode>.pbl | fip.bin | ddr_fip.bin |
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+-------------+--------------------------+---------+-------------------+
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| TBBR Boot | bl2_<boot_mode>_sec.pbl | fip.bin | ddr_fip_sec.bin |
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+-------------+--------------------------+---------+-------------------+
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Refer `nxp-ls-tbbr.rst`_ for detailed user steps.
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.. _lx2160ardb: https://www.nxp.com/products/processors-and-microcontrollers/arm-processors/layerscape-communication-process/layerscape-lx2160a-multicore-communications-processor:LX2160A
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.. _nxp-ls-tbbr.rst: ./nxp-ls-tbbr.rst
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@ -0,0 +1,271 @@
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Steps to blow fuses on NXP LS SoC:
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==================================
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- Enable POVDD
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-- Refer board GSG(Getting Started Guide) for the steps to enable POVDD.
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-- Once the POVDD is enabled, make sure to set variable POVDD_ENABLE := yes, in the platform.mk.
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+---+-----------------+-----------+------------+-----------------+-----------------------------+
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| | Platform | Jumper | Switch | LED to Verify | Through GPIO Pin (=number) |
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+===+=================+===========+============+=================+=============================+
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| 1.| lx2160ardb | J9 | | | no |
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+---+-----------------+-----------+------------+-----------------+-----------------------------+
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| 2.| lx2160aqds | J35 | | | no |
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+---+-----------------+-----------+------------+-----------------+-----------------------------+
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| 3.| lx2162aqds | J35 | SW9[4] = 1 | D15 | no |
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+---+-----------------+-----------+------------+-----------------+-----------------------------+
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- SFP registers to be written to:
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+---+----------------------------------+----------------------+----------------------+
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| | Platform | OTPMKR0..OTPMKR7 | SRKHR0..SRKHR7 |
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+===+==================================+======================+======================+
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| 1.| lx2160ardb/lx2160aqds/lx2162aqds | 0x1e80234..0x1e80250 | 0x1e80254..0x1e80270 |
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+---+----------------------------------+----------------------+----------------------+
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- At U-Boot prompt, verify that SNVS register - HPSR, whether OTPMK was written, already:
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+---+----------------------------------+-------------------------------------------+---------------+
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| | Platform | OTPMK_ZERO_BIT(=value) | SNVS_HPSR_REG |
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+===+==================================+===========================================+===============+
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| 1.| lx2160ardb/lx2160aqds/lx2162aqds | 27 (= 1 means not blown, =0 means blown) | 0x01E90014 |
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+---+----------------------------------+-------------------------------------------+---------------+
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From u-boot prompt:
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-- Check for the OTPMK.
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.. code:: shell
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md $SNVS_HPSR_REG
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Command Output:
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01e90014: 88000900
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In case it is read as 00000000, then read this register using jtag (in development mode only through CW tap).
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+0 +4 +8 +C
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[0x01E90014] 88000900
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Note: OTPMK_ZERO_BIT is 1, indicating that the OTPMK is not blown.
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-- Check for the SRK Hash.
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.. code:: shell
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md $SRKHR0 0x10
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Command Output:
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01e80254: 00000000 00000000 00000000 00000000 ................
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01e80264: 00000000 00000000 00000000 00000000 ................
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Note: Zero means that SRK hash is not blown.
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- If not blown, then from the U-Boot prompt, using following commands:
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-- Provision the OTPMK.
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.. code:: shell
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mw.l $OTPMKR0 <OTMPKR_0_32Bit_val>
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mw.l $OTPMKR1 <OTMPKR_1_32Bit_val>
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mw.l $OTPMKR2 <OTMPKR_2_32Bit_val>
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mw.l $OTPMKR3 <OTMPKR_3_32Bit_val>
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mw.l $OTPMKR4 <OTMPKR_4_32Bit_val>
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mw.l $OTPMKR5 <OTMPKR_5_32Bit_val>
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mw.l $OTPMKR6 <OTMPKR_6_32Bit_val>
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mw.l $OTPMKR7 <OTMPKR_7_32Bit_val>
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-- Provision the SRK Hash.
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.. code:: shell
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mw.l $SRKHR0 <SRKHR_0_32Bit_val>
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mw.l $SRKHR1 <SRKHR_1_32Bit_val>
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mw.l $SRKHR2 <SRKHR_2_32Bit_val>
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mw.l $SRKHR3 <SRKHR_3_32Bit_val>
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mw.l $SRKHR4 <SRKHR_4_32Bit_val>
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mw.l $SRKHR5 <SRKHR_5_32Bit_val>
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mw.l $SRKHR6 <SRKHR_6_32Bit_val>
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mw.l $SRKHR7 <SRKHR_7_32Bit_val>
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Note: SRK Hash should be carefully written keeping in mind the SFP Block Endianness.
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- At U-Boot prompt, verify that SNVS registers for OTPMK are correctly written:
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-- Check for the OTPMK.
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.. code:: shell
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md $SNVS_HPSR_REG
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Command Output:
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01e90014: 80000900
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OTPMK_ZERO_BIT is zero, indicating that the OTPMK is blown.
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Note: In case it is read as 00000000, then read this register using jtag (in development mode only through CW tap).
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.. code:: shell
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md $OTPMKR0 0x10
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Command Output:
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01e80234: ffffffff ffffffff ffffffff ffffffff ................
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01e80244: ffffffff ffffffff ffffffff ffffffff ................
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Note: OTPMK will never be visible in plain.
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-- Check for the SRK Hash. For example, if following SRK hash is written:
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SFP SRKHR0 = fdc2fed4
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SFP SRKHR1 = 317f569e
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SFP SRKHR2 = 1828425c
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SFP SRKHR3 = e87b5cfd
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SFP SRKHR4 = 34beab8f
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SFP SRKHR5 = df792a70
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SFP SRKHR6 = 2dff85e1
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SFP SRKHR7 = 32a29687,
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then following would be the value on dumping SRK hash.
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.. code:: shell
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md $SRKHR0 0x10
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Command Output:
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01e80254: d4fec2fd 9e567f31 5c422818 fd5c7be8 ....1.V..(B\.{\.
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01e80264: 8fabbe34 702a79df e185ff2d 8796a232 4....y*p-...2...
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Note: SRK Hash is visible in plain based on the SFP Block Endianness.
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- Caution: Donot proceed to the next step, until you are sure that OTPMK and SRKH are correctly blown from above steps.
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-- After the next step, there is no turning back.
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-- Fuses will be burnt, which cannot be undo.
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- Write SFP_INGR[INST] with the PROGFB(0x2) instruction to blow the fuses.
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-- User need to save the SRK key pair and OTPMK Key forever, to continue using this board.
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+---+----------------------------------+-------------------------------------------+-----------+
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| | Platform | SFP_INGR_REG | SFP_WRITE_DATE_FRM_MIRROR_REG_TO_FUSE |
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+===+==================================+=======================================================+
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| 1.| lx2160ardb/lx2160aqds/lx2162aqds | 0x01E80020 | 0x2 |
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+---+----------------------------------+--------------+----------------------------------------+
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.. code:: shell
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md $SFP_INGR_REG $SFP_WRITE_DATE_FRM_MIRROR_REG_TO_FUSE
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- On reset, if the SFP register were read from u-boot, it will show the following:
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-- Check for the OTPMK.
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.. code:: shell
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md $SNVS_HPSR_REG
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Command Output:
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01e90014: 80000900
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In case it is read as 00000000, then read this register using jtag (in development mode only through CW tap).
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+0 +4 +8 +C
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[0x01E90014] 80000900
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Note: OTPMK_ZERO_BIT is zero, indicating that the OTPMK is blown.
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.. code:: shell
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md $OTPMKR0 0x10
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Command Output:
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01e80234: ffffffff ffffffff ffffffff ffffffff ................
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01e80244: ffffffff ffffffff ffffffff ffffffff ................
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Note: OTPMK will never be visible in plain.
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-- SRK Hash
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.. code:: shell
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md $SRKHR0 0x10
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||||
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Command Output:
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01e80254: d4fec2fd 9e567f31 5c422818 fd5c7be8 ....1.V..(B\.{\.
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01e80264: 8fabbe34 702a79df e185ff2d 8796a232 4....y*p-...2...
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||||
Note: SRK Hash is visible in plain based on the SFP Block Endianness.
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||||
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||||
Second method to do the fuse provsioning:
|
||||
=========================================
|
||||
|
||||
This method is used for quick way to provision fuses.
|
||||
Typically used by those who needs to provision number of boards.
|
||||
|
||||
- Enable POVDD:
|
||||
-- Refer the table above to enable POVDD.
|
||||
|
||||
Note: If GPIO Pin supports enabling POVDD, it can be done through the below input_fuse_file.
|
||||
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||||
-- Once the POVDD is enabled, make sure to set variable POVDD_ENABLE := yes, in the platform.mk.
|
||||
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||||
- User need to populate the "input_fuse_file", corresponding to the platform for:
|
||||
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||||
-- OTPMK
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||||
-- SRKH
|
||||
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||||
Table of fuse provisioning input file for every supported platform:
|
||||
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||||
+---+----------------------------------+-----------------------------------------------------------------+
|
||||
| | Platform | FUSE_PROV_FILE |
|
||||
+===+==================================+=================================================================+
|
||||
| 1.| lx2160ardb/lx2160aqds/lx2162aqds | ${CST_DIR}/input_files/gen_fusescr/ls2088_1088/input_fuse_file |
|
||||
+---+----------------------------------+--------------+--------------------------------------------------+
|
||||
|
||||
- Create the TF-A binary with FUSE_PROG=1.
|
||||
|
||||
.. code:: shell
|
||||
|
||||
make PLAT=$PLAT FUSE_PROG=1\
|
||||
BOOT_MODE=<platform_supported_boot_mode> \
|
||||
RCW=$RCW_BIN \
|
||||
BL32=$TEE_BIN SPD=opteed\
|
||||
BL33=$UBOOT_SECURE_BIN \
|
||||
pbl \
|
||||
fip \
|
||||
fip_fuse \
|
||||
FUSE_PROV_FILE=../../apps/security/cst/input_files/gen_fusescr/ls2088_1088/input_fuse_file
|
||||
|
||||
- Deployment:
|
||||
-- Refer the nxp-layerscape.rst for deploying TF-A images.
|
||||
-- Deploying fip_fuse.bin:
|
||||
|
||||
For Flexspi-Nor:
|
||||
|
||||
.. code:: shell
|
||||
|
||||
tftp 82000000 $path/fuse_fip.bin;
|
||||
i2c mw 66 50 20;sf probe 0:0; sf erase 0x880000 +$filesize; sf write 0x82000000 0x880000 $filesize;
|
||||
|
||||
For SD or eMMC [file_size_in_block_sizeof_512 = (Size_of_bytes_tftp / 512)]:
|
||||
|
||||
.. code:: shell
|
||||
|
||||
tftp 82000000 $path/fuse_fip.bin;
|
||||
mmc write 82000000 0x4408 <file_size_in_block_sizeof_512>;
|
||||
|
||||
- Valiation:
|
||||
|
||||
+---+----------------------------------+---------------------------------------------------+
|
||||
| | Platform | Error_Register | Error_Register_Address |
|
||||
+===+==================================+===================================================+
|
||||
| 1.| lx2160ardb/lx2160aqds/lx2162aqds | DCFG scratch 4 register | 0x01EE020C |
|
||||
+---+----------------------------------+---------------------------------------------------+
|
||||
|
||||
At the U-Boot prompt, check DCFG scratch 4 register for any error.
|
||||
|
||||
.. code:: shell
|
||||
|
||||
md $Error_Register_Address 1
|
||||
|
||||
Command Ouput:
|
||||
01ee020c: 00000000
|
||||
|
||||
Note:
|
||||
- 0x00000000 shows no error, then fuse provisioning is successful.
|
||||
- For non-zero value, refer the code header file ".../drivers/nxp/sfp/sfp_error_codes.h"
|
||||
|
|
@ -0,0 +1,210 @@
|
|||
|
||||
--------------
|
||||
NXP Platforms:
|
||||
--------------
|
||||
TRUSTED_BOARD_BOOT option can be enabled by specifying TRUSTED_BOARD_BOOT=1 on command line during make.
|
||||
|
||||
|
||||
|
||||
Bare-Minimum Preparation to run TBBR on NXP Platforms:
|
||||
=======================================================
|
||||
- OTPMK(One Time Programable Key) needs to be burnt in fuses.
|
||||
-- It is the 256 bit key that stores a secret value used by the NXP SEC 4.0 IP in Trusted or Secure mode.
|
||||
|
||||
Note: It is primarily for the purpose of decrypting additional secrets stored in system non-volatile memory.
|
||||
|
||||
-- NXP CST tool gives an option to generate it.
|
||||
|
||||
Use the below command from directory 'cst', with correct options.
|
||||
|
||||
.. code:: shell
|
||||
|
||||
./gen_otpmk_drbg
|
||||
|
||||
- SRKH (Super Root Key Hash) needs to be burnt in fuses.
|
||||
-- It is the 256 bit hash of the list of the public keys of the SRK key pair.
|
||||
-- NXP CST tool gives an option to generate the RSA key pair and its hash.
|
||||
|
||||
Use the below command from directory 'cst', with correct options.
|
||||
|
||||
.. code:: shell
|
||||
|
||||
./gen_keys
|
||||
|
||||
Refer fuse frovisioning readme 'nxp-ls-fuse-prov.rst' for steps to blow these keys.
|
||||
|
||||
|
||||
|
||||
Two options are provided for TRUSTED_BOARD_BOOT:
|
||||
================================================
|
||||
|
||||
-------------------------------------------------------------------------
|
||||
Option 1: CoT using X 509 certificates
|
||||
-------------------------------------------------------------------------
|
||||
|
||||
- This CoT is as provided by ARM.
|
||||
|
||||
- To use this option user needs to specify mbedtld dir path in MBEDTLS_DIR.
|
||||
|
||||
- To generate CSF header, path of CST repository needs to be specified as CST_DIR
|
||||
|
||||
- CSF header is embedded to each of the BL2 image.
|
||||
|
||||
- GENERATE_COT=1 adds the tool 'cert_create' to the build environment to generate:
|
||||
-- X509 Certificates as (.crt) files.
|
||||
-- X509 Pem key file as (.pem) files.
|
||||
|
||||
- SAVE_KEYS=1 saves the keys and certificates, if GENERATE_COT=1.
|
||||
-- For this to work, file name for cert and keys are provided as part of compilation or build command.
|
||||
|
||||
--- default file names will be used, incase not provided as part compilation or build command.
|
||||
--- default folder 'BUILD_PLAT' will be used to store them.
|
||||
|
||||
- ROTPK for x.509 certificates is generated and embedded in bl2.bin and
|
||||
verified as part of CoT by Boot ROM during secure boot.
|
||||
|
||||
- Compilation steps:
|
||||
|
||||
All Images
|
||||
.. code:: shell
|
||||
|
||||
make PLAT=$PLAT TRUSTED_BOARD_BOOT=1 GENERATE_COT=1 MBEDTLS_DIR=$MBEDTLS_PATH CST_DIR=$CST_DIR_PATH \
|
||||
BOOT_MODE=<platform_supported_boot_mode> \
|
||||
RCW=$RCW_BIN \
|
||||
BL32=$TEE_BIN SPD=opteed\
|
||||
BL33=$UBOOT_SECURE_BIN \
|
||||
pbl \
|
||||
fip
|
||||
|
||||
Additional FIP_DDR Image (For NXP platforms like lx2160a)
|
||||
.. code:: shell
|
||||
|
||||
make PLAT=$PLAT TRUSTED_BOARD_BOOT=1 GENERATE_COT=1 MBEDTLS_DIR=$MBEDTLS_PATH fip_ddr
|
||||
|
||||
Note: make target 'fip_ddr' should never be combine with other make target 'fip', 'pbl' & 'bl2'.
|
||||
|
||||
-------------------------------------------------------------------------
|
||||
Option 2: CoT using NXP CSF headers.
|
||||
-------------------------------------------------------------------------
|
||||
|
||||
- This option is automatically selected when TRUSTED_BOARD_BOOT is set but MBEDTLS_DIR path is not specified.
|
||||
|
||||
- CSF header is embedded to each of the BL31, BL32 and BL33 image.
|
||||
|
||||
- To generate CSF header, path of CST repository needs to be specified as CST_DIR
|
||||
|
||||
- Default input files for CSF header generation is added in this repo.
|
||||
|
||||
- Default input file requires user to generate RSA key pair named
|
||||
-- srk.pri, and
|
||||
-- srk.pub, and add them in ATF repo.
|
||||
-- These keys can be generated using gen_keys tool of CST.
|
||||
|
||||
- To change the input file , user can use the options BL33_INPUT_FILE, BL32_INPUT_FILE, BL31_INPUT_FILE
|
||||
|
||||
- There are 2 paths in secure boot flow :
|
||||
-- Development Mode (sb_en in RCW = 1, SFP->OSPR, ITS = 0)
|
||||
|
||||
--- In this flow , even on ROTPK comparison failure, flow would continue.
|
||||
--- However SNVS is transitioned to non-secure state
|
||||
|
||||
-- Production mode (SFP->OSPR, ITS = 1)
|
||||
|
||||
--- Any failure is fatal failure
|
||||
|
||||
- Compilation steps:
|
||||
|
||||
All Images
|
||||
.. code:: shell
|
||||
|
||||
make PLAT=$PLAT TRUSTED_BOARD_BOOT=1 CST_DIR=$CST_DIR_PATH \
|
||||
BOOT_MODE=<platform_supported_boot_mode> \
|
||||
RCW=$RCW_BIN \
|
||||
BL32=$TEE_BIN SPD=opteed\
|
||||
BL33=$UBOOT_SECURE_BIN \
|
||||
pbl \
|
||||
fip
|
||||
|
||||
Additional FIP_DDR Image (For NXP platforms like lx2160a)
|
||||
.. code:: shell
|
||||
|
||||
make PLAT=$PLAT TRUSTED_BOARD_BOOT=1 CST_DIR=$CST_DIR_PATH fip_ddr
|
||||
|
||||
- Compilation Steps with build option for generic image processing filters to prepend CSF header:
|
||||
-- Generic image processing filters to prepend CSF header
|
||||
|
||||
BL32_INPUT_FILE = < file name>
|
||||
BL33_INPUT_FILE = <file name>
|
||||
|
||||
.. code:: shell
|
||||
|
||||
make PLAT=$PLAT TRUSTED_BOARD_BOOT=1 CST_DIR=$CST_DIR_PATH \
|
||||
BOOT_MODE=<platform_supported_boot_mode> \
|
||||
RCW=$RCW_BIN \
|
||||
BL32=$TEE_BIN SPD=opteed\
|
||||
BL33=$UBOOT_SECURE_BIN \
|
||||
BL33_INPUT_FILE = <ip file> \
|
||||
BL32_INPUT_FILE = <ip_file> \
|
||||
BL31_INPUT_FILE = <ip file> \
|
||||
pbl \
|
||||
fip
|
||||
|
||||
|
||||
Deploy ATF Images
|
||||
=================
|
||||
Same steps as mentioned in the readme "nxp-layerscape.rst".
|
||||
|
||||
|
||||
|
||||
Verification to check if Secure state is achieved:
|
||||
==================================================
|
||||
|
||||
+---+----------------+-----------------+------------------------+----------------------------------+-------------------------------+
|
||||
| | Platform | SNVS_HPSR_REG | SYS_SECURE_BIT(=value) | SYSTEM_SECURE_CONFIG_BIT(=value) | SSM_STATE |
|
||||
+===+================+=================+========================+==================================+===============================+
|
||||
| 1.| lx2160ardb or | 0x01E90014 | 15 | 14-12 | 11-8 |
|
||||
| | lx2160aqds or | | ( = 1, BootROM Booted) | ( = 010 means Intent to Secure, | (=1111 means secure boot) |
|
||||
| | lx2162aqds | | | ( = 000 Unsecure) | (=1011 means Non-secure Boot) |
|
||||
+---+----------------+-----------------+------------------------+----------------------------------+-------------------------------+
|
||||
|
||||
- Production mode (SFP->OSPR, ITS = 1)
|
||||
-- Linux prompt will successfully come. if the TBBR is successful.
|
||||
|
||||
--- Else, Linux boot will be successful.
|
||||
|
||||
-- For secure-boot status, read SNVS Register $SNVS_HPSR_REG from u-boot prompt:
|
||||
|
||||
.. code:: shell
|
||||
|
||||
md $SNVS_HPSR_REG
|
||||
|
||||
Command Output:
|
||||
1e90014: 8000AF00
|
||||
|
||||
In case it is read as 00000000, then read this register using jtag (in development mode only through CW tap).
|
||||
+0 +4 +8 +C
|
||||
[0x01E90014] 8000AF00
|
||||
|
||||
|
||||
- Development Mode (sb_en in RCW = 1, SFP->OSPR, ITS = 0)
|
||||
-- Refer the SoC specific table to read the register to interpret whether the secure boot is achieved or not.
|
||||
-- Using JTAG (in development environment only, using CW tap):
|
||||
|
||||
--- For secure-boot status, read SNVS Register $SNVS_HPSR_REG
|
||||
|
||||
.. code:: shell
|
||||
|
||||
ccs::display_regs 86 0x01E90014 4 0 1
|
||||
|
||||
Command Output:
|
||||
Using the SAP chain position number 86, following is the output.
|
||||
|
||||
+0 +4 +8 +C
|
||||
[0x01E90014] 8000AF00
|
||||
|
||||
Note: Chain position number will vary from one SoC to other SoC.
|
||||
|
||||
- Interpretation of the value:
|
||||
|
||||
-- 0xA indicates BootROM booted, with intent to secure.
|
||||
-- 0xF = secure boot, as SSM_STATE.
|
||||
Loading…
Reference in New Issue