From 7c802c715f14b203e5dfc7e4ccee498b861eb406 Mon Sep 17 00:00:00 2001 From: Tomas Pilar Date: Wed, 28 Oct 2020 15:34:12 +0000 Subject: [PATCH] Define registers for FEAT_RNG support Add ISAR0 feature register read helper, location of FEAT_RNG bits, feature support helper and the rndr/rndrrs register read helpers. Signed-off-by: Tomas Pilar Change-Id: I2a785a36f62a917548e55892ce92fa8b72fcb99d --- include/arch/aarch64/arch.h | 4 ++++ include/arch/aarch64/arch_features.h | 6 ++++++ include/arch/aarch64/arch_helpers.h | 5 +++++ 3 files changed, 15 insertions(+) diff --git a/include/arch/aarch64/arch.h b/include/arch/aarch64/arch.h index 09e598a2d..2cdc7b230 100644 --- a/include/arch/aarch64/arch.h +++ b/include/arch/aarch64/arch.h @@ -193,6 +193,10 @@ #define ID_AA64DFR0_MTPMU_MASK ULL(0xf) #define ID_AA64DFR0_MTPMU_SUPPORTED ULL(1) +/* ID_AA64ISAR0_EL1 definitions */ +#define ID_AA64ISAR0_RNDR_SHIFT U(60) +#define ID_AA64ISAR0_RNDR_MASK ULL(0xf) + /* ID_AA64ISAR1_EL1 definitions */ #define ID_AA64ISAR1_EL1 S3_0_C0_C6_1 #define ID_AA64ISAR1_GPI_SHIFT U(28) diff --git a/include/arch/aarch64/arch_features.h b/include/arch/aarch64/arch_features.h index 6b5d32696..671b3dc60 100644 --- a/include/arch/aarch64/arch_features.h +++ b/include/arch/aarch64/arch_features.h @@ -76,6 +76,12 @@ static inline unsigned long int get_armv8_6_ecv_support(void) ID_AA64MMFR0_EL1_ECV_MASK); } +static inline bool is_armv8_5_rng_present(void) +{ + return ((read_id_aa64isar0_el1() >> ID_AA64ISAR0_RNDR_SHIFT) & + ID_AA64ISAR0_RNDR_MASK); +} + /* * Return MPAM version: * diff --git a/include/arch/aarch64/arch_helpers.h b/include/arch/aarch64/arch_helpers.h index 5d1bc948c..7fafafc5a 100644 --- a/include/arch/aarch64/arch_helpers.h +++ b/include/arch/aarch64/arch_helpers.h @@ -245,6 +245,7 @@ void disable_mmu_icache_el3(void); DEFINE_SYSREG_RW_FUNCS(par_el1) DEFINE_SYSREG_READ_FUNC(id_pfr1_el1) +DEFINE_SYSREG_READ_FUNC(id_aa64isar0_el1) DEFINE_SYSREG_READ_FUNC(id_aa64isar1_el1) DEFINE_SYSREG_READ_FUNC(id_aa64pfr0_el1) DEFINE_SYSREG_READ_FUNC(id_aa64pfr1_el1) @@ -522,6 +523,10 @@ DEFINE_RENAME_SYSREG_RW_FUNCS(tfsr_el1, TFSR_EL1) DEFINE_RENAME_SYSREG_RW_FUNCS(rgsr_el1, RGSR_EL1) DEFINE_RENAME_SYSREG_RW_FUNCS(gcr_el1, GCR_EL1) +/* Armv8.5 FEAT_RNG Registers */ +DEFINE_SYSREG_READ_FUNC(rndr) +DEFINE_SYSREG_READ_FUNC(rndrrs) + /* DynamIQ Shared Unit power management */ DEFINE_RENAME_SYSREG_RW_FUNCS(clusterpwrdn_el1, CLUSTERPWRDN_EL1)