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Merge "rcar_gen3: plat: Rename RCAR_PRODUCT_* to PRR_PRODUCT_*" into integration

This commit is contained in:
Paul Beesley 2019-08-20 14:14:03 +00:00 committed by TrustedFirmware Code Review
parent 44f4bb24ff df51d8fe7e
commit 7cc287dea6
13 changed files with 135 additions and 147 deletions
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14
drivers/renesas/rcar/emmc/emmc_interrupt.c
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@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights
* reserved. * reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
@ -26,17 +26,17 @@ uint32_t emmc_interrupt(void)
uint32_t end_bit; uint32_t end_bit;
prr_data = mmio_read_32((uintptr_t) RCAR_PRR); prr_data = mmio_read_32((uintptr_t) RCAR_PRR);
cut_ver = prr_data & RCAR_CUT_MASK; cut_ver = prr_data & PRR_CUT_MASK;
if ((prr_data & RCAR_PRODUCT_MASK) == RCAR_PRODUCT_H3) { if ((prr_data & PRR_PRODUCT_MASK) == PRR_PRODUCT_H3) {
if (cut_ver == RCAR_CUT_VER10) { if (cut_ver == PRR_PRODUCT_10) {
end_bit = BIT17; end_bit = BIT17;
} else if (cut_ver == RCAR_CUT_VER11) { } else if (cut_ver == PRR_PRODUCT_11) {
end_bit = BIT17; end_bit = BIT17;
} else { } else {
end_bit = BIT20; end_bit = BIT20;
} }
} else if ((prr_data & RCAR_PRODUCT_MASK) == RCAR_PRODUCT_M3) { } else if ((prr_data & PRR_PRODUCT_MASK) == PRR_PRODUCT_M3) {
if (cut_ver == RCAR_CUT_VER10) { if (cut_ver == PRR_PRODUCT_10) {
end_bit = BIT17; end_bit = BIT17;
} else { } else {
end_bit = BIT20; end_bit = BIT20;

14
drivers/renesas/rcar/emmc/emmc_mount.c
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@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved. * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
@ -29,14 +29,14 @@ static void emmc_set_bootpartition(void)
{ {
uint32_t reg; uint32_t reg;
reg = mmio_read_32(RCAR_PRR) & (RCAR_PRODUCT_MASK | RCAR_CUT_MASK); reg = mmio_read_32(RCAR_PRR) & (PRR_PRODUCT_MASK | PRR_CUT_MASK);
if (reg == RCAR_PRODUCT_M3_CUT10) { if (reg == PRR_PRODUCT_M3_CUT10) {
mmc_drv_obj.boot_partition_en = mmc_drv_obj.boot_partition_en =
(EMMC_PARTITION_ID) ((mmc_drv_obj.ext_csd_data[179] & (EMMC_PARTITION_ID) ((mmc_drv_obj.ext_csd_data[179] &
EMMC_BOOT_PARTITION_EN_MASK) >> EMMC_BOOT_PARTITION_EN_MASK) >>
EMMC_BOOT_PARTITION_EN_SHIFT); EMMC_BOOT_PARTITION_EN_SHIFT);
} else if ((reg == RCAR_PRODUCT_H3_CUT20) } else if ((reg == PRR_PRODUCT_H3_CUT20)
|| (reg == RCAR_PRODUCT_M3_CUT11)) { || (reg == PRR_PRODUCT_M3_CUT11)) {
mmc_drv_obj.boot_partition_en = mmc_drv_obj.partition_access; mmc_drv_obj.boot_partition_en = mmc_drv_obj.partition_access;
} else { } else {
if ((mmio_read_32(MFISBTSTSR) & MFISBTSTSR_BOOT_PARTITION) != if ((mmio_read_32(MFISBTSTSR) & MFISBTSTSR_BOOT_PARTITION) !=
@ -460,8 +460,8 @@ static void emmc_get_partition_access(void)
uint32_t reg; uint32_t reg;
EMMC_ERROR_CODE result; EMMC_ERROR_CODE result;
reg = mmio_read_32(RCAR_PRR) & (RCAR_PRODUCT_MASK | RCAR_CUT_MASK); reg = mmio_read_32(RCAR_PRR) & (PRR_PRODUCT_MASK | PRR_CUT_MASK);
if ((reg == RCAR_PRODUCT_H3_CUT20) || (reg == RCAR_PRODUCT_M3_CUT11)) { if ((reg == PRR_PRODUCT_H3_CUT20) || (reg == PRR_PRODUCT_M3_CUT11)) {
SETR_32(SD_OPTION, 0x000060EEU); /* 8 bits width */ SETR_32(SD_OPTION, 0x000060EEU); /* 8 bits width */
/* CMD8 (EXT_CSD) */ /* CMD8 (EXT_CSD) */
emmc_make_trans_cmd(CMD8_SEND_EXT_CSD, 0x00000000U, emmc_make_trans_cmd(CMD8_SEND_EXT_CSD, 0x00000000U,

6
drivers/renesas/rcar/iic_dvfs/iic_dvfs.c
View File

@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved. * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
@ -189,8 +189,8 @@ IIC_DVFS_FUNC(start, DVFS_STATE_T * state)
mode = mmio_read_8(IIC_DVFS_REG_ICCR) | IIC_DVFS_BIT_ICCR_ENABLE; mode = mmio_read_8(IIC_DVFS_REG_ICCR) | IIC_DVFS_BIT_ICCR_ENABLE;
mmio_write_8(IIC_DVFS_REG_ICCR, mode); mmio_write_8(IIC_DVFS_REG_ICCR, mode);
lsi_product = mmio_read_32(RCAR_PRR) & RCAR_PRODUCT_MASK; lsi_product = mmio_read_32(RCAR_PRR) & PRR_PRODUCT_MASK;
if (lsi_product == RCAR_PRODUCT_E3) if (lsi_product == PRR_PRODUCT_E3)
goto start; goto start;
reg = mmio_read_32(RCAR_MODEMR) & CHECK_MD13_MD14; reg = mmio_read_32(RCAR_MODEMR) & CHECK_MD13_MD14;

10
drivers/renesas/rcar/pfc/M3/pfc_init_m3.c
View File

@ -615,8 +615,8 @@ static void start_rtdma0_descriptor(void)
uint32_t reg; uint32_t reg;
reg = mmio_read_32(RCAR_PRR); reg = mmio_read_32(RCAR_PRR);
reg &= (RCAR_PRODUCT_MASK | RCAR_CUT_MASK); reg &= (PRR_PRODUCT_MASK | PRR_CUT_MASK);
if (reg == (RCAR_PRODUCT_M3_CUT10)) { if (reg == (PRR_PRODUCT_M3_CUT10)) {
/* Enable clock supply to RTDMAC. */ /* Enable clock supply to RTDMAC. */
mstpcr_write(CPG_SCMSTPCR0, CPG_MSTPSR0, SCMSTPCR0_RTDMAC); mstpcr_write(CPG_SCMSTPCR0, CPG_MSTPSR0, SCMSTPCR0_RTDMAC);
@ -654,14 +654,14 @@ static void pfc_reg_write(uint32_t addr, uint32_t data)
uint32_t prr; uint32_t prr;
prr = mmio_read_32(RCAR_PRR); prr = mmio_read_32(RCAR_PRR);
prr &= (RCAR_PRODUCT_MASK | RCAR_CUT_MASK); prr &= (PRR_PRODUCT_MASK | PRR_CUT_MASK);
mmio_write_32(PFC_PMMR, ~data); mmio_write_32(PFC_PMMR, ~data);
if (prr == (RCAR_PRODUCT_M3_CUT10)) { if (prr == (PRR_PRODUCT_M3_CUT10)) {
mmio_write_16(SCIF3_SCFCR, SCFCR_DATA); /* Dummy write */ mmio_write_16(SCIF3_SCFCR, SCFCR_DATA); /* Dummy write */
} }
mmio_write_32((uintptr_t)addr, data); mmio_write_32((uintptr_t)addr, data);
if (prr == (RCAR_PRODUCT_M3_CUT10)) { if (prr == (PRR_PRODUCT_M3_CUT10)) {
mmio_write_16(SCIF3_SCFCR, SCFCR_DATA); /* Dummy write */ mmio_write_16(SCIF3_SCFCR, SCFCR_DATA); /* Dummy write */
} }
} }

10
drivers/renesas/rcar/pfc/pfc_init.c
View File

@ -57,8 +57,8 @@ void rcar_pfc_init(void)
reg = mmio_read_32(RCAR_PRR); reg = mmio_read_32(RCAR_PRR);
#if RCAR_LSI == RCAR_AUTO #if RCAR_LSI == RCAR_AUTO
switch (reg & RCAR_PRODUCT_MASK) { switch (reg & PRR_PRODUCT_MASK) {
case RCAR_PRODUCT_H3: case PRR_PRODUCT_H3:
switch (reg & PRR_CUT_MASK) { switch (reg & PRR_CUT_MASK) {
case PRR_PRODUCT_10: /* H3 Ver.1.0 */ case PRR_PRODUCT_10: /* H3 Ver.1.0 */
pfc_init_h3_v1(); pfc_init_h3_v1();
@ -71,13 +71,13 @@ void rcar_pfc_init(void)
break; break;
} }
break; break;
case RCAR_PRODUCT_M3: case PRR_PRODUCT_M3:
pfc_init_m3(); pfc_init_m3();
break; break;
case RCAR_PRODUCT_M3N: case PRR_PRODUCT_M3N:
pfc_init_m3n(); pfc_init_m3n();
break; break;
case RCAR_PRODUCT_V3M: case PRR_PRODUCT_V3M:
pfc_init_v3m(); pfc_init_v3m();
break; break;
default: default:

32
drivers/renesas/rcar/pwrc/pwrc.c
View File

@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved. * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
@ -314,16 +314,16 @@ void rcar_pwrc_clusteroff(uint64_t mpidr)
rcar_lock_get(); rcar_lock_get();
reg = mmio_read_32(RCAR_PRR); reg = mmio_read_32(RCAR_PRR);
product = reg & RCAR_PRODUCT_MASK; product = reg & PRR_PRODUCT_MASK;
cut = reg & RCAR_CUT_MASK; cut = reg & PRR_CUT_MASK;
c = rcar_pwrc_get_mpidr_cluster(mpidr); c = rcar_pwrc_get_mpidr_cluster(mpidr);
dst = IS_CA53(c) ? RCAR_CA53CPUCMCR : RCAR_CA57CPUCMCR; dst = IS_CA53(c) ? RCAR_CA53CPUCMCR : RCAR_CA57CPUCMCR;
if (RCAR_PRODUCT_M3 == product && cut < RCAR_CUT_VER30) if (PRR_PRODUCT_M3 == product && cut < PRR_PRODUCT_30)
goto done; goto done;
if (RCAR_PRODUCT_H3 == product && cut <= RCAR_CUT_VER20) if (PRR_PRODUCT_H3 == product && cut <= PRR_PRODUCT_20)
goto done; goto done;
/* all of the CPUs in the cluster is in the CoreStandby mode */ /* all of the CPUs in the cluster is in the CoreStandby mode */
@ -424,13 +424,13 @@ static void __attribute__ ((section(".system_ram")))
uint32_t reg = mmio_read_32(RCAR_PRR); uint32_t reg = mmio_read_32(RCAR_PRR);
uint32_t cut, product; uint32_t cut, product;
product = reg & RCAR_PRODUCT_MASK; product = reg & PRR_PRODUCT_MASK;
cut = reg & RCAR_CUT_MASK; cut = reg & PRR_CUT_MASK;
if (product == RCAR_PRODUCT_M3 && cut < RCAR_CUT_VER30) if (product == PRR_PRODUCT_M3 && cut < PRR_PRODUCT_30)
goto self_refresh; goto self_refresh;
if (product == RCAR_PRODUCT_H3 && cut < RCAR_CUT_VER20) if (product == PRR_PRODUCT_H3 && cut < PRR_PRODUCT_20)
goto self_refresh; goto self_refresh;
mmio_write_32(DBSC4_REG_DBSYSCNT0, DBSC4_SET_DBSYSCNT0_WRITE_ENABLE); mmio_write_32(DBSC4_REG_DBSYSCNT0, DBSC4_SET_DBSYSCNT0_WRITE_ENABLE);
@ -445,16 +445,16 @@ self_refresh:
/* Set the Self-Refresh mode */ /* Set the Self-Refresh mode */
mmio_write_32(DBSC4_REG_DBACEN, 0); mmio_write_32(DBSC4_REG_DBACEN, 0);
if (product == RCAR_PRODUCT_H3 && cut < RCAR_CUT_VER20) if (product == PRR_PRODUCT_H3 && cut < PRR_PRODUCT_20)
rcar_micro_delay(100); rcar_micro_delay(100);
else if (product == RCAR_PRODUCT_H3) { else if (product == PRR_PRODUCT_H3) {
mmio_write_32(DBSC4_REG_DBCAM0CTRL0, 1); mmio_write_32(DBSC4_REG_DBCAM0CTRL0, 1);
DBCAM_FLUSH(0); DBCAM_FLUSH(0);
DBCAM_FLUSH(1); DBCAM_FLUSH(1);
DBCAM_FLUSH(2); DBCAM_FLUSH(2);
DBCAM_FLUSH(3); DBCAM_FLUSH(3);
mmio_write_32(DBSC4_REG_DBCAM0CTRL0, 0); mmio_write_32(DBSC4_REG_DBCAM0CTRL0, 0);
} else if (product == RCAR_PRODUCT_M3) { } else if (product == PRR_PRODUCT_M3) {
mmio_write_32(DBSC4_REG_DBCAM0CTRL0, 1); mmio_write_32(DBSC4_REG_DBCAM0CTRL0, 1);
DBCAM_FLUSH(0); DBCAM_FLUSH(0);
DBCAM_FLUSH(1); DBCAM_FLUSH(1);
@ -499,10 +499,10 @@ self_refresh:
mmio_write_32(DBSC4_REG_DBRFEN, 0U); mmio_write_32(DBSC4_REG_DBRFEN, 0U);
rcar_micro_delay(1U); rcar_micro_delay(1U);
if (product == RCAR_PRODUCT_M3 && cut < RCAR_CUT_VER30) if (product == PRR_PRODUCT_M3 && cut < PRR_PRODUCT_30)
return; return;
if (product == RCAR_PRODUCT_H3 && cut < RCAR_CUT_VER20) if (product == PRR_PRODUCT_H3 && cut < PRR_PRODUCT_20)
return; return;
mmio_write_32(DBSC4_REG_DBSYSCNT0, DBSC4_SET_DBSYSCNT0_WRITE_DISABLE); mmio_write_32(DBSC4_REG_DBSYSCNT0, DBSC4_SET_DBSYSCNT0_WRITE_DISABLE);
@ -648,9 +648,9 @@ void __attribute__ ((section(".system_ram"))) __attribute__ ((noinline))
uint32_t reg, product; uint32_t reg, product;
reg = mmio_read_32(RCAR_PRR); reg = mmio_read_32(RCAR_PRR);
product = reg & RCAR_PRODUCT_MASK; product = reg & PRR_PRODUCT_MASK;
if (product != RCAR_PRODUCT_E3) if (product != PRR_PRODUCT_E3)
rcar_pwrc_set_self_refresh(); rcar_pwrc_set_self_refresh();
else else
rcar_pwrc_set_self_refresh_e3(); rcar_pwrc_set_self_refresh_e3();

22
drivers/renesas/rcar/rom/rom_api.c
View File

@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved. * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
@ -30,30 +30,30 @@ static uint32_t get_table_index(void)
uint32_t cut_ver; uint32_t cut_ver;
uint32_t index; uint32_t index;
product = mmio_read_32(RCAR_PRR) & RCAR_PRODUCT_MASK; product = mmio_read_32(RCAR_PRR) & PRR_PRODUCT_MASK;
cut_ver = mmio_read_32(RCAR_PRR) & RCAR_CUT_MASK; cut_ver = mmio_read_32(RCAR_PRR) & PRR_CUT_MASK;
switch (product) { switch (product) {
case RCAR_PRODUCT_H3: case PRR_PRODUCT_H3:
if (cut_ver == RCAR_CUT_VER10) if (cut_ver == PRR_PRODUCT_10)
index = OLD_API_TABLE1; index = OLD_API_TABLE1;
else if (cut_ver == RCAR_CUT_VER11) else if (cut_ver == PRR_PRODUCT_11)
index = OLD_API_TABLE1; index = OLD_API_TABLE1;
else if (cut_ver == RCAR_CUT_VER20) else if (cut_ver == PRR_PRODUCT_20)
index = OLD_API_TABLE2; index = OLD_API_TABLE2;
else else
/* Later than H3 Ver.2.0 */ /* Later than H3 Ver.2.0 */
index = NEW_API_TABLE; index = NEW_API_TABLE;
break; break;
case RCAR_PRODUCT_M3: case PRR_PRODUCT_M3:
if (cut_ver == RCAR_CUT_VER10) if (cut_ver == PRR_PRODUCT_10)
index = OLD_API_TABLE3; index = OLD_API_TABLE3;
else else
/* M3 Ver.1.1 or later */ /* M3 Ver.1.1 or later */
index = NEW_API_TABLE; index = NEW_API_TABLE;
break; break;
case RCAR_PRODUCT_V3M: case PRR_PRODUCT_V3M:
if (cut_ver == RCAR_CUT_VER10) if (cut_ver == PRR_PRODUCT_10)
/* V3M WS1.0 */ /* V3M WS1.0 */
index = NEW_API_TABLE2; index = NEW_API_TABLE2;
else else

6
drivers/renesas/rcar/rpc/rpc_driver.c
View File

@ -34,10 +34,10 @@ static void rpc_setup(void)
if (mmio_read_32(RPC_CMNCR) & RPC_CMNCR_MD_BIT) if (mmio_read_32(RPC_CMNCR) & RPC_CMNCR_MD_BIT)
mmio_clrbits_32(RPC_CMNCR, RPC_CMNCR_MD_BIT); mmio_clrbits_32(RPC_CMNCR, RPC_CMNCR_MD_BIT);
product = mmio_read_32(RCAR_PRR) & RCAR_PRODUCT_MASK; product = mmio_read_32(RCAR_PRR) & PRR_PRODUCT_MASK;
cut = mmio_read_32(RCAR_PRR) & RCAR_CUT_MASK; cut = mmio_read_32(RCAR_PRR) & PRR_CUT_MASK;
if ((product == RCAR_PRODUCT_M3) && (cut < RCAR_CUT_VER30)) if ((product == PRR_PRODUCT_M3) && (cut < PRR_PRODUCT_30))
phy_strtim = RPC_PHYCNT_STRTIM_M3V1; phy_strtim = RPC_PHYCNT_STRTIM_M3V1;
else else
phy_strtim = RPC_PHYCNT_STRTIM; phy_strtim = RPC_PHYCNT_STRTIM;

6
drivers/renesas/rcar/watchdog/swdt.c
View File

@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved. * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
@ -82,7 +82,7 @@ void rcar_swdt_init(void)
uint32_t reg, val, product_cut, chk_data; uint32_t reg, val, product_cut, chk_data;
reg = mmio_read_32(RCAR_PRR); reg = mmio_read_32(RCAR_PRR);
product_cut = reg & (RCAR_PRODUCT_MASK | RCAR_CUT_MASK); product_cut = reg & (PRR_PRODUCT_MASK | PRR_CUT_MASK);
reg = mmio_read_32(RCAR_MODEMR); reg = mmio_read_32(RCAR_MODEMR);
chk_data = reg & CHECK_MD13_MD14; chk_data = reg & CHECK_MD13_MD14;
@ -108,7 +108,7 @@ void rcar_swdt_init(void)
val |= WTCNT_COUNT_8p22k; val |= WTCNT_COUNT_8p22k;
break; break;
case MD14_MD13_TYPE_3: case MD14_MD13_TYPE_3:
val |= product_cut == (RCAR_PRODUCT_H3 | RCAR_CUT_VER10) ? val |= product_cut == (PRR_PRODUCT_H3 | PRR_PRODUCT_10) ?
WTCNT_COUNT_8p13k_H3VER10 : WTCNT_COUNT_8p13k; WTCNT_COUNT_8p13k_H3VER10 : WTCNT_COUNT_8p13k;
break; break;
default: default:

36
plat/renesas/rcar/bl2_cpg_init.c
View File

@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved. * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
@ -109,12 +109,12 @@ static void bl2_secure_cpg_init(void)
#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_H3) || (RCAR_LSI == RCAR_H3N) #if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_H3) || (RCAR_LSI == RCAR_H3N)
static void bl2_realtime_cpg_init_h3(void) static void bl2_realtime_cpg_init_h3(void)
{ {
uint32_t cut = mmio_read_32(RCAR_PRR) & RCAR_CUT_MASK; uint32_t cut = mmio_read_32(RCAR_PRR) & PRR_CUT_MASK;
uint32_t cr0, cr8; uint32_t cr0, cr8;
cr0 = (cut == RCAR_CUT_VER10 || cut == RCAR_CUT_VER11) ? cr0 = (cut == PRR_PRODUCT_10 || cut == PRR_PRODUCT_11) ?
0x00200000U : 0x00210000U; 0x00200000U : 0x00210000U;
cr8 = (cut == RCAR_CUT_VER10 || cut == RCAR_CUT_VER11) ? cr8 = (cut == PRR_PRODUCT_10 || cut == PRR_PRODUCT_11) ?
0x01F1FFF4U : 0x01F1FFF7U; 0x01F1FFF4U : 0x01F1FFF7U;
cpg_write(RMSTPCR0, cr0); cpg_write(RMSTPCR0, cr0);
@ -329,7 +329,7 @@ void bl2_cpg_init(void)
{ {
uint32_t boot_cpu = mmio_read_32(RCAR_MODEMR) & MODEMR_BOOT_CPU_MASK; uint32_t boot_cpu = mmio_read_32(RCAR_MODEMR) & MODEMR_BOOT_CPU_MASK;
#if RCAR_LSI == RCAR_AUTO #if RCAR_LSI == RCAR_AUTO
uint32_t product = mmio_read_32(RCAR_PRR) & RCAR_PRODUCT_MASK; uint32_t product = mmio_read_32(RCAR_PRR) & PRR_PRODUCT_MASK;
#endif #endif
bl2_secure_cpg_init(); bl2_secure_cpg_init();
@ -338,22 +338,22 @@ void bl2_cpg_init(void)
#if RCAR_LSI == RCAR_AUTO #if RCAR_LSI == RCAR_AUTO
switch (product) { switch (product) {
case RCAR_PRODUCT_H3: case PRR_PRODUCT_H3:
bl2_realtime_cpg_init_h3(); bl2_realtime_cpg_init_h3();
break; break;
case RCAR_PRODUCT_M3: case PRR_PRODUCT_M3:
bl2_realtime_cpg_init_m3(); bl2_realtime_cpg_init_m3();
break; break;
case RCAR_PRODUCT_M3N: case PRR_PRODUCT_M3N:
bl2_realtime_cpg_init_m3n(); bl2_realtime_cpg_init_m3n();
break; break;
case RCAR_PRODUCT_V3M: case PRR_PRODUCT_V3M:
bl2_realtime_cpg_init_v3m(); bl2_realtime_cpg_init_v3m();
break; break;
case RCAR_PRODUCT_E3: case PRR_PRODUCT_E3:
bl2_realtime_cpg_init_e3(); bl2_realtime_cpg_init_e3();
break; break;
case RCAR_PRODUCT_D3: case PRR_PRODUCT_D3:
bl2_realtime_cpg_init_d3(); bl2_realtime_cpg_init_d3();
break; break;
default: default:
@ -381,25 +381,25 @@ void bl2_cpg_init(void)
void bl2_system_cpg_init(void) void bl2_system_cpg_init(void)
{ {
#if RCAR_LSI == RCAR_AUTO #if RCAR_LSI == RCAR_AUTO
uint32_t product = mmio_read_32(RCAR_PRR) & RCAR_PRODUCT_MASK; uint32_t product = mmio_read_32(RCAR_PRR) & PRR_PRODUCT_MASK;
switch (product) { switch (product) {
case RCAR_PRODUCT_H3: case PRR_PRODUCT_H3:
bl2_system_cpg_init_h3(); bl2_system_cpg_init_h3();
break; break;
case RCAR_PRODUCT_M3: case PRR_PRODUCT_M3:
bl2_system_cpg_init_m3(); bl2_system_cpg_init_m3();
break; break;
case RCAR_PRODUCT_M3N: case PRR_PRODUCT_M3N:
bl2_system_cpg_init_m3n(); bl2_system_cpg_init_m3n();
break; break;
case RCAR_PRODUCT_V3M: case PRR_PRODUCT_V3M:
bl2_system_cpg_init_v3m(); bl2_system_cpg_init_v3m();
break; break;
case RCAR_PRODUCT_E3: case PRR_PRODUCT_E3:
bl2_system_cpg_init_e3(); bl2_system_cpg_init_e3();
break; break;
case RCAR_PRODUCT_D3: case PRR_PRODUCT_D3:
bl2_system_cpg_init_d3(); bl2_system_cpg_init_d3();
break; break;
default: default:

98
plat/renesas/rcar/bl2_plat_setup.c
View File

@ -65,22 +65,22 @@ static void bl2_init_generic_timer(void);
/* R-Car Gen3 product check */ /* R-Car Gen3 product check */
#if (RCAR_LSI == RCAR_H3) || (RCAR_LSI == RCAR_H3N) #if (RCAR_LSI == RCAR_H3) || (RCAR_LSI == RCAR_H3N)
#define TARGET_PRODUCT RCAR_PRODUCT_H3 #define TARGET_PRODUCT PRR_PRODUCT_H3
#define TARGET_NAME "R-Car H3" #define TARGET_NAME "R-Car H3"
#elif RCAR_LSI == RCAR_M3 #elif RCAR_LSI == RCAR_M3
#define TARGET_PRODUCT RCAR_PRODUCT_M3 #define TARGET_PRODUCT PRR_PRODUCT_M3
#define TARGET_NAME "R-Car M3" #define TARGET_NAME "R-Car M3"
#elif RCAR_LSI == RCAR_M3N #elif RCAR_LSI == RCAR_M3N
#define TARGET_PRODUCT RCAR_PRODUCT_M3N #define TARGET_PRODUCT PRR_PRODUCT_M3N
#define TARGET_NAME "R-Car M3N" #define TARGET_NAME "R-Car M3N"
#elif RCAR_LSI == RCAR_V3M #elif RCAR_LSI == RCAR_V3M
#define TARGET_PRODUCT RCAR_PRODUCT_V3M #define TARGET_PRODUCT PRR_PRODUCT_V3M
#define TARGET_NAME "R-Car V3M" #define TARGET_NAME "R-Car V3M"
#elif RCAR_LSI == RCAR_E3 #elif RCAR_LSI == RCAR_E3
#define TARGET_PRODUCT RCAR_PRODUCT_E3 #define TARGET_PRODUCT PRR_PRODUCT_E3
#define TARGET_NAME "R-Car E3" #define TARGET_NAME "R-Car E3"
#elif RCAR_LSI == RCAR_D3 #elif RCAR_LSI == RCAR_D3
#define TARGET_PRODUCT RCAR_PRODUCT_D3 #define TARGET_PRODUCT PRR_PRODUCT_D3
#define TARGET_NAME "R-Car D3" #define TARGET_NAME "R-Car D3"
#elif RCAR_LSI == RCAR_AUTO #elif RCAR_LSI == RCAR_AUTO
#define TARGET_NAME "R-Car H3/M3/M3N/V3M" #define TARGET_NAME "R-Car H3/M3/M3N/V3M"
@ -238,17 +238,17 @@ void bl2_plat_flush_bl31_params(void)
bl2_secure_setting(); bl2_secure_setting();
reg = mmio_read_32(RCAR_PRR); reg = mmio_read_32(RCAR_PRR);
product_cut = reg & (RCAR_PRODUCT_MASK | RCAR_CUT_MASK); product_cut = reg & (PRR_PRODUCT_MASK | PRR_CUT_MASK);
product = reg & RCAR_PRODUCT_MASK; product = reg & PRR_PRODUCT_MASK;
cut = reg & RCAR_CUT_MASK; cut = reg & PRR_CUT_MASK;
if (product == RCAR_PRODUCT_M3 && RCAR_CUT_VER30 > cut) if (product == PRR_PRODUCT_M3 && PRR_PRODUCT_30 > cut)
goto tlb; goto tlb;
if (product == RCAR_PRODUCT_H3 && RCAR_CUT_VER20 > cut) if (product == PRR_PRODUCT_H3 && PRR_PRODUCT_20 > cut)
goto tlb; goto tlb;
if (product == RCAR_PRODUCT_D3) if (product == PRR_PRODUCT_D3)
goto tlb; goto tlb;
/* Disable MFIS write protection */ /* Disable MFIS write protection */
@ -261,28 +261,28 @@ tlb:
boot_cpu != MODEMR_BOOT_CPU_CA53) boot_cpu != MODEMR_BOOT_CPU_CA53)
goto mmu; goto mmu;
if (product_cut == RCAR_PRODUCT_H3_CUT20) { if (product_cut == PRR_PRODUCT_H3_CUT20) {
mmio_write_32(IPMMUVI0_IMSCTLR, IMSCTLR_DISCACHE); mmio_write_32(IPMMUVI0_IMSCTLR, IMSCTLR_DISCACHE);
mmio_write_32(IPMMUVI1_IMSCTLR, IMSCTLR_DISCACHE); mmio_write_32(IPMMUVI1_IMSCTLR, IMSCTLR_DISCACHE);
mmio_write_32(IPMMUPV0_IMSCTLR, IMSCTLR_DISCACHE); mmio_write_32(IPMMUPV0_IMSCTLR, IMSCTLR_DISCACHE);
mmio_write_32(IPMMUPV1_IMSCTLR, IMSCTLR_DISCACHE); mmio_write_32(IPMMUPV1_IMSCTLR, IMSCTLR_DISCACHE);
mmio_write_32(IPMMUPV2_IMSCTLR, IMSCTLR_DISCACHE); mmio_write_32(IPMMUPV2_IMSCTLR, IMSCTLR_DISCACHE);
mmio_write_32(IPMMUPV3_IMSCTLR, IMSCTLR_DISCACHE); mmio_write_32(IPMMUPV3_IMSCTLR, IMSCTLR_DISCACHE);
} else if (product_cut == (RCAR_PRODUCT_M3N | RCAR_CUT_VER10) || } else if (product_cut == (PRR_PRODUCT_M3N | PRR_PRODUCT_10) ||
product_cut == (RCAR_PRODUCT_M3N | RCAR_CUT_VER11)) { product_cut == (PRR_PRODUCT_M3N | PRR_PRODUCT_11)) {
mmio_write_32(IPMMUVI0_IMSCTLR, IMSCTLR_DISCACHE); mmio_write_32(IPMMUVI0_IMSCTLR, IMSCTLR_DISCACHE);
mmio_write_32(IPMMUPV0_IMSCTLR, IMSCTLR_DISCACHE); mmio_write_32(IPMMUPV0_IMSCTLR, IMSCTLR_DISCACHE);
} else if ((product_cut == (RCAR_PRODUCT_E3 | RCAR_CUT_VER10)) || } else if ((product_cut == (PRR_PRODUCT_E3 | PRR_PRODUCT_10)) ||
(product_cut == (RCAR_PRODUCT_E3 | RCAR_CUT_VER11))) { (product_cut == (PRR_PRODUCT_E3 | PRR_PRODUCT_11))) {
mmio_write_32(IPMMUVI0_IMSCTLR, IMSCTLR_DISCACHE); mmio_write_32(IPMMUVI0_IMSCTLR, IMSCTLR_DISCACHE);
mmio_write_32(IPMMUVP0_IMSCTLR, IMSCTLR_DISCACHE); mmio_write_32(IPMMUVP0_IMSCTLR, IMSCTLR_DISCACHE);
mmio_write_32(IPMMUPV0_IMSCTLR, IMSCTLR_DISCACHE); mmio_write_32(IPMMUPV0_IMSCTLR, IMSCTLR_DISCACHE);
} }
if (product_cut == (RCAR_PRODUCT_H3_CUT20) || if (product_cut == (PRR_PRODUCT_H3_CUT20) ||
product_cut == (RCAR_PRODUCT_M3N | RCAR_CUT_VER10) || product_cut == (PRR_PRODUCT_M3N | PRR_PRODUCT_10) ||
product_cut == (RCAR_PRODUCT_M3N | RCAR_CUT_VER11) || product_cut == (PRR_PRODUCT_M3N | PRR_PRODUCT_11) ||
product_cut == (RCAR_PRODUCT_E3 | RCAR_CUT_VER10)) { product_cut == (PRR_PRODUCT_E3 | PRR_PRODUCT_10)) {
mmio_write_32(IPMMUHC_IMSCTLR, IMSCTLR_DISCACHE); mmio_write_32(IPMMUHC_IMSCTLR, IMSCTLR_DISCACHE);
mmio_write_32(IPMMURT_IMSCTLR, IMSCTLR_DISCACHE); mmio_write_32(IPMMURT_IMSCTLR, IMSCTLR_DISCACHE);
mmio_write_32(IPMMUMP_IMSCTLR, IMSCTLR_DISCACHE); mmio_write_32(IPMMUMP_IMSCTLR, IMSCTLR_DISCACHE);
@ -458,28 +458,28 @@ static void bl2_populate_compatible_string(void *fdt)
} }
reg = mmio_read_32(RCAR_PRR); reg = mmio_read_32(RCAR_PRR);
switch (reg & RCAR_PRODUCT_MASK) { switch (reg & PRR_PRODUCT_MASK) {
case RCAR_PRODUCT_H3: case PRR_PRODUCT_H3:
ret = fdt_appendprop_string(fdt, 0, "compatible", ret = fdt_appendprop_string(fdt, 0, "compatible",
"renesas,r8a7795"); "renesas,r8a7795");
break; break;
case RCAR_PRODUCT_M3: case PRR_PRODUCT_M3:
ret = fdt_appendprop_string(fdt, 0, "compatible", ret = fdt_appendprop_string(fdt, 0, "compatible",
"renesas,r8a7796"); "renesas,r8a7796");
break; break;
case RCAR_PRODUCT_M3N: case PRR_PRODUCT_M3N:
ret = fdt_appendprop_string(fdt, 0, "compatible", ret = fdt_appendprop_string(fdt, 0, "compatible",
"renesas,r8a77965"); "renesas,r8a77965");
break; break;
case RCAR_PRODUCT_V3M: case PRR_PRODUCT_V3M:
ret = fdt_appendprop_string(fdt, 0, "compatible", ret = fdt_appendprop_string(fdt, 0, "compatible",
"renesas,r8a77970"); "renesas,r8a77970");
break; break;
case RCAR_PRODUCT_E3: case PRR_PRODUCT_E3:
ret = fdt_appendprop_string(fdt, 0, "compatible", ret = fdt_appendprop_string(fdt, 0, "compatible",
"renesas,r8a77990"); "renesas,r8a77990");
break; break;
case RCAR_PRODUCT_D3: case PRR_PRODUCT_D3:
ret = fdt_appendprop_string(fdt, 0, "compatible", ret = fdt_appendprop_string(fdt, 0, "compatible",
"renesas,r8a77995"); "renesas,r8a77995");
break; break;
@ -572,7 +572,7 @@ static void bl2_advertise_dram_size(uint32_t product)
}; };
switch (product) { switch (product) {
case RCAR_PRODUCT_H3: case PRR_PRODUCT_H3:
#if (RCAR_DRAM_LPDDR4_MEMCONF == 0) #if (RCAR_DRAM_LPDDR4_MEMCONF == 0)
/* 4GB(1GBx4) */ /* 4GB(1GBx4) */
dram_config[1] = 0x40000000ULL; dram_config[1] = 0x40000000ULL;
@ -594,7 +594,7 @@ static void bl2_advertise_dram_size(uint32_t product)
#endif /* RCAR_DRAM_LPDDR4_MEMCONF == 0 */ #endif /* RCAR_DRAM_LPDDR4_MEMCONF == 0 */
break; break;
case RCAR_PRODUCT_M3: case PRR_PRODUCT_M3:
#if (RCAR_GEN3_ULCB == 1) #if (RCAR_GEN3_ULCB == 1)
/* 2GB(1GBx2 2ch split) */ /* 2GB(1GBx2 2ch split) */
dram_config[1] = 0x40000000ULL; dram_config[1] = 0x40000000ULL;
@ -606,17 +606,17 @@ static void bl2_advertise_dram_size(uint32_t product)
#endif #endif
break; break;
case RCAR_PRODUCT_M3N: case PRR_PRODUCT_M3N:
/* 2GB(1GBx2) */ /* 2GB(1GBx2) */
dram_config[1] = 0x80000000ULL; dram_config[1] = 0x80000000ULL;
break; break;
case RCAR_PRODUCT_V3M: case PRR_PRODUCT_V3M:
/* 1GB(512MBx2) */ /* 1GB(512MBx2) */
dram_config[1] = 0x40000000ULL; dram_config[1] = 0x40000000ULL;
break; break;
case RCAR_PRODUCT_E3: case PRR_PRODUCT_E3:
#if (RCAR_DRAM_DDR3L_MEMCONF == 0) #if (RCAR_DRAM_DDR3L_MEMCONF == 0)
/* 1GB(512MBx2) */ /* 1GB(512MBx2) */
dram_config[1] = 0x40000000ULL; dram_config[1] = 0x40000000ULL;
@ -629,7 +629,7 @@ static void bl2_advertise_dram_size(uint32_t product)
#endif /* RCAR_DRAM_DDR3L_MEMCONF == 0 */ #endif /* RCAR_DRAM_DDR3L_MEMCONF == 0 */
break; break;
case RCAR_PRODUCT_D3: case PRR_PRODUCT_D3:
/* 512MB */ /* 512MB */
dram_config[1] = 0x20000000ULL; dram_config[1] = 0x20000000ULL;
break; break;
@ -716,26 +716,26 @@ void bl2_el3_early_platform_setup(u_register_t arg1, u_register_t arg2,
version_of_renesas); version_of_renesas);
reg = mmio_read_32(RCAR_PRR); reg = mmio_read_32(RCAR_PRR);
product_cut = reg & (RCAR_PRODUCT_MASK | RCAR_CUT_MASK); product_cut = reg & (PRR_PRODUCT_MASK | PRR_CUT_MASK);
product = reg & RCAR_PRODUCT_MASK; product = reg & PRR_PRODUCT_MASK;
switch (product) { switch (product) {
case RCAR_PRODUCT_H3: case PRR_PRODUCT_H3:
str = product_h3; str = product_h3;
break; break;
case RCAR_PRODUCT_M3: case PRR_PRODUCT_M3:
str = product_m3; str = product_m3;
break; break;
case RCAR_PRODUCT_M3N: case PRR_PRODUCT_M3N:
str = product_m3n; str = product_m3n;
break; break;
case RCAR_PRODUCT_V3M: case PRR_PRODUCT_V3M:
str = product_v3m; str = product_v3m;
break; break;
case RCAR_PRODUCT_E3: case PRR_PRODUCT_E3:
str = product_e3; str = product_e3;
break; break;
case RCAR_PRODUCT_D3: case PRR_PRODUCT_D3:
str = product_d3; str = product_d3;
break; break;
default: default:
@ -743,9 +743,9 @@ void bl2_el3_early_platform_setup(u_register_t arg1, u_register_t arg2,
break; break;
} }
if ((RCAR_PRODUCT_M3 == product) && if ((PRR_PRODUCT_M3 == product) &&
(RCAR_CUT_VER20 == (reg & RCAR_MAJOR_MASK))) { (PRR_PRODUCT_20 == (reg & RCAR_MAJOR_MASK))) {
if (RCAR_M3_CUT_VER11 == (reg & RCAR_CUT_MASK)) { if (RCAR_M3_CUT_VER11 == (reg & PRR_CUT_MASK)) {
/* M3 Ver.1.1 or Ver.1.2 */ /* M3 Ver.1.1 or Ver.1.2 */
NOTICE("BL2: PRR is R-Car %s Ver.1.1 / Ver.1.2\n", NOTICE("BL2: PRR is R-Car %s Ver.1.1 / Ver.1.2\n",
str); str);
@ -761,7 +761,7 @@ void bl2_el3_early_platform_setup(u_register_t arg1, u_register_t arg2,
NOTICE("BL2: PRR is R-Car %s Ver.%d.%d\n", str, major, minor); NOTICE("BL2: PRR is R-Car %s Ver.%d.%d\n", str, major, minor);
} }
if (product == RCAR_PRODUCT_E3) { if (product == PRR_PRODUCT_E3) {
reg = mmio_read_32(RCAR_MODEMR); reg = mmio_read_32(RCAR_MODEMR);
sscg = reg & RCAR_SSCG_MASK; sscg = reg & RCAR_SSCG_MASK;
str = sscg == RCAR_SSCG_ENABLE ? sscg_on : sscg_off; str = sscg == RCAR_SSCG_ENABLE ? sscg_on : sscg_off;
@ -930,7 +930,7 @@ lcm_state:
mmio_write_32(CPG_CA53DBGRCR, mmio_write_32(CPG_CA53DBGRCR,
DBGCPUPREN | mmio_read_32(CPG_CA53DBGRCR)); DBGCPUPREN | mmio_read_32(CPG_CA53DBGRCR));
if (product_cut == RCAR_PRODUCT_H3_CUT10) { if (product_cut == PRR_PRODUCT_H3_CUT10) {
reg = mmio_read_32(CPG_PLL2CR); reg = mmio_read_32(CPG_PLL2CR);
reg &= ~((uint32_t) 1 << 5); reg &= ~((uint32_t) 1 << 5);
mmio_write_32(CPG_PLL2CR, reg); mmio_write_32(CPG_PLL2CR, reg);
@ -1016,7 +1016,7 @@ static void bl2_init_generic_timer(void)
/* Set frequency data in CNTFID0 */ /* Set frequency data in CNTFID0 */
reg_cntfid = pll_table[modemr_pll >> MODEMR_BOOT_PLL_SHIFT]; reg_cntfid = pll_table[modemr_pll >> MODEMR_BOOT_PLL_SHIFT];
reg = mmio_read_32(RCAR_PRR) & (RCAR_PRODUCT_MASK | RCAR_CUT_MASK); reg = mmio_read_32(RCAR_PRR) & (PRR_PRODUCT_MASK | PRR_CUT_MASK);
switch (modemr_pll) { switch (modemr_pll) {
case MD14_MD13_TYPE_0: case MD14_MD13_TYPE_0:
rcar_get_board_type(&board_type, &board_rev); rcar_get_board_type(&board_type, &board_rev);
@ -1025,7 +1025,7 @@ static void bl2_init_generic_timer(void)
} }
break; break;
case MD14_MD13_TYPE_3: case MD14_MD13_TYPE_3:
if (RCAR_PRODUCT_H3_CUT10 == reg) { if (PRR_PRODUCT_H3_CUT10 == reg) {
reg_cntfid = reg_cntfid >> 1U; reg_cntfid = reg_cntfid >> 1U;
} }
break; break;

4
plat/renesas/rcar/bl31_plat_setup.c
View File

@ -44,9 +44,9 @@ void plat_cci_init(void)
{ {
uint32_t prd; uint32_t prd;
prd = mmio_read_32(RCAR_PRR) & (RCAR_PRODUCT_MASK | RCAR_CUT_MASK); prd = mmio_read_32(RCAR_PRR) & (PRR_PRODUCT_MASK | PRR_CUT_MASK);
if (RCAR_PRODUCT_H3_CUT10 == prd || RCAR_PRODUCT_H3_CUT11 == prd) { if (PRR_PRODUCT_H3_CUT10 == prd || PRR_PRODUCT_H3_CUT11 == prd) {
cci_map[0U] = CCI500_CLUSTER0_SL_IFACE_IX; cci_map[0U] = CCI500_CLUSTER0_SL_IFACE_IX;
cci_map[1U] = CCI500_CLUSTER1_SL_IFACE_IX; cci_map[1U] = CCI500_CLUSTER1_SL_IFACE_IX;
} }

24
plat/renesas/rcar/include/rcar_def.h
View File

@ -147,31 +147,19 @@
#define RCAR_SYSCISCR U(0xE6180008) /* Interrupt stat clear */ #define RCAR_SYSCISCR U(0xE6180008) /* Interrupt stat clear */
/* Product register */ /* Product register */
#define RCAR_PRR U(0xFFF00044) #define RCAR_PRR U(0xFFF00044)
#define RCAR_PRODUCT_MASK U(0x00007F00)
#define RCAR_CUT_MASK U(0x000000FF)
#define RCAR_PRODUCT_H3 U(0x00004F00)
#define RCAR_PRODUCT_M3 U(0x00005200)
#define RCAR_PRODUCT_V3M U(0x00005400)
#define RCAR_PRODUCT_M3N U(0x00005500)
#define RCAR_PRODUCT_E3 U(0x00005700)
#define RCAR_PRODUCT_D3 U(0x00005800)
#define RCAR_CUT_VER10 U(0x00000000)
#define RCAR_CUT_VER11 U(0x00000001) /* H3/M3N/E3 Ver.1.1 */
#define RCAR_M3_CUT_VER11 U(0x00000010) /* M3 Ver.1.1/Ver.1.2 */ #define RCAR_M3_CUT_VER11 U(0x00000010) /* M3 Ver.1.1/Ver.1.2 */
#define RCAR_CUT_VER20 U(0x00000010)
#define RCAR_CUT_VER30 U(0x00000020)
#define RCAR_MAJOR_MASK U(0x000000F0) #define RCAR_MAJOR_MASK U(0x000000F0)
#define RCAR_MINOR_MASK U(0x0000000F) #define RCAR_MINOR_MASK U(0x0000000F)
#define RCAR_PRODUCT_SHIFT U(8) #define PRR_PRODUCT_SHIFT U(8)
#define RCAR_MAJOR_SHIFT U(4) #define RCAR_MAJOR_SHIFT U(4)
#define RCAR_MINOR_SHIFT U(0) #define RCAR_MINOR_SHIFT U(0)
#define RCAR_MAJOR_OFFSET U(1) #define RCAR_MAJOR_OFFSET U(1)
#define RCAR_M3_MINOR_OFFSET U(2) #define RCAR_M3_MINOR_OFFSET U(2)
#define RCAR_PRODUCT_H3_CUT10 (RCAR_PRODUCT_H3 | U(0x00)) /* 1.0 */ #define PRR_PRODUCT_H3_CUT10 (PRR_PRODUCT_H3 | U(0x00)) /* 1.0 */
#define RCAR_PRODUCT_H3_CUT11 (RCAR_PRODUCT_H3 | U(0x01)) /* 1.1 */ #define PRR_PRODUCT_H3_CUT11 (PRR_PRODUCT_H3 | U(0x01)) /* 1.1 */
#define RCAR_PRODUCT_H3_CUT20 (RCAR_PRODUCT_H3 | U(0x10)) /* 2.0 */ #define PRR_PRODUCT_H3_CUT20 (PRR_PRODUCT_H3 | U(0x10)) /* 2.0 */
#define RCAR_PRODUCT_M3_CUT10 (RCAR_PRODUCT_M3 | U(0x00)) /* 1.0 */ #define PRR_PRODUCT_M3_CUT10 (PRR_PRODUCT_M3 | U(0x00)) /* 1.0 */
#define RCAR_PRODUCT_M3_CUT11 (RCAR_PRODUCT_M3 | U(0x10)) #define PRR_PRODUCT_M3_CUT11 (PRR_PRODUCT_M3 | U(0x10))
#define PRR 0xFFF00044U #define PRR 0xFFF00044U
#define PRR_PRODUCT_MASK 0x00007F00U #define PRR_PRODUCT_MASK 0x00007F00U
#define PRR_CUT_MASK 0x000000FFU #define PRR_CUT_MASK 0x000000FFU