andrius
/
arm-trusted-firmware
1
0
Fork 0
Code Issues Pull Requests Releases Wiki Activity

Tegra: print GICC registers conditionally 

The GICC interface exists only on the interrupt controllers following
the GICv2 specification.

This patch prints the GICC register contents from the platform's macro,
plat_crash_print_regs' only when TEGRA_GICC_BASE is defined. This
allows platforms using future versions of the GIC specification to
still use this macro.

Change-Id: Ia5762d0a1ae28c832664d69362a7776e46a22ad1
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
This commit is contained in:
Varun Wadekar 2019-10-04 11:40:56 -07:00 committed by Manish Pandey
parent 601e3ed209
commit 7cd336ab9f
1 changed files with 3 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
plat/nvidia/tegra/include/plat_macros.S
View File

@ -1,5 +1,6 @@
/*
* Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2015-2020, NVIDIA Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -27,6 +28,7 @@ spacer:
* ---------------------------------------------
*/
.macro plat_crash_print_regs
#ifdef TEGRA_GICC_BASE
mov_imm x16, TEGRA_GICC_BASE
/* gicc base address is now in x16 */
@ -37,7 +39,7 @@ spacer:
ldr w10, [x16, #GICC_CTLR]
/* Store to the crash buf and print to cosole */
bl str_in_crash_buf_print
#endif
/* Print the GICD_ISPENDR regs */
mov_imm x16, TEGRA_GICD_BASE
add x7, x16, #GICD_ISPENDR