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Initial platform port for MediaTek mt8173 

- Boot up 4 cores.
- Add a generic UART driver.
- Add generic CPU helper functions
- Supoort suspend
- Add system_off & system_reset implementation
- Add crash console reporting implementation
- Add get_sys_suspend_power_state() for PSCI 1.0 SYSTEM_SUSPEND
- Add Mediatek SIP runtime service
- Add delay timer platform implementation

Change-Id: I44138249f115ee10b9cbd26fdbc2dd3af04d825f
Signed-off-by: CC Ma <cc.ma@mediatek.com>
Signed-off-by: Jimmy Huang <jimmy.huang@mediatek.com>
This commit is contained in:
CC Ma 2015-04-13 14:47:57 +08:00 committed by Yidi Lin
parent 6b0d97b24a
commit 7d116dccab
40 changed files with 5507 additions and 0 deletions
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113
plat/mediatek/common/mtk_sip_svc.c Normal file
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/*
* Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* Neither the name of ARM nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#include <assert.h>
#include <debug.h>
#include <mtk_sip_svc.h>
#include <runtime_svc.h>
#include <uuid.h>
/* Mediatek SiP Service UUID */
DEFINE_SVC_UUID(mtk_sip_svc_uid,
0xf7582ba4, 0x4262, 0x4d7d, 0x80, 0xe5,
0x8f, 0x95, 0x05, 0x00, 0x0f, 0x3d);
/*
* This function handles Mediatek defined SiP Calls */
static uint64_t mediatek_sip_handler(uint32_t smc_fid,
uint64_t x1,
uint64_t x2,
uint64_t x3,
uint64_t x4,
void *cookie,
void *handle)
{
uint64_t ret;
switch (smc_fid) {
case MTK_SIP_SET_AUTHORIZED_SECURE_REG:
ret = mt_sip_set_authorized_sreg((uint32_t)x1, (uint32_t)x2);
SMC_RET1(handle, ret);
default:
ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid);
break;
}
SMC_RET1(handle, SMC_UNK);
}
/*
* This function is responsible for handling all SiP calls from the NS world
*/
uint64_t sip_smc_handler(uint32_t smc_fid,
uint64_t x1,
uint64_t x2,
uint64_t x3,
uint64_t x4,
void *cookie,
void *handle,
uint64_t flags)
{
uint32_t ns;
/* Determine which security state this SMC originated from */
ns = is_caller_non_secure(flags);
if (!ns)
SMC_RET1(handle, SMC_UNK);
switch (smc_fid) {
case SIP_SVC_CALL_COUNT:
/* Return the number of Mediatek SiP Service Calls. */
SMC_RET1(handle, MTK_SIP_NUM_CALLS);
case SIP_SVC_UID:
/* Return UID to the caller */
SMC_UUID_RET(handle, mtk_sip_svc_uid);
case SIP_SVC_VERSION:
/* Return the version of current implementation */
SMC_RET2(handle, MTK_SIP_SVC_VERSION_MAJOR,
MTK_SIP_SVC_VERSION_MINOR);
default:
return mediatek_sip_handler(smc_fid, x1, x2, x3, x4,
cookie, handle);
}
}
/* Define a runtime service descriptor for fast SMC calls */
DECLARE_RT_SVC(
mediatek_sip_svc,
OEN_SIP_START,
OEN_SIP_END,
SMC_TYPE_FAST,
NULL,
sip_smc_handler
);

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/*
* Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* Neither the name of ARM nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __PLAT_SIP_SVC_H__
#define __PLAT_SIP_SVC_H__
#include <stdint.h>
/* SMC function IDs for SiP Service queries */
#define SIP_SVC_CALL_COUNT 0x8200ff00
#define SIP_SVC_UID 0x8200ff01
/* 0x8200ff02 is reserved */
#define SIP_SVC_VERSION 0x8200ff03
/* Mediatek SiP Service Calls version numbers */
#define MTK_SIP_SVC_VERSION_MAJOR 0x0
#define MTK_SIP_SVC_VERSION_MINOR 0x1
/* Number of Mediatek SiP Calls implemented */
#define MTK_SIP_NUM_CALLS 1
/* Mediatek SiP Service Calls function IDs */
#define MTK_SIP_SET_AUTHORIZED_SECURE_REG 0x82000001
/* Mediatek SiP Calls error code */
enum {
MTK_SIP_E_SUCCESS = 0,
MTK_SIP_E_INVALID_PARAM = -1
};
/*
* This function should be implemented in Mediatek SOC directory. It fullfills
* MTK_SIP_SET_AUTHORIZED_SECURE_REG SiP call by checking the sreg with the
* predefined secure register list, if a match was found, set val to sreg.
*
* Return MTK_SIP_E_SUCCESS on success, and MTK_SIP_E_INVALID_PARAM on failure.
*/
uint64_t mt_sip_set_authorized_sreg(uint32_t sreg, uint32_t val);
#endif /* __PLAT_SIP_SVC_H__ */

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/*
* Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* Neither the name of ARM nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#include <arch.h>
#include <asm_macros.S>
#include <mt8173_def.h>
.globl plat_secondary_cold_boot_setup
.globl plat_report_exception
.globl platform_is_primary_cpu
.globl plat_crash_console_init
.globl plat_crash_console_putc
/* -----------------------------------------------------
* void plat_secondary_cold_boot_setup (void);
*
* This function performs any platform specific actions
* needed for a secondary cpu after a cold reset e.g
* mark the cpu's presence, mechanism to place it in a
* holding pen etc.
* -----------------------------------------------------
*/
func plat_secondary_cold_boot_setup
/* MT8173 Oak does not do cold boot for secondary CPU */
cb_panic:
b cb_panic
endfunc plat_secondary_cold_boot_setup
func platform_is_primary_cpu
and x0, x0, #(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)
cmp x0, #MT8173_PRIMARY_CPU
cset x0, eq
ret
endfunc platform_is_primary_cpu
/* ---------------------------------------------
* int plat_crash_console_init(void)
* Function to initialize the crash console
* without a C Runtime to print crash report.
* Clobber list : x0, x1, x2
* ---------------------------------------------
*/
func plat_crash_console_init
mov_imm x0, MT8173_UART0_BASE
mov_imm x1, MT8173_UART_CLOCK
mov_imm x2, MT8173_BAUDRATE
b console_core_init
endfunc plat_crash_console_init
/* ---------------------------------------------
* int plat_crash_console_putc(void)
* Function to print a character on the crash
* console without a C Runtime.
* Clobber list : x1, x2
* ---------------------------------------------
*/
func plat_crash_console_putc
mov_imm x1, MT8173_UART0_BASE
b console_core_putc
endfunc plat_crash_console_putc

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/*
* Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* Neither the name of ARM nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#include <arch_helpers.h>
#include <arm_gic.h>
#include <bl_common.h>
#include <cci.h>
#include <debug.h>
#include <mt8173_def.h>
#include <platform_def.h>
#include <xlat_tables.h>
static const int cci_map[] = {
PLAT_MT_CCI_CLUSTER0_SL_IFACE_IX,
PLAT_MT_CCI_CLUSTER1_SL_IFACE_IX
};
/* Table of regions to map using the MMU. */
const mmap_region_t plat_mmap[] = {
/* for TF text, RO, RW */
MAP_REGION_FLAT(TZRAM_BASE, TZRAM_SIZE + TZRAM2_SIZE,
MT_MEMORY | MT_RW | MT_SECURE),
MAP_REGION_FLAT(MTK_DEV_RNG0_BASE, MTK_DEV_RNG0_SIZE,
MT_DEVICE | MT_RW | MT_SECURE),
MAP_REGION_FLAT(MTK_DEV_RNG1_BASE, MTK_DEV_RNG1_SIZE,
MT_DEVICE | MT_RW | MT_SECURE),
{ 0 }
};
/*******************************************************************************
* Macro generating the code for the function setting up the pagetables as per
* the platform memory map & initialize the mmu, for the given exception level
******************************************************************************/
#define DEFINE_CONFIGURE_MMU_EL(_el) \
void plat_configure_mmu_el ## _el(unsigned long total_base, \
unsigned long total_size, \
unsigned long ro_start, \
unsigned long ro_limit, \
unsigned long coh_start, \
unsigned long coh_limit) \
{ \
mmap_add_region(total_base, total_base, \
total_size, \
MT_MEMORY | MT_RW | MT_SECURE); \
mmap_add_region(ro_start, ro_start, \
ro_limit - ro_start, \
MT_MEMORY | MT_RO | MT_SECURE); \
mmap_add_region(coh_start, coh_start, \
coh_limit - coh_start, \
MT_DEVICE | MT_RW | MT_SECURE); \
mmap_add(plat_mmap); \
init_xlat_tables(); \
\
enable_mmu_el ## _el(0); \
}
/* Define EL3 variants of the function initialising the MMU */
DEFINE_CONFIGURE_MMU_EL(3)
uint64_t plat_get_syscnt_freq(void)
{
return SYS_COUNTER_FREQ_IN_TICKS;
}
void plat_cci_init(void)
{
/* Initialize CCI driver */
cci_init(PLAT_MT_CCI_BASE, cci_map, ARRAY_SIZE(cci_map));
}
void plat_cci_enable(void)
{
/*
* Enable CCI coherency for this cluster.
* No need for locks as no other cpu is active at the moment.
*/
cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr()));
}
void plat_cci_disable(void)
{
cci_disable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr()));
}

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/*
* Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* Neither the name of ARM nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#include <arm_gic.h>
#include <assert.h>
#include <bl_common.h>
#include <console.h>
#include <debug.h>
#include <mcucfg.h>
#include <mmio.h>
#include <mtcmos.h>
#include <plat_private.h>
#include <platform.h>
#include <spm.h>
/*******************************************************************************
* Declarations of linker defined symbols which will help us find the layout
* of trusted SRAM
******************************************************************************/
unsigned long __RO_START__;
unsigned long __RO_END__;
unsigned long __COHERENT_RAM_START__;
unsigned long __COHERENT_RAM_END__;
/*
* The next 2 constants identify the extents of the code & RO data region.
* These addresses are used by the MMU setup code and therefore they must be
* page-aligned. It is the responsibility of the linker script to ensure that
* __RO_START__ and __RO_END__ linker symbols refer to page-aligned addresses.
*/
#define BL31_RO_BASE (unsigned long)(&__RO_START__)
#define BL31_RO_LIMIT (unsigned long)(&__RO_END__)
/*
* The next 2 constants identify the extents of the coherent memory region.
* These addresses are used by the MMU setup code and therefore they must be
* page-aligned. It is the responsibility of the linker script to ensure that
* __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols
* refer to page-aligned addresses.
*/
#define BL31_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__)
#define BL31_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__)
static entry_point_info_t bl32_ep_info;
static entry_point_info_t bl33_ep_info;
static void platform_setup_cpu(void)
{
/* turn off all the little core's power except cpu 0 */
mtcmos_little_cpu_off();
/* setup big cores */
mmio_write_32((uintptr_t)&mt8173_mcucfg->mp1_config_res,
MP1_DIS_RGU0_WAIT_PD_CPUS_L1_ACK |
MP1_DIS_RGU1_WAIT_PD_CPUS_L1_ACK |
MP1_DIS_RGU2_WAIT_PD_CPUS_L1_ACK |
MP1_DIS_RGU3_WAIT_PD_CPUS_L1_ACK |
MP1_DIS_RGU_NOCPU_WAIT_PD_CPUS_L1_ACK);
mmio_setbits_32((uintptr_t)&mt8173_mcucfg->mp1_miscdbg, MP1_AINACTS);
mmio_setbits_32((uintptr_t)&mt8173_mcucfg->mp1_clkenm_div,
MP1_SW_CG_GEN);
mmio_clrbits_32((uintptr_t)&mt8173_mcucfg->mp1_rst_ctl,
MP1_L2RSTDISABLE);
/* set big cores arm64 boot mode */
mmio_setbits_32((uintptr_t)&mt8173_mcucfg->mp1_cpucfg,
MP1_CPUCFG_64BIT);
/* set LITTLE cores arm64 boot mode */
mmio_setbits_32((uintptr_t)&mt8173_mcucfg->mp0_rv_addr[0].rv_addr_hw,
MP0_CPUCFG_64BIT);
}
/*******************************************************************************
* Return a pointer to the 'entry_point_info' structure of the next image for
* the security state specified. BL33 corresponds to the non-secure image type
* while BL32 corresponds to the secure image type. A NULL pointer is returned
* if the image does not exist.
******************************************************************************/
entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type)
{
entry_point_info_t *next_image_info;
next_image_info = (type == NON_SECURE) ? &bl33_ep_info : &bl32_ep_info;
/* None of the images on this platform can have 0x0 as the entrypoint */
if (next_image_info->pc)
return next_image_info;
else
return NULL;
}
/*******************************************************************************
* Perform any BL3-1 early platform setup. Here is an opportunity to copy
* parameters passed by the calling EL (S-EL1 in BL2 & S-EL3 in BL1) before they
* are lost (potentially). This needs to be done before the MMU is initialized
* so that the memory layout can be used while creating page tables.
* BL2 has flushed this information to memory, so we are guaranteed to pick up
* good data.
******************************************************************************/
void bl31_early_platform_setup(bl31_params_t *from_bl2,
void *plat_params_from_bl2)
{
console_init(MT8173_UART0_BASE, MT8173_UART_CLOCK, MT8173_BAUDRATE);
VERBOSE("bl31_setup\n");
assert(from_bl2 != NULL);
assert(from_bl2->h.type == PARAM_BL31);
assert(from_bl2->h.version >= VERSION_1);
assert(((unsigned long)plat_params_from_bl2) == MT_BL31_PLAT_PARAM_VAL);
bl32_ep_info = *from_bl2->bl32_ep_info;
bl33_ep_info = *from_bl2->bl33_ep_info;
}
/*******************************************************************************
* Perform any BL3-1 platform setup code
******************************************************************************/
void bl31_platform_setup(void)
{
platform_setup_cpu();
plat_delay_timer_init();
/* Initialize the gic cpu and distributor interfaces */
plat_mt_gic_init();
arm_gic_setup();
/* Topologies are best known to the platform. */
mt_setup_topology();
/* Initialize spm at boot time */
spm_boot_init();
}
/*******************************************************************************
* Perform the very early platform specific architectural setup here. At the
* moment this is only intializes the mmu in a quick and dirty way.
******************************************************************************/
void bl31_plat_arch_setup(void)
{
plat_cci_init();
plat_cci_enable();
plat_configure_mmu_el3(BL31_RO_BASE,
(BL31_COHERENT_RAM_LIMIT - BL31_RO_BASE),
BL31_RO_BASE,
BL31_RO_LIMIT,
BL31_COHERENT_RAM_BASE,
BL31_COHERENT_RAM_LIMIT);
}

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/*
* Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* Neither the name of ARM nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#include <debug.h>
#include <gpio.h>
#include <mmio.h>
#include <mt8173_def.h>
#include <pmic_wrap_init.h>
enum {
MAX_GPIO_REG_BITS = 16,
};
struct mt_gpio_obj {
struct gpio_regs *reg;
};
static struct mt_gpio_obj gpio_dat = {
.reg = (struct gpio_regs *)(GPIO_BASE),
};
static struct mt_gpio_obj *gpio_obj = &gpio_dat;
struct mt_gpioext_obj {
struct gpioext_regs *reg;
};
static struct mt_gpioext_obj gpioext_dat = {
.reg = (struct gpioext_regs *)(GPIOEXT_BASE),
};
static struct mt_gpioext_obj *gpioext_obj = &gpioext_dat;
static inline struct mt_gpio_obj *mt_get_gpio_obj(void)
{
return gpio_obj;
}
static inline struct mt_gpioext_obj *mt_get_gpioext_obj(void)
{
return gpioext_obj;
}
enum {
GPIO_PRO_DIR = 0,
GPIO_PRO_DOUT,
GPIO_PRO_DIN,
GPIO_PRO_PULLEN,
GPIO_PRO_PULLSEL,
GPIO_PRO_MODE,
GPIO_PRO_MAX,
};
static inline int32_t gpioext_write(uint16_t *addr, int64_t data)
{
return pwrap_write((uint32_t)(uintptr_t)addr, data);
}
static inline int32_t gpioext_set_bits(uint32_t bit, uint16_t *reg)
{
return gpioext_write(reg, bit);
}
static int32_t mt_set_gpio_chip(uint32_t pin, uint32_t property, uint32_t val)
{
uint32_t pos = 0;
uint32_t bit = 0;
struct mt_gpio_obj *obj = mt_get_gpio_obj();
uint16_t *reg;
uint32_t data = 0;
if (!obj)
return -ERACCESS;
if (pin >= GPIO_EXTEND_START)
return -ERINVAL;
if (property >= GPIO_PRO_MAX)
return -ERINVAL;
pos = pin / MAX_GPIO_REG_BITS;
bit = pin % MAX_GPIO_REG_BITS;
data = 1L << bit;
switch (property) {
case GPIO_PRO_DIR:
if (val == GPIO_DIR_IN)
reg = &obj->reg->dir[pos].rst;
else
reg = &obj->reg->dir[pos].set;
break;
case GPIO_PRO_DOUT:
if (val == GPIO_OUT_ZERO)
reg = &obj->reg->dout[pos].rst;
else
reg = &obj->reg->dout[pos].set;
break;
default:
return -ERINVAL;
}
mmio_write_16((uintptr_t)reg, data);
return RSUCCESS;
}
static int32_t mt_set_gpio_ext(uint32_t pin, uint32_t property, uint32_t val)
{
uint32_t pos = 0;
uint32_t bit = 0;
struct mt_gpioext_obj *obj = mt_get_gpioext_obj();
uint16_t *reg;
uint32_t data = 0;
int ret = 0;
if (!obj)
return -ERACCESS;
if (pin >= MAX_GPIO_PIN)
return -ERINVAL;
if (property >= GPIO_PRO_MAX)
return -ERINVAL;
pin -= GPIO_EXTEND_START;
pos = pin / MAX_GPIO_REG_BITS;
bit = pin % MAX_GPIO_REG_BITS;
switch (property) {
case GPIO_PRO_DIR:
if (val == GPIO_DIR_IN)
reg = &obj->reg->dir[pos].rst;
else
reg = &obj->reg->dir[pos].set;
break;
case GPIO_PRO_DOUT:
if (val == GPIO_OUT_ZERO)
reg = &obj->reg->dout[pos].rst;
else
reg = &obj->reg->dout[pos].set;
break;
default:
return -ERINVAL;
}
data = (1L << bit);
ret = gpioext_set_bits(data, reg);
return ret ? -ERWRAPPER : RSUCCESS;
}
static void mt_gpio_pin_decrypt(uint32_t *cipher)
{
if ((*cipher & (0x80000000)) == 0)
INFO("Pin %u decrypt warning!\n", *cipher);
*cipher &= ~(0x80000000);
}
int32_t mt_set_gpio_out(uint32_t pin, uint32_t output)
{
uint32_t gp = GPIO_PRO_DOUT;
mt_gpio_pin_decrypt(&pin);
return (pin >= GPIO_EXTEND_START) ?
mt_set_gpio_ext(pin, gp, output) :
mt_set_gpio_chip(pin, gp, output);
}
void gpio_set(uint32_t gpio, int32_t value)
{
mt_set_gpio_out(gpio, value);
}

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/*
* Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* Neither the name of ARM nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __PLAT_DRIVER_GPIO_H__
#define __PLAT_DRIVER_GPIO_H__
#include <stdint.h>
enum {
GPIOEXT_BASE = 0xC000,
};
/* Error Code No. */
enum {
RSUCCESS = 0,
ERACCESS,
ERINVAL,
ERWRAPPER,
};
enum {
GPIO_UNSUPPORTED = -1,
GPIO0, GPIO1, GPIO2, GPIO3, GPIO4, GPIO5, GPIO6, GPIO7,
GPIO8, GPIO9, GPIO10, GPIO11, GPIO12, GPIO13, GPIO14, GPIO15,
GPIO16, GPIO17, GPIO18, GPIO19, GPIO20, GPIO21, GPIO22, GPIO23,
GPIO24, GPIO25, GPIO26, GPIO27, GPIO28, GPIO29, GPIO30, GPIO31,
GPIO32, GPIO33, GPIO34, GPIO35, GPIO36, GPIO37, GPIO38, GPIO39,
GPIO40, GPIO41, GPIO42, GPIO43, GPIO44, GPIO45, GPIO46, GPIO47,
GPIO48, GPIO49, GPIO50, GPIO51, GPIO52, GPIO53, GPIO54, GPIO55,
GPIO56, GPIO57, GPIO58, GPIO59, GPIO60, GPIO61, GPIO62, GPIO63,
GPIO64, GPIO65, GPIO66, GPIO67, GPIO68, GPIO69, GPIO70, GPIO71,
GPIO72, GPIO73, GPIO74, GPIO75, GPIO76, GPIO77, GPIO78, GPIO79,
GPIO80, GPIO81, GPIO82, GPIO83, GPIO84, GPIO85, GPIO86, GPIO87,
GPIO88, GPIO89, GPIO90, GPIO91, GPIO92, GPIO93, GPIO94, GPIO95,
GPIO96, GPIO97, GPIO98, GPIO99, GPIO100, GPIO101, GPIO102, GPIO103,
GPIO104, GPIO105, GPIO106, GPIO107, GPIO108, GPIO109, GPIO110, GPIO111,
GPIO112, GPIO113, GPIO114, GPIO115, GPIO116, GPIO117, GPIO118, GPIO119,
GPIO120, GPIO121, GPIO122, GPIO123, GPIO124, GPIO125, GPIO126, GPIO127,
GPIO128, GPIO129, GPIO130, GPIO131, GPIO132, GPIO133, GPIO134,
GPIOEXT0, GPIOEXT1, GPIOEXT2, GPIOEXT3, GPIOEXT4, GPIOEXT5,
GPIOEXT6, GPIOEXT7, GPIOEXT8, GPIOEXT9, GPIOEXT10, GPIOEXT11,
GPIOEXT12, GPIOEXT13, GPIOEXT14, GPIOEXT15, GPIOEXT16, GPIOEXT17,
GPIOEXT18, GPIOEXT19, GPIOEXT20, GPIOEXT21, GPIOEXT22, GPIOEXT23,
GPIOEXT24, GPIOEXT25, GPIOEXT26, GPIOEXT27, GPIOEXT28, GPIOEXT29,
GPIOEXT30, GPIOEXT31, GPIOEXT32, GPIOEXT33, GPIOEXT34, GPIOEXT35,
GPIOEXT36, GPIOEXT37, GPIOEXT38, GPIOEXT39, GPIOEXT40,
GPIO_MAX
};
#define MAX_GPIO_PIN GPIO_MAX
#define GPIO_EXTEND_START GPIOEXT0
/* GPIO DIRECTION */
enum {
GPIO_DIR_UNSUPPORTED = -1,
GPIO_DIR_IN = 0,
GPIO_DIR_OUT = 1,
GPIO_DIR_MAX,
GPIO_DIR_DEFAULT = GPIO_DIR_IN,
};
/* GPIO OUTPUT */
enum {
GPIO_OUT_UNSUPPORTED = -1,
GPIO_OUT_ZERO = 0,
GPIO_OUT_ONE = 1,
GPIO_OUT_MAX,
GPIO_OUT_DEFAULT = GPIO_OUT_ZERO,
GPIO_DATA_OUT_DEFAULT = GPIO_OUT_ZERO, /* compatible with DCT */
};
struct val_regs {
uint16_t val;
uint16_t _align1;
uint16_t set;
uint16_t _align2;
uint16_t rst;
uint16_t _align3[3];
};
struct gpio_regs {
struct val_regs dir[9]; /* 0x0000 ~ 0x008F: 144 bytes */
uint8_t rsv00[112]; /* 0x0090 ~ 0x00FF: 112 bytes */
struct val_regs pullen[9]; /* 0x0100 ~ 0x018F: 144 bytes */
uint8_t rsv01[112]; /* 0x0190 ~ 0x01FF: 112 bytes */
struct val_regs pullsel[9]; /* 0x0200 ~ 0x028F: 144 bytes */
uint8_t rsv02[112]; /* 0x0290 ~ 0x02FF: 112 bytes */
uint8_t rsv03[256]; /* 0x0300 ~ 0x03FF: 256 bytes */
struct val_regs dout[9]; /* 0x0400 ~ 0x048F: 144 bytes */
uint8_t rsv04[112]; /* 0x0490 ~ 0x04FF: 112 bytes */
struct val_regs din[9]; /* 0x0500 ~ 0x058F: 114 bytes */
uint8_t rsv05[112]; /* 0x0590 ~ 0x05FF: 112 bytes */
struct val_regs mode[27]; /* 0x0600 ~ 0x07AF: 432 bytes */
uint8_t rsv06[336]; /* 0x07B0 ~ 0x08FF: 336 bytes */
struct val_regs ies[3]; /* 0x0900 ~ 0x092F: 48 bytes */
struct val_regs smt[3]; /* 0x0930 ~ 0x095F: 48 bytes */
uint8_t rsv07[160]; /* 0x0960 ~ 0x09FF: 160 bytes */
struct val_regs tdsel[8]; /* 0x0A00 ~ 0x0A7F: 128 bytes */
struct val_regs rdsel[6]; /* 0x0A80 ~ 0x0ADF: 96 bytes */
uint8_t rsv08[32]; /* 0x0AE0 ~ 0x0AFF: 32 bytes */
struct val_regs drv_mode[10]; /* 0x0B00 ~ 0x0B9F: 160 bytes */
uint8_t rsv09[96]; /* 0x0BA0 ~ 0x0BFF: 96 bytes */
struct val_regs msdc0_ctrl0; /* 0x0C00 ~ 0x0C0F: 16 bytes */
struct val_regs msdc0_ctrl1; /* 0x0C10 ~ 0x0C1F: 16 bytes */
struct val_regs msdc0_ctrl2; /* 0x0C20 ~ 0x0C2F: 16 bytes */
struct val_regs msdc0_ctrl5; /* 0x0C30 ~ 0x0C3F: 16 bytes */
struct val_regs msdc1_ctrl0; /* 0x0C40 ~ 0x0C4F: 16 bytes */
struct val_regs msdc1_ctrl1; /* 0x0C50 ~ 0x0C5F: 16 bytes */
struct val_regs msdc1_ctrl2; /* 0x0C60 ~ 0x0C6F: 16 bytes */
struct val_regs msdc1_ctrl5; /* 0x0C70 ~ 0x0C7F: 16 bytes */
struct val_regs msdc2_ctrl0; /* 0x0C80 ~ 0x0C8F: 16 bytes */
struct val_regs msdc2_ctrl1; /* 0x0C90 ~ 0x0C9F: 16 bytes */
struct val_regs msdc2_ctrl2; /* 0x0CA0 ~ 0x0CAF: 16 bytes */
struct val_regs msdc2_ctrl5; /* 0x0CB0 ~ 0x0CBF: 16 bytes */
struct val_regs msdc3_ctrl0; /* 0x0CC0 ~ 0x0CCF: 16 bytes */
struct val_regs msdc3_ctrl1; /* 0x0CD0 ~ 0x0CDF: 16 bytes */
struct val_regs msdc3_ctrl2; /* 0x0CE0 ~ 0x0CEF: 16 bytes */
struct val_regs msdc3_ctrl5; /* 0x0CF0 ~ 0x0CFF: 16 bytes */
struct val_regs msdc0_ctrl3; /* 0x0D00 ~ 0x0D0F: 16 bytes */
struct val_regs msdc0_ctrl4; /* 0x0D10 ~ 0x0D1F: 16 bytes */
struct val_regs msdc1_ctrl3; /* 0x0D20 ~ 0x0D2F: 16 bytes */
struct val_regs msdc1_ctrl4; /* 0x0D30 ~ 0x0D3F: 16 bytes */
struct val_regs msdc2_ctrl3; /* 0x0D40 ~ 0x0D4F: 16 bytes */
struct val_regs msdc2_ctrl4; /* 0x0D50 ~ 0x0D5F: 16 bytes */
struct val_regs msdc3_ctrl3; /* 0x0D60 ~ 0x0D6F: 16 bytes */
struct val_regs msdc3_ctrl4; /* 0x0D70 ~ 0x0D7F: 16 bytes */
uint8_t rsv10[64]; /* 0x0D80 ~ 0x0DBF: 64 bytes */
struct val_regs exmd_ctrl[1]; /* 0x0DC0 ~ 0x0DCF: 16 bytes */
uint8_t rsv11[48]; /* 0x0DD0 ~ 0x0DFF: 48 bytes */
struct val_regs kpad_ctrl[2]; /* 0x0E00 ~ 0x0E1F: 32 bytes */
struct val_regs hsic_ctrl[4]; /* 0x0E20 ~ 0x0E5F: 64 bytes */
};
struct ext_val_regs {
uint16_t val;
uint16_t set;
uint16_t rst;
uint16_t _align;
};
struct gpioext_regs {
struct ext_val_regs dir[4]; /* 0x0000 ~ 0x001F: 32 bytes */
struct ext_val_regs pullen[4]; /* 0x0020 ~ 0x003F: 32 bytes */
struct ext_val_regs pullsel[4]; /* 0x0040 ~ 0x005F: 32 bytes */
struct ext_val_regs dinv[4]; /* 0x0060 ~ 0x007F: 32 bytes */
struct ext_val_regs dout[4]; /* 0x0080 ~ 0x009F: 32 bytes */
struct ext_val_regs din[4]; /* 0x00A0 ~ 0x00BF: 32 bytes */
struct ext_val_regs mode[10]; /* 0x00C0 ~ 0x010F: 80 bytes */
};
/* GPIO Driver interface */
void gpio_set(uint32_t gpio, int32_t value);
#endif /* __PLAT_DRIVER_GPIO_H__ */

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/*
* Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* Neither the name of ARM nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#include <mmio.h>
#include <mt8173_def.h>
#include <mtcmos.h>
#include <spm.h>
enum {
SRAM_ISOINT_B = 1U << 6,
SRAM_CKISO = 1U << 5,
PWR_CLK_DIS = 1U << 4,
PWR_ON_2ND = 1U << 3,
PWR_ON = 1U << 2,
PWR_ISO = 1U << 1,
PWR_RST_B = 1U << 0
};
enum {
L1_PDN_ACK = 1U << 8,
L1_PDN = 1U << 0
};
enum {
LITTLE_CPU3 = 1U << 12,
LITTLE_CPU2 = 1U << 11,
LITTLE_CPU1 = 1U << 10,
};
enum {
SRAM_PDN = 0xf << 8,
DIS_SRAM_ACK = 0x1 << 12,
AUD_SRAM_ACK = 0xf << 12,
};
enum {
DIS_PWR_STA_MASK = 0x1 << 3,
AUD_PWR_STA_MASK = 0x1 << 24,
};
static void mtcmos_ctrl_little_off(unsigned int linear_id)
{
uint32_t reg_pwr_con;
uint32_t reg_l1_pdn;
uint32_t bit_cpu;
switch (linear_id) {
case 1:
reg_pwr_con = SPM_CA7_CPU1_PWR_CON;
reg_l1_pdn = SPM_CA7_CPU1_L1_PDN;
bit_cpu = LITTLE_CPU1;
break;
case 2:
reg_pwr_con = SPM_CA7_CPU2_PWR_CON;
reg_l1_pdn = SPM_CA7_CPU2_L1_PDN;
bit_cpu = LITTLE_CPU2;
break;
case 3:
reg_pwr_con = SPM_CA7_CPU3_PWR_CON;
reg_l1_pdn = SPM_CA7_CPU3_L1_PDN;
bit_cpu = LITTLE_CPU3;
break;
default:
/* should never come to here */
return;
}
/* enable register control */
mmio_write_32(SPM_POWERON_CONFIG_SET,
(SPM_PROJECT_CODE << 16) | (1U << 0));
mmio_setbits_32(reg_pwr_con, PWR_ISO);
mmio_setbits_32(reg_pwr_con, SRAM_CKISO);
mmio_clrbits_32(reg_pwr_con, SRAM_ISOINT_B);
mmio_setbits_32(reg_l1_pdn, L1_PDN);
while (!(mmio_read_32(reg_l1_pdn) & L1_PDN_ACK))
continue;
mmio_clrbits_32(reg_pwr_con, PWR_RST_B);
mmio_setbits_32(reg_pwr_con, PWR_CLK_DIS);
mmio_clrbits_32(reg_pwr_con, PWR_ON);
mmio_clrbits_32(reg_pwr_con, PWR_ON_2ND);
while ((mmio_read_32(SPM_PWR_STATUS) & bit_cpu) ||
(mmio_read_32(SPM_PWR_STATUS_2ND) & bit_cpu))
continue;
}
void mtcmos_little_cpu_off(void)
{
/* turn off little cpu 1 - 3 */
mtcmos_ctrl_little_off(1);
mtcmos_ctrl_little_off(2);
mtcmos_ctrl_little_off(3);
}

41
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/*
* Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* Neither the name of ARM nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __MTCMOS_H__
#define __MTCMOS_H__
/*
* This function will turn off all the little core's power except cpu 0. The
* cores in cluster 0 are all powered when the system power on. The System
* Power Manager (SPM) will do nothing if it found the core's power was on
* during CPU_ON psci call.
*/
void mtcmos_little_cpu_off(void);
#endif /* __MTCMOS_H__ */

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/*
* Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* Neither the name of ARM nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#include <debug.h>
#include <delay_timer.h>
#include <mmio.h>
#include <mt8173_def.h>
#include <pmic_wrap_init.h>
/* pmic wrap module wait_idle and read polling interval (in microseconds) */
enum {
WAIT_IDLE_POLLING_DELAY_US = 1,
READ_POLLING_DELAY_US = 2
};
static inline uint32_t wait_for_state_idle(uint32_t timeout_us,
void *wacs_register,
void *wacs_vldclr_register,
uint32_t *read_reg)
{
uint32_t reg_rdata;
uint32_t retry;
retry = (timeout_us + WAIT_IDLE_POLLING_DELAY_US) /
WAIT_IDLE_POLLING_DELAY_US;
do {
udelay(WAIT_IDLE_POLLING_DELAY_US);
reg_rdata = mmio_read_32((uintptr_t)wacs_register);
/* if last read command timeout,clear vldclr bit
read command state machine:FSM_REQ-->wfdle-->WFVLDCLR;
write:FSM_REQ-->idle */
switch (((reg_rdata >> RDATA_WACS_FSM_SHIFT) &
RDATA_WACS_FSM_MASK)) {
case WACS_FSM_WFVLDCLR:
mmio_write_32((uintptr_t)wacs_vldclr_register, 1);
ERROR("WACS_FSM = PMIC_WRAP_WACS_VLDCLR\n");
break;
case WACS_FSM_WFDLE:
ERROR("WACS_FSM = WACS_FSM_WFDLE\n");
break;
case WACS_FSM_REQ:
ERROR("WACS_FSM = WACS_FSM_REQ\n");
break;
case WACS_FSM_IDLE:
goto done;
default:
break;
}
retry--;
} while (retry);
done:
if (!retry) /* timeout */
return E_PWR_WAIT_IDLE_TIMEOUT;
if (read_reg)
*read_reg = reg_rdata;
return 0;
}
static inline uint32_t wait_for_state_ready(uint32_t timeout_us,
void *wacs_register,
uint32_t *read_reg)
{
uint32_t reg_rdata;
uint32_t retry;
retry = (timeout_us + READ_POLLING_DELAY_US) / READ_POLLING_DELAY_US;
do {
udelay(READ_POLLING_DELAY_US);
reg_rdata = mmio_read_32((uintptr_t)wacs_register);
if (((reg_rdata >> RDATA_WACS_FSM_SHIFT) & RDATA_WACS_FSM_MASK)
== WACS_FSM_WFVLDCLR)
break;
retry--;
} while (retry);
if (!retry) { /* timeout */
ERROR("timeout when waiting for idle\n");
return E_PWR_WAIT_IDLE_TIMEOUT_READ;
}
if (read_reg)
*read_reg = reg_rdata;
return 0;
}
static int32_t pwrap_wacs2(uint32_t write,
uint32_t adr,
uint32_t wdata,
uint32_t *rdata,
uint32_t init_check)
{
uint32_t reg_rdata = 0;
uint32_t wacs_write = 0;
uint32_t wacs_adr = 0;
uint32_t wacs_cmd = 0;
uint32_t return_value = 0;
if (init_check) {
reg_rdata = mmio_read_32((uintptr_t)&mt8173_pwrap->wacs2_rdata);
/* Prevent someone to used pwrap before pwrap init */
if (((reg_rdata >> RDATA_INIT_DONE_SHIFT) &
RDATA_INIT_DONE_MASK) != WACS_INIT_DONE) {
ERROR("initialization isn't finished\n");
return E_PWR_NOT_INIT_DONE;
}
}
reg_rdata = 0;
/* Check IDLE in advance */
return_value = wait_for_state_idle(TIMEOUT_WAIT_IDLE,
&mt8173_pwrap->wacs2_rdata,
&mt8173_pwrap->wacs2_vldclr,
0);
if (return_value != 0) {
ERROR("wait_for_fsm_idle fail,return_value=%d\n", return_value);
goto FAIL;
}
wacs_write = write << 31;
wacs_adr = (adr >> 1) << 16;
wacs_cmd = wacs_write | wacs_adr | wdata;
mmio_write_32((uintptr_t)&mt8173_pwrap->wacs2_cmd, wacs_cmd);
if (write == 0) {
if (NULL == rdata) {
ERROR("rdata is a NULL pointer\n");
return_value = E_PWR_INVALID_ARG;
goto FAIL;
}
return_value = wait_for_state_ready(TIMEOUT_READ,
&mt8173_pwrap->wacs2_rdata,
&reg_rdata);
if (return_value != 0) {
ERROR("wait_for_fsm_vldclr fail,return_value=%d\n",
return_value);
goto FAIL;
}
*rdata = ((reg_rdata >> RDATA_WACS_RDATA_SHIFT)
& RDATA_WACS_RDATA_MASK);
mmio_write_32((uintptr_t)&mt8173_pwrap->wacs2_vldclr, 1);
}
FAIL:
return return_value;
}
/* external API for pmic_wrap user */
int32_t pwrap_read(uint32_t adr, uint32_t *rdata)
{
return pwrap_wacs2(0, adr, 0, rdata, 1);
}
int32_t pwrap_write(uint32_t adr, uint32_t wdata)
{
return pwrap_wacs2(1, adr, wdata, 0, 1);
}

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/*
* Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* Neither the name of ARM nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __PMIC_WRAP_INIT_H__
#define __PMIC_WRAP_INIT_H__
/* external API */
int32_t pwrap_read(uint32_t adr, uint32_t *rdata);
int32_t pwrap_write(uint32_t adr, uint32_t wdata);
static struct mt8173_pmic_wrap_regs *const mt8173_pwrap =
(void *)PMIC_WRAP_BASE;
/* timeout setting */
enum {
TIMEOUT_RESET = 50, /* us */
TIMEOUT_READ = 50, /* us */
TIMEOUT_WAIT_IDLE = 50 /* us */
};
/* PMIC_WRAP registers */
struct mt8173_pmic_wrap_regs {
uint32_t mux_sel;
uint32_t wrap_en;
uint32_t dio_en;
uint32_t sidly;
uint32_t rddmy;
uint32_t si_ck_con;
uint32_t cshext_write;
uint32_t cshext_read;
uint32_t cslext_start;
uint32_t cslext_end;
uint32_t staupd_prd;
uint32_t staupd_grpen;
uint32_t reserved[4];
uint32_t staupd_man_trig;
uint32_t staupd_sta;
uint32_t wrap_sta;
uint32_t harb_init;
uint32_t harb_hprio;
uint32_t hiprio_arb_en;
uint32_t harb_sta0;
uint32_t harb_sta1;
uint32_t man_en;
uint32_t man_cmd;
uint32_t man_rdata;
uint32_t man_vldclr;
uint32_t wacs0_en;
uint32_t init_done0;
uint32_t wacs0_cmd;
uint32_t wacs0_rdata;
uint32_t wacs0_vldclr;
uint32_t wacs1_en;
uint32_t init_done1;
uint32_t wacs1_cmd;
uint32_t wacs1_rdata;
uint32_t wacs1_vldclr;
uint32_t wacs2_en;
uint32_t init_done2;
uint32_t wacs2_cmd;
uint32_t wacs2_rdata;
uint32_t wacs2_vldclr;
uint32_t int_en;
uint32_t int_flg_raw;
uint32_t int_flg;
uint32_t int_clr;
uint32_t sig_adr;
uint32_t sig_mode;
uint32_t sig_value;
uint32_t sig_errval;
uint32_t crc_en;
uint32_t timer_en;
uint32_t timer_sta;
uint32_t wdt_unit;
uint32_t wdt_src_en;
uint32_t wdt_flg;
uint32_t debug_int_sel;
uint32_t dvfs_adr0;
uint32_t dvfs_wdata0;
uint32_t dvfs_adr1;
uint32_t dvfs_wdata1;
uint32_t dvfs_adr2;
uint32_t dvfs_wdata2;
uint32_t dvfs_adr3;
uint32_t dvfs_wdata3;
uint32_t dvfs_adr4;
uint32_t dvfs_wdata4;
uint32_t dvfs_adr5;
uint32_t dvfs_wdata5;
uint32_t dvfs_adr6;
uint32_t dvfs_wdata6;
uint32_t dvfs_adr7;
uint32_t dvfs_wdata7;
uint32_t spminf_sta;
uint32_t cipher_key_sel;
uint32_t cipher_iv_sel;
uint32_t cipher_en;
uint32_t cipher_rdy;
uint32_t cipher_mode;
uint32_t cipher_swrst;
uint32_t dcm_en;
uint32_t dcm_dbc_prd;
};
enum {
RDATA_WACS_RDATA_SHIFT = 0,
RDATA_WACS_FSM_SHIFT = 16,
RDATA_WACS_REQ_SHIFT = 19,
RDATA_SYNC_IDLE_SHIFT,
RDATA_INIT_DONE_SHIFT,
RDATA_SYS_IDLE_SHIFT,
};
enum {
RDATA_WACS_RDATA_MASK = 0xffff,
RDATA_WACS_FSM_MASK = 0x7,
RDATA_WACS_REQ_MASK = 0x1,
RDATA_SYNC_IDLE_MASK = 0x1,
RDATA_INIT_DONE_MASK = 0x1,
RDATA_SYS_IDLE_MASK = 0x1,
};
/* WACS_FSM */
enum {
WACS_FSM_IDLE = 0x00,
WACS_FSM_REQ = 0x02,
WACS_FSM_WFDLE = 0x04,
WACS_FSM_WFVLDCLR = 0x06,
WACS_INIT_DONE = 0x01,
WACS_SYNC_IDLE = 0x01,
WACS_SYNC_BUSY = 0x00
};
/* error information flag */
enum {
E_PWR_INVALID_ARG = 1,
E_PWR_INVALID_RW = 2,
E_PWR_INVALID_ADDR = 3,
E_PWR_INVALID_WDAT = 4,
E_PWR_INVALID_OP_MANUAL = 5,
E_PWR_NOT_IDLE_STATE = 6,
E_PWR_NOT_INIT_DONE = 7,
E_PWR_NOT_INIT_DONE_READ = 8,
E_PWR_WAIT_IDLE_TIMEOUT = 9,
E_PWR_WAIT_IDLE_TIMEOUT_READ = 10,
E_PWR_INIT_SIDLY_FAIL = 11,
E_PWR_RESET_TIMEOUT = 12,
E_PWR_TIMEOUT = 13,
E_PWR_INIT_RESET_SPI = 20,
E_PWR_INIT_SIDLY = 21,
E_PWR_INIT_REG_CLOCK = 22,
E_PWR_INIT_ENABLE_PMIC = 23,
E_PWR_INIT_DIO = 24,
E_PWR_INIT_CIPHER = 25,
E_PWR_INIT_WRITE_TEST = 26,
E_PWR_INIT_ENABLE_CRC = 27,
E_PWR_INIT_ENABLE_DEWRAP = 28,
E_PWR_INIT_ENABLE_EVENT = 29,
E_PWR_READ_TEST_FAIL = 30,
E_PWR_WRITE_TEST_FAIL = 31,
E_PWR_SWITCH_DIO = 32
};
#endif /* __PMIC_WRAP_INIT_H__ */

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/*
* Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* Neither the name of ARM nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#include <assert.h>
#include <debug.h>
#include <delay_timer.h>
#include <mt8173_def.h>
#include <pmic_wrap_init.h>
#include <rtc.h>
/* RTC busy status polling interval and retry count */
enum {
RTC_WRTGR_POLLING_DELAY_MS = 10,
RTC_WRTGR_POLLING_CNT = 100
};
static uint16_t RTC_Read(uint32_t addr)
{
uint32_t rdata = 0;
pwrap_read((uint32_t)addr, &rdata);
return (uint16_t)rdata;
}
static void RTC_Write(uint32_t addr, uint16_t data)
{
pwrap_write((uint32_t)addr, (uint32_t)data);
}
static inline int32_t rtc_busy_wait(void)
{
uint64_t retry = RTC_WRTGR_POLLING_CNT;
do {
mdelay(RTC_WRTGR_POLLING_DELAY_MS);
if (!(RTC_Read(RTC_BBPU) & RTC_BBPU_CBUSY))
return 1;
retry--;
} while (retry);
ERROR("[RTC] rtc cbusy time out!\n");
return 0;
}
static int32_t Write_trigger(void)
{
RTC_Write(RTC_WRTGR, 1);
return rtc_busy_wait();
}
static int32_t Writeif_unlock(void)
{
RTC_Write(RTC_PROT, RTC_PROT_UNLOCK1);
if (!Write_trigger())
return 0;
RTC_Write(RTC_PROT, RTC_PROT_UNLOCK2);
if (!Write_trigger())
return 0;
return 1;
}
void rtc_bbpu_power_down(void)
{
uint16_t bbpu;
/* pull PWRBB low */
bbpu = RTC_BBPU_KEY | RTC_BBPU_AUTO | RTC_BBPU_PWREN;
if (Writeif_unlock()) {
RTC_Write(RTC_BBPU, bbpu);
if (!Write_trigger())
assert(1);
} else {
assert(1);
}
}

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/*
* Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* Neither the name of ARM nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __PLAT_DRIVER_RTC_H__
#define __PLAT_DRIVER_RTC_H__
/* RTC registers */
enum {
RTC_BBPU = 0xE000,
RTC_IRQ_STA = 0xE002,
RTC_IRQ_EN = 0xE004,
RTC_CII_EN = 0xE006
};
enum {
RTC_OSC32CON = 0xE026,
RTC_CON = 0xE03E,
RTC_WRTGR = 0xE03C
};
enum {
RTC_PDN1 = 0xE02C,
RTC_PDN2 = 0xE02E,
RTC_SPAR0 = 0xE030,
RTC_SPAR1 = 0xE032,
RTC_PROT = 0xE036,
RTC_DIFF = 0xE038,
RTC_CALI = 0xE03A
};
enum {
RTC_PROT_UNLOCK1 = 0x586A,
RTC_PROT_UNLOCK2 = 0x9136
};
enum {
RTC_BBPU_PWREN = 1U << 0,
RTC_BBPU_BBPU = 1U << 2,
RTC_BBPU_AUTO = 1U << 3,
RTC_BBPU_CLRPKY = 1U << 4,
RTC_BBPU_RELOAD = 1U << 5,
RTC_BBPU_CBUSY = 1U << 6
};
enum {
RTC_BBPU_KEY = 0x43 << 8
};
void rtc_bbpu_power_down(void);
#endif /* __PLAT_DRIVER_RTC_H__ */

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/*
* Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* Neither the name of ARM nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#include <bakery_lock.h>
#include <debug.h>
#include <mmio.h>
#include <mt8173_def.h>
#include <spm.h>
#include <spm_suspend.h>
/*
* System Power Manager (SPM) is a hardware module, which controls cpu or
* system power for different power scenarios using different firmware, i.e.,
* - spm_hotplug.c for cpu power control in cpu hotplug flow.
* - spm_mcdi.c for cpu power control in cpu idle power saving state.
* - spm_suspend.c for system power control in system suspend scenario.
*
* This file provide utility functions common to hotplug, mcdi(idle), suspend
* power scenarios. A bakery lock (software lock) is incoporated to protect
* certain critical sections to avoid kicking different SPM firmware
* concurrently.
*/
#define SPM_SYSCLK_SETTLE 128 /* 3.9ms */
#if DEBUG
static int spm_dormant_sta = CPU_DORMANT_RESET;
#endif
static bakery_lock_t spm_lock __attribute__ ((section("tzfw_coherent_mem")));
static int spm_hotplug_ready __attribute__ ((section("tzfw_coherent_mem")));
static int spm_mcdi_ready __attribute__ ((section("tzfw_coherent_mem")));
static int spm_suspend_ready __attribute__ ((section("tzfw_coherent_mem")));
void spm_lock_init(void)
{
bakery_lock_init(&spm_lock);
}
void spm_lock_get(void)
{
bakery_lock_get(&spm_lock);
}
void spm_lock_release(void)
{
bakery_lock_release(&spm_lock);
}
int is_mcdi_ready(void)
{
return spm_mcdi_ready;
}
int is_hotplug_ready(void)
{
return spm_hotplug_ready;
}
int is_suspend_ready(void)
{
return spm_suspend_ready;
}
void set_mcdi_ready(void)
{
spm_mcdi_ready = 1;
spm_hotplug_ready = 0;
spm_suspend_ready = 0;
}
void set_hotplug_ready(void)
{
spm_mcdi_ready = 0;
spm_hotplug_ready = 1;
spm_suspend_ready = 0;
}
void set_suspend_ready(void)
{
spm_mcdi_ready = 0;
spm_hotplug_ready = 0;
spm_suspend_ready = 1;
}
void clear_all_ready(void)
{
spm_mcdi_ready = 0;
spm_hotplug_ready = 0;
spm_suspend_ready = 0;
}
void spm_register_init(void)
{
mmio_write_32(SPM_POWERON_CONFIG_SET, SPM_REGWR_CFG_KEY | SPM_REGWR_EN);
mmio_write_32(SPM_POWER_ON_VAL0, 0);
mmio_write_32(SPM_POWER_ON_VAL1, POWER_ON_VAL1_DEF);
mmio_write_32(SPM_PCM_PWR_IO_EN, 0);
mmio_write_32(SPM_PCM_CON0, CON0_CFG_KEY | CON0_PCM_SW_RESET);
mmio_write_32(SPM_PCM_CON0, CON0_CFG_KEY);
if (mmio_read_32(SPM_PCM_FSM_STA) != PCM_FSM_STA_DEF)
WARN("PCM reset failed\n");
mmio_write_32(SPM_PCM_CON0, CON0_CFG_KEY | CON0_IM_SLEEP_DVS);
mmio_write_32(SPM_PCM_CON1, CON1_CFG_KEY | CON1_EVENT_LOCK_EN |
CON1_SPM_SRAM_ISO_B | CON1_SPM_SRAM_SLP_B | CON1_MIF_APBEN);
mmio_write_32(SPM_PCM_IM_PTR, 0);
mmio_write_32(SPM_PCM_IM_LEN, 0);
mmio_write_32(SPM_CLK_CON, CC_SYSCLK0_EN_1 | CC_SYSCLK0_EN_0 |
CC_SYSCLK1_EN_0 | CC_SRCLKENA_MASK_0 | CC_CLKSQ1_SEL |
CC_CXO32K_RM_EN_MD2 | CC_CXO32K_RM_EN_MD1 | CC_MD32_DCM_EN);
mmio_write_32(SPM_SLEEP_ISR_MASK, 0xff0c);
mmio_write_32(SPM_SLEEP_ISR_STATUS, 0xc);
mmio_write_32(SPM_PCM_SW_INT_CLEAR, 0xff);
mmio_write_32(SPM_MD32_SRAM_CON, 0xff0);
}
void spm_reset_and_init_pcm(void)
{
unsigned int con1;
int i = 0;
mmio_write_32(SPM_PCM_CON0, CON0_CFG_KEY | CON0_PCM_SW_RESET);
mmio_write_32(SPM_PCM_CON0, CON0_CFG_KEY);
while (mmio_read_32(SPM_PCM_FSM_STA) != PCM_FSM_STA_DEF) {
i++;
if (i > 1000) {
i = 0;
WARN("PCM reset failed\n");
break;
}
}
mmio_write_32(SPM_PCM_CON0, CON0_CFG_KEY | CON0_IM_SLEEP_DVS);
con1 = mmio_read_32(SPM_PCM_CON1) &
(CON1_PCM_WDT_WAKE_MODE | CON1_PCM_WDT_EN);
mmio_write_32(SPM_PCM_CON1, con1 | CON1_CFG_KEY | CON1_EVENT_LOCK_EN |
CON1_SPM_SRAM_ISO_B | CON1_SPM_SRAM_SLP_B |
CON1_IM_NONRP_EN | CON1_MIF_APBEN);
}
void spm_init_pcm_register(void)
{
mmio_write_32(SPM_PCM_REG_DATA_INI, mmio_read_32(SPM_POWER_ON_VAL0));
mmio_write_32(SPM_PCM_PWR_IO_EN, PCM_RF_SYNC_R0);
mmio_write_32(SPM_PCM_PWR_IO_EN, 0);
mmio_write_32(SPM_PCM_REG_DATA_INI, mmio_read_32(SPM_POWER_ON_VAL1));
mmio_write_32(SPM_PCM_PWR_IO_EN, PCM_RF_SYNC_R7);
mmio_write_32(SPM_PCM_PWR_IO_EN, 0);
}
void spm_set_power_control(const struct pwr_ctrl *pwrctrl)
{
mmio_write_32(SPM_AP_STANBY_CON, (!pwrctrl->md32_req_mask << 21) |
(!pwrctrl->mfg_req_mask << 17) |
(!pwrctrl->disp_req_mask << 16) |
(!!pwrctrl->mcusys_idle_mask << 7) |
(!!pwrctrl->ca15top_idle_mask << 6) |
(!!pwrctrl->ca7top_idle_mask << 5) |
(!!pwrctrl->wfi_op << 4));
mmio_write_32(SPM_PCM_SRC_REQ, (!!pwrctrl->pcm_apsrc_req << 0));
mmio_write_32(SPM_PCM_PASR_DPD_2, 0);
mmio_clrsetbits_32(SPM_CLK_CON, CC_SRCLKENA_MASK_0,
(pwrctrl->srclkenai_mask ? CC_SRCLKENA_MASK_0 : 0));
mmio_write_32(SPM_SLEEP_CA15_WFI0_EN, !!pwrctrl->ca15_wfi0_en);
mmio_write_32(SPM_SLEEP_CA15_WFI1_EN, !!pwrctrl->ca15_wfi1_en);
mmio_write_32(SPM_SLEEP_CA15_WFI2_EN, !!pwrctrl->ca15_wfi2_en);
mmio_write_32(SPM_SLEEP_CA15_WFI3_EN, !!pwrctrl->ca15_wfi3_en);
mmio_write_32(SPM_SLEEP_CA7_WFI0_EN, !!pwrctrl->ca7_wfi0_en);
mmio_write_32(SPM_SLEEP_CA7_WFI1_EN, !!pwrctrl->ca7_wfi1_en);
mmio_write_32(SPM_SLEEP_CA7_WFI2_EN, !!pwrctrl->ca7_wfi2_en);
mmio_write_32(SPM_SLEEP_CA7_WFI3_EN, !!pwrctrl->ca7_wfi3_en);
}
void spm_set_wakeup_event(const struct pwr_ctrl *pwrctrl)
{
unsigned int val, mask;
if (pwrctrl->timer_val_cust == 0)
val = pwrctrl->timer_val ? pwrctrl->timer_val : PCM_TIMER_MAX;
else
val = pwrctrl->timer_val_cust;
mmio_write_32(SPM_PCM_TIMER_VAL, val);
mmio_setbits_32(SPM_PCM_CON1, CON1_CFG_KEY);
if (pwrctrl->wake_src_cust == 0)
mask = pwrctrl->wake_src;
else
mask = pwrctrl->wake_src_cust;
if (pwrctrl->syspwreq_mask)
mask &= ~WAKE_SRC_SYSPWREQ;
mmio_write_32(SPM_SLEEP_WAKEUP_EVENT_MASK, ~mask);
mmio_write_32(SPM_SLEEP_ISR_MASK, 0xfe04);
}
void spm_get_wakeup_status(struct wake_status *wakesta)
{
wakesta->assert_pc = mmio_read_32(SPM_PCM_REG_DATA_INI);
wakesta->r12 = mmio_read_32(SPM_PCM_REG12_DATA);
wakesta->raw_sta = mmio_read_32(SPM_SLEEP_ISR_RAW_STA);
wakesta->wake_misc = mmio_read_32(SPM_SLEEP_WAKEUP_MISC);
wakesta->timer_out = mmio_read_32(SPM_PCM_TIMER_OUT);
wakesta->r13 = mmio_read_32(SPM_PCM_REG13_DATA);
wakesta->idle_sta = mmio_read_32(SPM_SLEEP_SUBSYS_IDLE_STA);
wakesta->debug_flag = mmio_read_32(SPM_PCM_PASR_DPD_3);
wakesta->event_reg = mmio_read_32(SPM_PCM_EVENT_REG_STA);
wakesta->isr = mmio_read_32(SPM_SLEEP_ISR_STATUS);
}
void spm_init_event_vector(const struct pcm_desc *pcmdesc)
{
/* init event vector register */
mmio_write_32(SPM_PCM_EVENT_VECTOR0, pcmdesc->vec0);
mmio_write_32(SPM_PCM_EVENT_VECTOR1, pcmdesc->vec1);
mmio_write_32(SPM_PCM_EVENT_VECTOR2, pcmdesc->vec2);
mmio_write_32(SPM_PCM_EVENT_VECTOR3, pcmdesc->vec3);
mmio_write_32(SPM_PCM_EVENT_VECTOR4, pcmdesc->vec4);
mmio_write_32(SPM_PCM_EVENT_VECTOR5, pcmdesc->vec5);
mmio_write_32(SPM_PCM_EVENT_VECTOR6, pcmdesc->vec6);
mmio_write_32(SPM_PCM_EVENT_VECTOR7, pcmdesc->vec7);
/* event vector will be enabled by PCM itself */
}
void spm_kick_im_to_fetch(const struct pcm_desc *pcmdesc)
{
unsigned int ptr = 0, len, con0;
ptr = (unsigned int)(unsigned long)(pcmdesc->base);
len = pcmdesc->size - 1;
if (mmio_read_32(SPM_PCM_IM_PTR) != ptr ||
mmio_read_32(SPM_PCM_IM_LEN) != len ||
pcmdesc->sess > 2) {
mmio_write_32(SPM_PCM_IM_PTR, ptr);
mmio_write_32(SPM_PCM_IM_LEN, len);
} else {
mmio_setbits_32(SPM_PCM_CON1, CON1_CFG_KEY | CON1_IM_SLAVE);
}
/* kick IM to fetch (only toggle IM_KICK) */
con0 = mmio_read_32(SPM_PCM_CON0) & ~(CON0_IM_KICK | CON0_PCM_KICK);
mmio_write_32(SPM_PCM_CON0, con0 | CON0_CFG_KEY | CON0_IM_KICK);
mmio_write_32(SPM_PCM_CON0, con0 | CON0_CFG_KEY);
/* kick IM to fetch (only toggle PCM_KICK) */
con0 = mmio_read_32(SPM_PCM_CON0) & ~(CON0_IM_KICK | CON0_PCM_KICK);
mmio_write_32(SPM_PCM_CON0, con0 | CON0_CFG_KEY | CON0_PCM_KICK);
mmio_write_32(SPM_PCM_CON0, con0 | CON0_CFG_KEY);
}
void spm_set_sysclk_settle(void)
{
mmio_write_32(SPM_CLK_SETTLE, SPM_SYSCLK_SETTLE);
INFO("settle = %u\n", mmio_read_32(SPM_CLK_SETTLE));
}
void spm_kick_pcm_to_run(struct pwr_ctrl *pwrctrl)
{
unsigned int con1;
con1 = mmio_read_32(SPM_PCM_CON1) &
~(CON1_PCM_WDT_WAKE_MODE | CON1_PCM_WDT_EN);
mmio_write_32(SPM_PCM_CON1, CON1_CFG_KEY | con1);
if (mmio_read_32(SPM_PCM_TIMER_VAL) > PCM_TIMER_MAX)
mmio_write_32(SPM_PCM_TIMER_VAL, PCM_TIMER_MAX);
mmio_write_32(SPM_PCM_WDT_TIMER_VAL,
mmio_read_32(SPM_PCM_TIMER_VAL) + PCM_WDT_TIMEOUT);
mmio_write_32(SPM_PCM_CON1, con1 | CON1_CFG_KEY | CON1_PCM_WDT_EN);
mmio_write_32(SPM_PCM_PASR_DPD_0, 0);
mmio_write_32(SPM_PCM_MAS_PAUSE_MASK, 0xffffffff);
mmio_write_32(SPM_PCM_REG_DATA_INI, 0);
mmio_clrbits_32(SPM_CLK_CON, CC_DISABLE_DORM_PWR);
mmio_write_32(SPM_PCM_FLAGS, pwrctrl->pcm_flags);
mmio_clrsetbits_32(SPM_CLK_CON, CC_LOCK_INFRA_DCM,
(pwrctrl->infra_dcm_lock ? CC_LOCK_INFRA_DCM : 0));
mmio_write_32(SPM_PCM_PWR_IO_EN,
(pwrctrl->r0_ctrl_en ? PCM_PWRIO_EN_R0 : 0) |
(pwrctrl->r7_ctrl_en ? PCM_PWRIO_EN_R7 : 0));
}
void spm_clean_after_wakeup(void)
{
mmio_clrsetbits_32(SPM_PCM_CON1, CON1_PCM_WDT_EN, CON1_CFG_KEY);
mmio_write_32(SPM_PCM_PWR_IO_EN, 0);
mmio_write_32(SPM_SLEEP_CPU_WAKEUP_EVENT, 0);
mmio_clrsetbits_32(SPM_PCM_CON1, CON1_PCM_TIMER_EN, CON1_CFG_KEY);
mmio_write_32(SPM_SLEEP_WAKEUP_EVENT_MASK, ~0);
mmio_write_32(SPM_SLEEP_ISR_MASK, 0xFF0C);
mmio_write_32(SPM_SLEEP_ISR_STATUS, 0xC);
mmio_write_32(SPM_PCM_SW_INT_CLEAR, 0xFF);
}
enum wake_reason_t spm_output_wake_reason(struct wake_status *wakesta)
{
enum wake_reason_t wr;
int i;
wr = WR_UNKNOWN;
if (wakesta->assert_pc != 0) {
ERROR("PCM ASSERT AT %u, r12=0x%x, r13=0x%x, debug_flag=0x%x\n",
wakesta->assert_pc, wakesta->r12, wakesta->r13,
wakesta->debug_flag);
return WR_PCM_ASSERT;
}
if (wakesta->r12 & WAKE_SRC_SPM_MERGE) {
if (wakesta->wake_misc & WAKE_MISC_PCM_TIMER)
wr = WR_PCM_TIMER;
if (wakesta->wake_misc & WAKE_MISC_CPU_WAKE)
wr = WR_WAKE_SRC;
}
for (i = 1; i < 32; i++) {
if (wakesta->r12 & (1U << i))
wr = WR_WAKE_SRC;
}
if ((wakesta->event_reg & 0x100000) == 0) {
INFO("pcm sleep abort!\n");
wr = WR_PCM_ABORT;
}
INFO("timer_out = %u, r12 = 0x%x, r13 = 0x%x, debug_flag = 0x%x\n",
wakesta->timer_out, wakesta->r12, wakesta->r13,
wakesta->debug_flag);
INFO("raw_sta = 0x%x, idle_sta = 0x%x, event_reg = 0x%x, isr = 0x%x\n",
wakesta->raw_sta, wakesta->idle_sta, wakesta->event_reg,
wakesta->isr);
INFO("dormant state = %d\n", spm_dormant_sta);
return wr;
}
void spm_boot_init(void)
{
/* Only CPU0 is online during boot, initialize cpu online reserve bit */
mmio_write_32(SPM_PCM_RESERVE, 0xFE);
spm_lock_init();
spm_register_init();
}

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/*
* Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* Neither the name of ARM nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __SPM_H__
#define __SPM_H__
#define SPM_POWERON_CONFIG_SET (SPM_BASE + 0x000)
#define SPM_POWER_ON_VAL0 (SPM_BASE + 0x010)
#define SPM_POWER_ON_VAL1 (SPM_BASE + 0x014)
#define SPM_CLK_SETTLE (SPM_BASE + 0x100)
#define SPM_CA7_CPU1_PWR_CON (SPM_BASE + 0x218)
#define SPM_CA7_CPU2_PWR_CON (SPM_BASE + 0x21c)
#define SPM_CA7_CPU3_PWR_CON (SPM_BASE + 0x220)
#define SPM_CA7_CPU1_L1_PDN (SPM_BASE + 0x264)
#define SPM_CA7_CPU2_L1_PDN (SPM_BASE + 0x26c)
#define SPM_CA7_CPU3_L1_PDN (SPM_BASE + 0x274)
#define SPM_MD32_SRAM_CON (SPM_BASE + 0x2c8)
#define SPM_PCM_CON0 (SPM_BASE + 0x310)
#define SPM_PCM_CON1 (SPM_BASE + 0x314)
#define SPM_PCM_IM_PTR (SPM_BASE + 0x318)
#define SPM_PCM_IM_LEN (SPM_BASE + 0x31c)
#define SPM_PCM_REG_DATA_INI (SPM_BASE + 0x320)
#define SPM_PCM_EVENT_VECTOR0 (SPM_BASE + 0x340)
#define SPM_PCM_EVENT_VECTOR1 (SPM_BASE + 0x344)
#define SPM_PCM_EVENT_VECTOR2 (SPM_BASE + 0x348)
#define SPM_PCM_EVENT_VECTOR3 (SPM_BASE + 0x34c)
#define SPM_PCM_MAS_PAUSE_MASK (SPM_BASE + 0x354)
#define SPM_PCM_PWR_IO_EN (SPM_BASE + 0x358)
#define SPM_PCM_TIMER_VAL (SPM_BASE + 0x35c)
#define SPM_PCM_TIMER_OUT (SPM_BASE + 0x360)
#define SPM_PCM_REG0_DATA (SPM_BASE + 0x380)
#define SPM_PCM_REG1_DATA (SPM_BASE + 0x384)
#define SPM_PCM_REG2_DATA (SPM_BASE + 0x388)
#define SPM_PCM_REG3_DATA (SPM_BASE + 0x38c)
#define SPM_PCM_REG4_DATA (SPM_BASE + 0x390)
#define SPM_PCM_REG5_DATA (SPM_BASE + 0x394)
#define SPM_PCM_REG6_DATA (SPM_BASE + 0x398)
#define SPM_PCM_REG7_DATA (SPM_BASE + 0x39c)
#define SPM_PCM_REG8_DATA (SPM_BASE + 0x3a0)
#define SPM_PCM_REG9_DATA (SPM_BASE + 0x3a4)
#define SPM_PCM_REG10_DATA (SPM_BASE + 0x3a8)
#define SPM_PCM_REG11_DATA (SPM_BASE + 0x3ac)
#define SPM_PCM_REG12_DATA (SPM_BASE + 0x3b0)
#define SPM_PCM_REG13_DATA (SPM_BASE + 0x3b4)
#define SPM_PCM_REG14_DATA (SPM_BASE + 0x3b8)
#define SPM_PCM_REG15_DATA (SPM_BASE + 0x3bc)
#define SPM_PCM_EVENT_REG_STA (SPM_BASE + 0x3c0)
#define SPM_PCM_FSM_STA (SPM_BASE + 0x3c4)
#define SPM_PCM_IM_HOST_RW_PTR (SPM_BASE + 0x3c8)
#define SPM_PCM_IM_HOST_RW_DAT (SPM_BASE + 0x3cc)
#define SPM_PCM_EVENT_VECTOR4 (SPM_BASE + 0x3d0)
#define SPM_PCM_EVENT_VECTOR5 (SPM_BASE + 0x3d4)
#define SPM_PCM_EVENT_VECTOR6 (SPM_BASE + 0x3d8)
#define SPM_PCM_EVENT_VECTOR7 (SPM_BASE + 0x3dc)
#define SPM_PCM_SW_INT_SET (SPM_BASE + 0x3e0)
#define SPM_PCM_SW_INT_CLEAR (SPM_BASE + 0x3e4)
#define SPM_CLK_CON (SPM_BASE + 0x400)
#define SPM_SLEEP_PTPOD2_CON (SPM_BASE + 0x408)
#define SPM_APMCU_PWRCTL (SPM_BASE + 0x600)
#define SPM_AP_DVFS_CON_SET (SPM_BASE + 0x604)
#define SPM_AP_STANBY_CON (SPM_BASE + 0x608)
#define SPM_PWR_STATUS (SPM_BASE + 0x60c)
#define SPM_PWR_STATUS_2ND (SPM_BASE + 0x610)
#define SPM_AP_BSI_REQ (SPM_BASE + 0x614)
#define SPM_SLEEP_TIMER_STA (SPM_BASE + 0x720)
#define SPM_SLEEP_WAKEUP_EVENT_MASK (SPM_BASE + 0x810)
#define SPM_SLEEP_CPU_WAKEUP_EVENT (SPM_BASE + 0x814)
#define SPM_SLEEP_MD32_WAKEUP_EVENT_MASK (SPM_BASE + 0x818)
#define SPM_PCM_WDT_TIMER_VAL (SPM_BASE + 0x824)
#define SPM_PCM_WDT_TIMER_OUT (SPM_BASE + 0x828)
#define SPM_PCM_MD32_MAILBOX (SPM_BASE + 0x830)
#define SPM_PCM_MD32_IRQ (SPM_BASE + 0x834)
#define SPM_SLEEP_ISR_MASK (SPM_BASE + 0x900)
#define SPM_SLEEP_ISR_STATUS (SPM_BASE + 0x904)
#define SPM_SLEEP_ISR_RAW_STA (SPM_BASE + 0x910)
#define SPM_SLEEP_MD32_ISR_RAW_STA (SPM_BASE + 0x914)
#define SPM_SLEEP_WAKEUP_MISC (SPM_BASE + 0x918)
#define SPM_SLEEP_BUS_PROTECT_RDY (SPM_BASE + 0x91c)
#define SPM_SLEEP_SUBSYS_IDLE_STA (SPM_BASE + 0x920)
#define SPM_PCM_RESERVE (SPM_BASE + 0xb00)
#define SPM_PCM_RESERVE2 (SPM_BASE + 0xb04)
#define SPM_PCM_FLAGS (SPM_BASE + 0xb08)
#define SPM_PCM_SRC_REQ (SPM_BASE + 0xb0c)
#define SPM_PCM_DEBUG_CON (SPM_BASE + 0xb20)
#define SPM_CA7_CPU0_IRQ_MASK (SPM_BASE + 0xb30)
#define SPM_CA7_CPU1_IRQ_MASK (SPM_BASE + 0xb34)
#define SPM_CA7_CPU2_IRQ_MASK (SPM_BASE + 0xb38)
#define SPM_CA7_CPU3_IRQ_MASK (SPM_BASE + 0xb3c)
#define SPM_CA15_CPU0_IRQ_MASK (SPM_BASE + 0xb40)
#define SPM_CA15_CPU1_IRQ_MASK (SPM_BASE + 0xb44)
#define SPM_CA15_CPU2_IRQ_MASK (SPM_BASE + 0xb48)
#define SPM_CA15_CPU3_IRQ_MASK (SPM_BASE + 0xb4c)
#define SPM_PCM_PASR_DPD_0 (SPM_BASE + 0xb60)
#define SPM_PCM_PASR_DPD_1 (SPM_BASE + 0xb64)
#define SPM_PCM_PASR_DPD_2 (SPM_BASE + 0xb68)
#define SPM_PCM_PASR_DPD_3 (SPM_BASE + 0xb6c)
#define SPM_SLEEP_CA7_WFI0_EN (SPM_BASE + 0xf00)
#define SPM_SLEEP_CA7_WFI1_EN (SPM_BASE + 0xf04)
#define SPM_SLEEP_CA7_WFI2_EN (SPM_BASE + 0xf08)
#define SPM_SLEEP_CA7_WFI3_EN (SPM_BASE + 0xf0c)
#define SPM_SLEEP_CA15_WFI0_EN (SPM_BASE + 0xf10)
#define SPM_SLEEP_CA15_WFI1_EN (SPM_BASE + 0xf14)
#define SPM_SLEEP_CA15_WFI2_EN (SPM_BASE + 0xf18)
#define SPM_SLEEP_CA15_WFI3_EN (SPM_BASE + 0xf1c)
#define SPM_PROJECT_CODE 0xb16
#define SPM_REGWR_EN (1U << 0)
#define SPM_REGWR_CFG_KEY (SPM_PROJECT_CODE << 16)
#define SPM_CPU_PDN_DIS (1U << 0)
#define SPM_INFRA_PDN_DIS (1U << 1)
#define SPM_DDRPHY_PDN_DIS (1U << 2)
#define SPM_DUALVCORE_PDN_DIS (1U << 3)
#define SPM_PASR_DIS (1U << 4)
#define SPM_DPD_DIS (1U << 5)
#define SPM_SODI_DIS (1U << 6)
#define SPM_MEMPLL_RESET (1U << 7)
#define SPM_MAINPLL_PDN_DIS (1U << 8)
#define SPM_CPU_DVS_DIS (1U << 9)
#define SPM_CPU_DORMANT (1U << 10)
#define SPM_EXT_VSEL_GPIO103 (1U << 11)
#define SPM_DDR_HIGH_SPEED (1U << 12)
#define SPM_OPT (1U << 13)
#define POWER_ON_VAL1_DEF 0x01011820
#define PCM_FSM_STA_DEF 0x48490
#define PCM_END_FSM_STA_DEF 0x08490
#define PCM_END_FSM_STA_MASK 0x3fff0
#define PCM_HANDSHAKE_SEND1 0xbeefbeef
#define PCM_WDT_TIMEOUT (30 * 32768)
#define PCM_TIMER_MAX (0xffffffff - PCM_WDT_TIMEOUT)
#define CON0_PCM_KICK (1U << 0)
#define CON0_IM_KICK (1U << 1)
#define CON0_IM_SLEEP_DVS (1U << 3)
#define CON0_PCM_SW_RESET (1U << 15)
#define CON0_CFG_KEY (SPM_PROJECT_CODE << 16)
#define CON1_IM_SLAVE (1U << 0)
#define CON1_MIF_APBEN (1U << 3)
#define CON1_PCM_TIMER_EN (1U << 5)
#define CON1_IM_NONRP_EN (1U << 6)
#define CON1_PCM_WDT_EN (1U << 8)
#define CON1_PCM_WDT_WAKE_MODE (1U << 9)
#define CON1_SPM_SRAM_SLP_B (1U << 10)
#define CON1_SPM_SRAM_ISO_B (1U << 11)
#define CON1_EVENT_LOCK_EN (1U << 12)
#define CON1_CFG_KEY (SPM_PROJECT_CODE << 16)
#define PCM_PWRIO_EN_R0 (1U << 0)
#define PCM_PWRIO_EN_R7 (1U << 7)
#define PCM_RF_SYNC_R0 (1U << 16)
#define PCM_RF_SYNC_R2 (1U << 18)
#define PCM_RF_SYNC_R6 (1U << 22)
#define PCM_RF_SYNC_R7 (1U << 23)
#define CC_SYSCLK0_EN_0 (1U << 0)
#define CC_SYSCLK0_EN_1 (1U << 1)
#define CC_SYSCLK1_EN_0 (1U << 2)
#define CC_SYSCLK1_EN_1 (1U << 3)
#define CC_SYSSETTLE_SEL (1U << 4)
#define CC_LOCK_INFRA_DCM (1U << 5)
#define CC_SRCLKENA_MASK_0 (1U << 6)
#define CC_CXO32K_RM_EN_MD1 (1U << 9)
#define CC_CXO32K_RM_EN_MD2 (1U << 10)
#define CC_CLKSQ1_SEL (1U << 12)
#define CC_DISABLE_DORM_PWR (1U << 14)
#define CC_MD32_DCM_EN (1U << 18)
#define WFI_OP_AND 1
#define WFI_OP_OR 0
#define WAKE_MISC_PCM_TIMER (1U << 19)
#define WAKE_MISC_CPU_WAKE (1U << 20)
/* define WAKE_SRC_XXX */
#define WAKE_SRC_SPM_MERGE (1 << 0)
#define WAKE_SRC_KP (1 << 2)
#define WAKE_SRC_WDT (1 << 3)
#define WAKE_SRC_GPT (1 << 4)
#define WAKE_SRC_EINT (1 << 6)
#define WAKE_SRC_LOW_BAT (1 << 9)
#define WAKE_SRC_MD32 (1 << 10)
#define WAKE_SRC_USB_CD (1 << 14)
#define WAKE_SRC_USB_PDN (1 << 15)
#define WAKE_SRC_AFE (1 << 20)
#define WAKE_SRC_THERM (1 << 21)
#define WAKE_SRC_SYSPWREQ (1 << 24)
#define WAKE_SRC_SEJ (1 << 27)
#define WAKE_SRC_ALL_MD32 (1 << 28)
#define WAKE_SRC_CPU_IRQ (1 << 29)
enum wake_reason_t {
WR_NONE = 0,
WR_UART_BUSY = 1,
WR_PCM_ASSERT = 2,
WR_PCM_TIMER = 3,
WR_PCM_ABORT = 4,
WR_WAKE_SRC = 5,
WR_UNKNOWN = 6,
};
struct pwr_ctrl {
unsigned int pcm_flags;
unsigned int pcm_flags_cust;
unsigned int pcm_reserve;
unsigned int timer_val;
unsigned int timer_val_cust;
unsigned int wake_src;
unsigned int wake_src_cust;
unsigned int wake_src_md32;
unsigned short r0_ctrl_en;
unsigned short r7_ctrl_en;
unsigned short infra_dcm_lock;
unsigned short pcm_apsrc_req;
unsigned short mcusys_idle_mask;
unsigned short ca15top_idle_mask;
unsigned short ca7top_idle_mask;
unsigned short wfi_op;
unsigned short ca15_wfi0_en;
unsigned short ca15_wfi1_en;
unsigned short ca15_wfi2_en;
unsigned short ca15_wfi3_en;
unsigned short ca7_wfi0_en;
unsigned short ca7_wfi1_en;
unsigned short ca7_wfi2_en;
unsigned short ca7_wfi3_en;
unsigned short disp_req_mask;
unsigned short mfg_req_mask;
unsigned short md32_req_mask;
unsigned short syspwreq_mask;
unsigned short srclkenai_mask;
};
struct wake_status {
unsigned int assert_pc;
unsigned int r12;
unsigned int raw_sta;
unsigned int wake_misc;
unsigned int timer_out;
unsigned int r13;
unsigned int idle_sta;
unsigned int debug_flag;
unsigned int event_reg;
unsigned int isr;
};
struct pcm_desc {
const char *version; /* PCM code version */
const unsigned int *base; /* binary array base */
const unsigned int size; /* binary array size */
const unsigned char sess; /* session number */
const unsigned char replace; /* replace mode */
unsigned int vec0; /* event vector 0 config */
unsigned int vec1; /* event vector 1 config */
unsigned int vec2; /* event vector 2 config */
unsigned int vec3; /* event vector 3 config */
unsigned int vec4; /* event vector 4 config */
unsigned int vec5; /* event vector 5 config */
unsigned int vec6; /* event vector 6 config */
unsigned int vec7; /* event vector 7 config */
};
struct spm_lp_scen {
const struct pcm_desc *pcmdesc;
struct pwr_ctrl *pwrctrl;
};
#define EVENT_VEC(event, resume, imme, pc) \
(((pc) << 16) | \
(!!(imme) << 6) | \
(!!(resume) << 5) | \
((event) & 0x1f))
#define spm_read(addr) mmio_read_32(addr)
#define spm_write(addr, val) mmio_write_32(addr, val)
#define is_cpu_pdn(flags) (!((flags) & SPM_CPU_PDN_DIS))
#define is_infra_pdn(flags) (!((flags) & SPM_INFRA_PDN_DIS))
#define is_ddrphy_pdn(flags) (!((flags) & SPM_DDRPHY_PDN_DIS))
static inline void set_pwrctrl_pcm_flags(struct pwr_ctrl *pwrctrl,
unsigned int flags)
{
flags &= ~SPM_EXT_VSEL_GPIO103;
if (pwrctrl->pcm_flags_cust == 0)
pwrctrl->pcm_flags = flags;
else
pwrctrl->pcm_flags = pwrctrl->pcm_flags_cust;
}
static inline void set_pwrctrl_pcm_data(struct pwr_ctrl *pwrctrl,
unsigned int data)
{
pwrctrl->pcm_reserve = data;
}
void spm_reset_and_init_pcm(void);
void spm_init_pcm_register(void); /* init r0 and r7 */
void spm_set_power_control(const struct pwr_ctrl *pwrctrl);
void spm_set_wakeup_event(const struct pwr_ctrl *pwrctrl);
void spm_get_wakeup_status(struct wake_status *wakesta);
void spm_set_sysclk_settle(void);
void spm_kick_pcm_to_run(struct pwr_ctrl *pwrctrl);
void spm_clean_after_wakeup(void);
enum wake_reason_t spm_output_wake_reason(struct wake_status *wakesta);
void spm_register_init(void);
void spm_go_to_hotplug(void);
void spm_init_event_vector(const struct pcm_desc *pcmdesc);
void spm_kick_im_to_fetch(const struct pcm_desc *pcmdesc);
void spm_set_sysclk_settle(void);
int is_mcdi_ready(void);
int is_hotplug_ready(void);
int is_suspend_ready(void);
void set_mcdi_ready(void);
void set_hotplug_ready(void);
void set_suspend_ready(void);
void clear_all_ready(void);
void spm_lock_init(void);
void spm_lock_get(void);
void spm_lock_release(void);
void spm_boot_init(void);
#endif /* __SPM_H__ */

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/*
* Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* Neither the name of ARM nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#include <mmio.h>
#include <mt8173_def.h>
#include <platform.h>
#include <spm.h>
#include <spm_hotplug.h>
#include <spm_mcdi.h>
/*
* System Power Manager (SPM) is a hardware module, which controls cpu or
* system power for different power scenarios using different firmware.
* This driver controls the cpu power in cpu hotplug flow.
*/
#define PCM_HOTPLUG_VALID_MASK 0x00ff0000
#define PCM_HOTPLUG_VALID_SHIFT 0x8
/**********************************************************
* PCM sequence for CPU hotplug
**********************************************************/
static const unsigned int hotplug_binary[] = {
0x1900001f, 0x1020020c, 0x1950001f, 0x1020020c, 0xa9400005, 0x00000001,
0xe1000005, 0x1910001f, 0x10006720, 0x814c9001, 0xd82000e5, 0x17c07c1f,
0x1900001f, 0x10001220, 0x1950001f, 0x10001220, 0xa15f0405, 0xe1000005,
0x1900001f, 0x10001228, 0x1950001f, 0x10001228, 0x810f1401, 0xd8200244,
0x17c07c1f, 0xe2e0006d, 0xe2e0002d, 0x1a00001f, 0x100062b8, 0x1910001f,
0x100062b8, 0xa9000004, 0x00000001, 0xe2000004, 0x1910001f, 0x100062b8,
0x81142804, 0xd8200444, 0x17c07c1f, 0xe2e0002c, 0xe2e0003c, 0xe2e0003e,
0xe2e0003a, 0xe2e00032, 0x1910001f, 0x1000660c, 0x81079001, 0x1950001f,
0x10006610, 0x81479401, 0xa1001404, 0xd8000584, 0x17c07c1f, 0x1900001f,
0x10006404, 0x1950001f, 0x10006404, 0xa1568405, 0xe1000005, 0xf0000000,
0x17c07c1f, 0x1900001f, 0x10006404, 0x1950001f, 0x10006404, 0x89400005,
0x0000dfff, 0xe1000005, 0xe2e00036, 0xe2e0003e, 0x1910001f, 0x1000660c,
0x81079001, 0x1950001f, 0x10006610, 0x81479401, 0x81001404, 0xd82008c4,
0x17c07c1f, 0xe2e0002e, 0x1a00001f, 0x100062b8, 0x1910001f, 0x100062b8,
0x89000004, 0x0000fffe, 0xe2000004, 0x1910001f, 0x100062b8, 0x81142804,
0xd8000ae4, 0x17c07c1f, 0xe2e0006e, 0xe2e0004e, 0xe2e0004c, 0xe2e0004d,
0x1900001f, 0x10001220, 0x1950001f, 0x10001220, 0x89400005, 0xbfffffff,
0xe1000005, 0x1900001f, 0x10001228, 0x1950001f, 0x10001228, 0x810f1401,
0xd8000ce4, 0x17c07c1f, 0x1900001f, 0x1020020c, 0x1950001f, 0x1020020c,
0x89400005, 0xfffffffe, 0xe1000005, 0xf0000000, 0x17c07c1f, 0x1212841f,
0xe2e00036, 0xe2e0003e, 0x1380201f, 0xe2e0003c, 0xe2a00000, 0x1b80001f,
0x20000080, 0xe2e0007c, 0x1b80001f, 0x20000003, 0xe2e0005c, 0xe2e0004c,
0xe2e0004d, 0xf0000000, 0x17c07c1f, 0xe2e0004f, 0xe2e0006f, 0xe2e0002f,
0xe2a00001, 0x1b80001f, 0x20000080, 0xe2e0002e, 0xe2e0003e, 0xe2e00032,
0xf0000000, 0x17c07c1f, 0x1212841f, 0xe2e00026, 0xe2e0002e, 0x1380201f,
0x1a00001f, 0x100062b4, 0x1910001f, 0x100062b4, 0x81322804, 0xe2000004,
0x81202804, 0xe2000004, 0x1b80001f, 0x20000034, 0x1910001f, 0x100062b4,
0x81142804, 0xd8001404, 0x17c07c1f, 0xe2e0000e, 0xe2e0000c, 0xe2e0000d,
0xf0000000, 0x17c07c1f, 0xe2e0002d, 0x1a00001f, 0x100062b4, 0x1910001f,
0x100062b4, 0xa1002804, 0xe2000004, 0xa1122804, 0xe2000004, 0x1b80001f,
0x20000080, 0x1910001f, 0x100062b4, 0x81142804, 0xd82016a4, 0x17c07c1f,
0xe2e0002f, 0xe2e0002b, 0xe2e00023, 0x1380201f, 0xe2e00022, 0xf0000000,
0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
0x17c07c1f, 0x17c07c1f, 0x1840001f, 0x00000001, 0x1840001f, 0x00000001,
0x1840001f, 0x00000001, 0xa1d48407, 0x1b00001f, 0x2f7be75f, 0xe8208000,
0x10006354, 0xfffe7b47, 0xa1d10407, 0x1b80001f, 0x20000020, 0x17c07c1f,
0x1910001f, 0x10006b00, 0x81461001, 0xb14690a1, 0xd82044e5, 0x17c07c1f,
0x1910001f, 0x10006610, 0x81079001, 0xd80044e4, 0x17c07c1f, 0x1990001f,
0x10006b00, 0x81421801, 0x82429801, 0x81402405, 0xd80044e5, 0x17c07c1f,
0x1a40001f, 0x100062b0, 0x1280041f, 0xc24007a0, 0x17c07c1f, 0x1910001f,
0x10006b00, 0x81449001, 0xd8204be5, 0x17c07c1f, 0x1910001f, 0x10006b00,
0x81009001, 0xd8204984, 0x17c07c1f, 0x1910001f, 0x10006610, 0x81051001,
0xd8204be4, 0x17c07c1f, 0x1910001f, 0x10006720, 0x81489001, 0xd82046c5,
0x17c07c1f, 0x1a40001f, 0x10006218, 0x1a80001f, 0x10006264, 0xc24010e0,
0x17c07c1f, 0x1910001f, 0x1000660c, 0x81051001, 0x1950001f, 0x10006610,
0x81451401, 0xa1001404, 0xd8004824, 0x17c07c1f, 0xd0004b00, 0x17c07c1f,
0x17c07c1f, 0x1910001f, 0x10006610, 0x81051001, 0xd8004be4, 0x17c07c1f,
0x1a40001f, 0x10006218, 0x1a80001f, 0x10006264, 0xc2400ee0, 0x17c07c1f,
0x1910001f, 0x10006b00, 0x89000004, 0xfffffdff, 0x1940001f, 0x10006b00,
0xe1400004, 0x17c07c1f, 0x1910001f, 0x10006b00, 0x81451001, 0xd8205305,
0x17c07c1f, 0x1910001f, 0x10006b00, 0x81011001, 0xd82050a4, 0x17c07c1f,
0x1910001f, 0x10006610, 0x81059001, 0xd8205304, 0x17c07c1f, 0x1910001f,
0x10006720, 0x81491001, 0xd8204de5, 0x17c07c1f, 0x1a40001f, 0x1000621c,
0x1a80001f, 0x1000626c, 0xc24010e0, 0x17c07c1f, 0x1910001f, 0x1000660c,
0x81059001, 0x1950001f, 0x10006610, 0x81459401, 0xa1001404, 0xd8004f44,
0x17c07c1f, 0xd0005220, 0x17c07c1f, 0x17c07c1f, 0x1910001f, 0x10006610,
0x81059001, 0xd8005304, 0x17c07c1f, 0x1a40001f, 0x1000621c, 0x1a80001f,
0x1000626c, 0xc2400ee0, 0x17c07c1f, 0x1910001f, 0x10006b00, 0x89000004,
0xfffffbff, 0x1940001f, 0x10006b00, 0xe1400004, 0x17c07c1f, 0x1910001f,
0x10006b00, 0x81459001, 0xd8205a25, 0x17c07c1f, 0x1910001f, 0x10006b00,
0x81019001, 0xd82057c4, 0x17c07c1f, 0x1910001f, 0x10006610, 0x81061001,
0xd8205a24, 0x17c07c1f, 0x1910001f, 0x10006720, 0x81499001, 0xd8205505,
0x17c07c1f, 0x1a40001f, 0x10006220, 0x1a80001f, 0x10006274, 0xc24010e0,
0x17c07c1f, 0x1910001f, 0x1000660c, 0x81061001, 0x1950001f, 0x10006610,
0x81461401, 0xa1001404, 0xd8005664, 0x17c07c1f, 0xd0005940, 0x17c07c1f,
0x17c07c1f, 0x1910001f, 0x10006610, 0x81061001, 0xd8005a24, 0x17c07c1f,
0x1a40001f, 0x10006220, 0x1a80001f, 0x10006274, 0xc2400ee0, 0x17c07c1f,
0x1910001f, 0x10006b00, 0x89000004, 0xfffff7ff, 0x1940001f, 0x10006b00,
0xe1400004, 0x17c07c1f, 0x1910001f, 0x10006b00, 0x81461001, 0xd8206185,
0x17c07c1f, 0x1910001f, 0x10006b00, 0x81021001, 0xd8205ec4, 0x17c07c1f,
0x1910001f, 0x10006610, 0x81081001, 0xd8206184, 0x17c07c1f, 0x1910001f,
0x10006720, 0x814a1001, 0xd8205c25, 0x17c07c1f, 0x1a40001f, 0x100062a0,
0x1280041f, 0xc2401540, 0x17c07c1f, 0x1910001f, 0x1000660c, 0x81081001,
0x1950001f, 0x10006610, 0x81481401, 0xa1001404, 0xd8005d64, 0x17c07c1f,
0xd00060a0, 0x17c07c1f, 0x17c07c1f, 0x1910001f, 0x10006610, 0x81479001,
0x81881001, 0x69a00006, 0x00000000, 0x81401805, 0xd8206185, 0x17c07c1f,
0x1a40001f, 0x100062a0, 0x1280041f, 0xc2401240, 0x17c07c1f, 0x1910001f,
0x10006b00, 0x89000004, 0xffffefff, 0x1940001f, 0x10006b00, 0xe1400004,
0x17c07c1f, 0x1910001f, 0x10006b00, 0x81469001, 0xd82068e5, 0x17c07c1f,
0x1910001f, 0x10006b00, 0x81029001, 0xd8206624, 0x17c07c1f, 0x1910001f,
0x10006610, 0x81089001, 0xd82068e4, 0x17c07c1f, 0x1910001f, 0x10006720,
0x814a9001, 0xd8206385, 0x17c07c1f, 0x1a40001f, 0x100062a4, 0x1290841f,
0xc2401540, 0x17c07c1f, 0x1910001f, 0x1000660c, 0x81089001, 0x1950001f,
0x10006610, 0x81489401, 0xa1001404, 0xd80064c4, 0x17c07c1f, 0xd0006800,
0x17c07c1f, 0x17c07c1f, 0x1910001f, 0x10006610, 0x81479001, 0x81889001,
0x69a00006, 0x00000000, 0x81401805, 0xd82068e5, 0x17c07c1f, 0x1a40001f,
0x100062a4, 0x1290841f, 0xc2401240, 0x17c07c1f, 0x1910001f, 0x10006b00,
0x89000004, 0xffffdfff, 0x1940001f, 0x10006b00, 0xe1400004, 0x1910001f,
0x10006610, 0x81479001, 0x81881001, 0x69600005, 0x00000000, 0xa1401805,
0x81889001, 0xa1401805, 0xd8006bc5, 0x17c07c1f, 0x1910001f, 0x10006b00,
0x81421001, 0x82429001, 0x82802405, 0xd8206bca, 0x17c07c1f, 0x1a40001f,
0x100062b0, 0x1280041f, 0xc2400000, 0x17c07c1f, 0x1990001f, 0x10006b00,
0x89800006, 0x00003f00, 0x69200006, 0x00000000, 0xd82041e4, 0x17c07c1f,
0x1990001f, 0x10006320, 0x69200006, 0xbeefbeef, 0xd8006dc4, 0x17c07c1f,
0xd00041e0, 0x17c07c1f, 0x1910001f, 0x10006358, 0x810b1001, 0xd8006dc4,
0x17c07c1f, 0x1980001f, 0xdeaddead, 0x19c0001f, 0x01411820, 0xf0000000
};
static const struct pcm_desc hotplug_pcm = {
.version = "pcm_power_down_mt8173_V37",
.base = hotplug_binary,
.size = 888,
.sess = 2,
.replace = 0,
};
static struct pwr_ctrl hotplug_ctrl = {
.wake_src = 0,
.wake_src_md32 = 0,
.wfi_op = WFI_OP_OR,
.mcusys_idle_mask = 1,
.ca7top_idle_mask = 1,
.ca15top_idle_mask = 1,
.disp_req_mask = 1,
.mfg_req_mask = 1,
.md32_req_mask = 1,
.syspwreq_mask = 1,
.pcm_flags = 0,
};
static const struct spm_lp_scen spm_hotplug = {
.pcmdesc = &hotplug_pcm,
.pwrctrl = &hotplug_ctrl,
};
void spm_go_to_hotplug(void)
{
const struct pcm_desc *pcmdesc = spm_hotplug.pcmdesc;
struct pwr_ctrl *pwrctrl = spm_hotplug.pwrctrl;
set_pwrctrl_pcm_flags(pwrctrl, 0);
spm_reset_and_init_pcm();
spm_kick_im_to_fetch(pcmdesc);
spm_set_power_control(pwrctrl);
spm_set_wakeup_event(pwrctrl);
spm_kick_pcm_to_run(pwrctrl);
}
void spm_clear_hotplug(void)
{
/* Inform SPM that CPU wants to program CPU_WAKEUP_EVENT and
* DISABLE_CPU_DROM */
mmio_write_32(SPM_PCM_REG_DATA_INI, PCM_HANDSHAKE_SEND1);
mmio_write_32(SPM_PCM_PWR_IO_EN, PCM_RF_SYNC_R6);
mmio_write_32(SPM_PCM_PWR_IO_EN, 0);
/* Wait SPM's response, can't use sleep api */
while ((mmio_read_32(SPM_PCM_FSM_STA) & PCM_END_FSM_STA_MASK)
!= PCM_END_FSM_STA_DEF)
;
/* no hotplug pcm running */
clear_all_ready();
}
void spm_hotplug_on(unsigned long mpidr)
{
unsigned long linear_id;
linear_id = platform_get_core_pos(mpidr);
spm_lock_get();
if (is_hotplug_ready() == 0) {
spm_mcdi_wakeup_all_cores();
mmio_clrbits_32(SPM_PCM_RESERVE, PCM_HOTPLUG_VALID_MASK);
spm_go_to_hotplug();
set_hotplug_ready();
}
/* turn on CPUx */
mmio_clrsetbits_32(SPM_PCM_RESERVE,
PCM_HOTPLUG_VALID_MASK | (1 << linear_id),
1 << (linear_id + PCM_HOTPLUG_VALID_SHIFT));
spm_lock_release();
}
void spm_hotplug_off(unsigned long mpidr)
{
unsigned long linear_id;
linear_id = platform_get_core_pos(mpidr);
spm_lock_get();
if (is_hotplug_ready() == 0) {
spm_mcdi_wakeup_all_cores();
mmio_clrbits_32(SPM_PCM_RESERVE, PCM_HOTPLUG_VALID_MASK);
spm_go_to_hotplug();
set_hotplug_ready();
}
mmio_clrsetbits_32(SPM_PCM_RESERVE, PCM_HOTPLUG_VALID_MASK,
(1 << linear_id) |
(1 << (linear_id + PCM_HOTPLUG_VALID_SHIFT)));
spm_lock_release();
}

37
plat/mediatek/mt8173/drivers/spm/spm_hotplug.h Normal file
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@ -0,0 +1,37 @@
/*
* Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* Neither the name of ARM nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __SPM_HOTPLUG_H__
#define __SPM_HOTPLUG_H__
void spm_clear_hotplug(void);
void spm_hotplug_off(unsigned long mpidr);
void spm_hotplug_on(unsigned long mpidr);
#endif /* __SPM_HOTPLUG_H__ */

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/*
* Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* Neither the name of ARM nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#include <arch.h>
#include <debug.h>
#include <mmio.h>
#include <mt8173_def.h>
#include <platform.h>
#include <platform_def.h>
#include <spm.h>
#include <spm_hotplug.h>
#include <spm_mcdi.h>
/*
* System Power Manager (SPM) is a hardware module, which controls cpu or
* system power for different power scenarios using different firmware.
* This driver controls the cpu power in cpu idle power saving state.
*/
#define WAKE_SRC_FOR_MCDI (WAKE_SRC_SYSPWREQ | WAKE_SRC_CPU_IRQ)
#define PCM_MCDI_HANDSHAKE_SYNC 0xbeefbeef
#define PCM_MCDI_HANDSHAKE_ACK 0xdeaddead
#define PCM_MCDI_UPDATE_INFORM 0xabcdabcd
#define PCM_MCDI_CKECK_DONE 0x12345678
#define PCM_MCDI_ALL_CORE_AWAKE 0x0
#define PCM_MCDI_OFFLOADED 0xaa55aa55
static const unsigned int mcdi_binary[] = {
0x1212841f, 0xe2e00036, 0xe2e0003e, 0x1380201f, 0xe2e0003c, 0xe2a00000,
0x1b80001f, 0x20000080, 0xe2e0007c, 0x1b80001f, 0x20000003, 0xe2e0005c,
0xe2e0004c, 0xe2e0004d, 0xf0000000, 0x17c07c1f, 0xe2e0004f, 0xe2e0006f,
0xe2e0002f, 0xe2a00001, 0x1b80001f, 0x20000080, 0xe2e0002e, 0xe2e0003e,
0xe2e00032, 0xf0000000, 0x17c07c1f, 0x1212841f, 0xe2e00026, 0xe2e0002e,
0x1380201f, 0x1a00001f, 0x100062b4, 0x1910001f, 0x100062b4, 0x81322804,
0xe2000004, 0x81202804, 0xe2000004, 0x1b80001f, 0x20000034, 0x1910001f,
0x100062b4, 0x81142804, 0xd8000524, 0x17c07c1f, 0xe2e0000e, 0xe2e0000c,
0xe2e0000d, 0xf0000000, 0x17c07c1f, 0xe2e0002d, 0x1a00001f, 0x100062b4,
0x1910001f, 0x100062b4, 0xa1002804, 0xe2000004, 0xa1122804, 0xe2000004,
0x1b80001f, 0x20000080, 0x1910001f, 0x100062b4, 0x81142804, 0xd82007c4,
0x17c07c1f, 0xe2e0002f, 0xe2e0002b, 0xe2e00023, 0x1380201f, 0xe2e00022,
0xf0000000, 0x17c07c1f, 0x18c0001f, 0x10006b6c, 0x1910001f, 0x10006b6c,
0xa1002804, 0xe0c00004, 0xf0000000, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
0x17c07c1f, 0x17c07c1f, 0x1840001f, 0x00000001, 0x11407c1f, 0xe8208000,
0x10006b6c, 0xa0000000, 0xe8208000, 0x10006310, 0x0b160008, 0x1900001f,
0x000f7bde, 0x1a00001f, 0x10200268, 0xe2000004, 0xe8208000, 0x10006600,
0x00000000, 0xc2800940, 0x1280041f, 0x1b00001f, 0x21000001, 0x1b80001f,
0xd0010000, 0xc2800940, 0x1290841f, 0x69200006, 0xbeefbeef, 0xd8204764,
0x17c07c1f, 0xc2800940, 0x1291041f, 0x1910001f, 0x10006358, 0x810b1001,
0xd80043e4, 0x17c07c1f, 0x1980001f, 0xdeaddead, 0x69200006, 0xabcdabcd,
0xd82044c4, 0x17c07c1f, 0xc2800940, 0x1291841f, 0x88900001, 0x10006814,
0x1910001f, 0x10006400, 0x81271002, 0x1880001f, 0x10006600, 0xe0800004,
0x1910001f, 0x10006358, 0x810b1001, 0xd8004684, 0x17c07c1f, 0x1980001f,
0x12345678, 0x60a07c05, 0x89100002, 0x10006600, 0x80801001, 0xd8007142,
0x17c07c1f, 0xc2800940, 0x1292041f, 0x1a10001f, 0x10006720, 0x82002001,
0x82201408, 0xd8204a08, 0x17c07c1f, 0x1a40001f, 0x10006200, 0x1a80001f,
0x1000625c, 0xc2400200, 0x17c07c1f, 0xa1400405, 0xc2800940, 0x1292841f,
0x1a10001f, 0x10006720, 0x8200a001, 0x82209408, 0xd8204be8, 0x17c07c1f,
0x1a40001f, 0x10006218, 0x1a80001f, 0x10006264, 0xc2400200, 0x17c07c1f,
0xa1508405, 0xc2800940, 0x1293041f, 0x1a10001f, 0x10006720, 0x82012001,
0x82211408, 0xd8204dc8, 0x17c07c1f, 0x1a40001f, 0x1000621c, 0x1a80001f,
0x1000626c, 0xc2400200, 0x17c07c1f, 0xa1510405, 0x1a10001f, 0x10006720,
0x8201a001, 0x82219408, 0xd8204f68, 0x17c07c1f, 0x1a40001f, 0x10006220,
0x1a80001f, 0x10006274, 0xc2400200, 0x17c07c1f, 0xa1518405, 0x1a10001f,
0x10006720, 0x82022001, 0x82221408, 0xd82050e8, 0x17c07c1f, 0x1a40001f,
0x100062a0, 0x1280041f, 0xc2400660, 0x17c07c1f, 0xa1520405, 0x1a10001f,
0x10006720, 0x8202a001, 0x82229408, 0xd8205268, 0x17c07c1f, 0x1a40001f,
0x100062a4, 0x1290841f, 0xc2400660, 0x17c07c1f, 0xa1528405, 0x1a10001f,
0x10006720, 0x82032001, 0x82231408, 0xd82053e8, 0x17c07c1f, 0x1a40001f,
0x100062a8, 0x1291041f, 0xc2400660, 0x17c07c1f, 0xa1530405, 0x1a10001f,
0x10006720, 0x8203a001, 0x82239408, 0xd8205568, 0x17c07c1f, 0x1a40001f,
0x100062ac, 0x1291841f, 0xc2400660, 0x17c07c1f, 0xa1538405, 0x1b80001f,
0x20000208, 0xd82070cc, 0x17c07c1f, 0x81001401, 0xd8205964, 0x17c07c1f,
0x1a10001f, 0x10006918, 0x81002001, 0xb1042081, 0xb1003081, 0xb10c3081,
0xd8205964, 0x17c07c1f, 0x1a40001f, 0x10006200, 0x1a80001f, 0x1000625c,
0xc2400000, 0x17c07c1f, 0x89400005, 0xfffffffe, 0xe8208000, 0x10006f00,
0x00000000, 0xe8208000, 0x10006b30, 0x00000000, 0xe8208000, 0x100063e0,
0x00000001, 0x81009401, 0xd8205cc4, 0x17c07c1f, 0x1a10001f, 0x10006918,
0x8100a001, 0xb104a081, 0xb1003081, 0xd8205cc4, 0x17c07c1f, 0x1a40001f,
0x10006218, 0x1a80001f, 0x10006264, 0xc2400000, 0x17c07c1f, 0x89400005,
0xfffffffd, 0xe8208000, 0x10006f04, 0x00000000, 0xe8208000, 0x10006b34,
0x00000000, 0xe8208000, 0x100063e0, 0x00000002, 0x81011401, 0xd8206024,
0x17c07c1f, 0x1a10001f, 0x10006918, 0x81012001, 0xb1052081, 0xb1003081,
0xd8206024, 0x17c07c1f, 0x1a40001f, 0x1000621c, 0x1a80001f, 0x1000626c,
0xc2400000, 0x17c07c1f, 0x89400005, 0xfffffffb, 0xe8208000, 0x10006f08,
0x00000000, 0xe8208000, 0x10006b38, 0x00000000, 0xe8208000, 0x100063e0,
0x00000004, 0x81019401, 0xd8206384, 0x17c07c1f, 0x1a10001f, 0x10006918,
0x8101a001, 0xb105a081, 0xb1003081, 0xd8206384, 0x17c07c1f, 0x1a40001f,
0x10006220, 0x1a80001f, 0x10006274, 0xc2400000, 0x17c07c1f, 0x89400005,
0xfffffff7, 0xe8208000, 0x10006f0c, 0x00000000, 0xe8208000, 0x10006b3c,
0x00000000, 0xe8208000, 0x100063e0, 0x00000008, 0x81021401, 0xd82066c4,
0x17c07c1f, 0x1a10001f, 0x10006918, 0x81022001, 0xb1062081, 0xb1003081,
0xd82066c4, 0x17c07c1f, 0x1a40001f, 0x100062a0, 0x1280041f, 0xc2400360,
0x17c07c1f, 0x89400005, 0xffffffef, 0xe8208000, 0x10006f10, 0x00000000,
0xe8208000, 0x10006b40, 0x00000000, 0xe8208000, 0x100063e0, 0x00000010,
0x81029401, 0xd8206a04, 0x17c07c1f, 0x1a10001f, 0x10006918, 0x8102a001,
0xb106a081, 0xb1003081, 0xd8206a04, 0x17c07c1f, 0x1a40001f, 0x100062a4,
0x1290841f, 0xc2400360, 0x17c07c1f, 0x89400005, 0xffffffdf, 0xe8208000,
0x10006f14, 0x00000000, 0xe8208000, 0x10006b44, 0x00000000, 0xe8208000,
0x100063e0, 0x00000020, 0x81031401, 0xd8206d44, 0x17c07c1f, 0x1a10001f,
0x10006918, 0x81032001, 0xb1072081, 0xb1003081, 0xd8206d44, 0x17c07c1f,
0x1a40001f, 0x100062a8, 0x1291041f, 0xc2400360, 0x17c07c1f, 0x89400005,
0xffffffbf, 0xe8208000, 0x10006f18, 0x00000000, 0xe8208000, 0x10006b48,
0x00000000, 0xe8208000, 0x100063e0, 0x00000040, 0x81039401, 0xd8207084,
0x17c07c1f, 0x1a10001f, 0x10006918, 0x8103a001, 0xb107a081, 0xb1003081,
0xd8207084, 0x17c07c1f, 0x1a40001f, 0x100062ac, 0x1291841f, 0xc2400360,
0x17c07c1f, 0x89400005, 0xffffff7f, 0xe8208000, 0x10006f1c, 0x00000000,
0xe8208000, 0x10006b4c, 0x00000000, 0xe8208000, 0x100063e0, 0x00000080,
0xc2800940, 0x1293841f, 0xd0004260, 0x17c07c1f, 0xc2800940, 0x1294041f,
0xe8208000, 0x10006600, 0x00000000, 0x1ac0001f, 0x55aa55aa, 0x1940001f,
0xaa55aa55, 0xc2800940, 0x1294841f, 0x1b80001f, 0x00001000, 0xf0000000,
0x17c07c1f
};
static const struct pcm_desc mcdi_pcm = {
.version = "pcm_mcdi_v0.5_20140721_mt8173_v03.04_20150507",
.base = mcdi_binary,
.size = 919,
.sess = 2,
.replace = 0,
};
static struct pwr_ctrl mcdi_ctrl = {
.wake_src = WAKE_SRC_FOR_MCDI,
.wake_src_md32 = 0,
.wfi_op = WFI_OP_OR,
.mcusys_idle_mask = 1,
.ca7top_idle_mask = 1,
.ca15top_idle_mask = 1,
.disp_req_mask = 1,
.mfg_req_mask = 1,
.md32_req_mask = 1,
};
static const struct spm_lp_scen spm_mcdi = {
.pcmdesc = &mcdi_pcm,
.pwrctrl = &mcdi_ctrl,
};
void spm_mcdi_cpu_wake_up_event(int wake_up_event, int disable_dormant_power)
{
if (((mmio_read_32(SPM_SLEEP_CPU_WAKEUP_EVENT) & 0x1) == 1)
&& ((mmio_read_32(SPM_CLK_CON) & CC_DISABLE_DORM_PWR) == 0)) {
/* MCDI is offload? */
INFO("%s: SPM_SLEEP_CPU_WAKEUP_EVENT:%x, SPM_CLK_CON %x",
__func__, mmio_read_32(SPM_SLEEP_CPU_WAKEUP_EVENT),
mmio_read_32(SPM_CLK_CON));
return;
}
/* Inform SPM that CPU wants to program CPU_WAKEUP_EVENT and
* DISABLE_CPU_DROM */
mmio_write_32(SPM_PCM_REG_DATA_INI, PCM_MCDI_HANDSHAKE_SYNC);
mmio_write_32(SPM_PCM_PWR_IO_EN, PCM_RF_SYNC_R6);
mmio_write_32(SPM_PCM_PWR_IO_EN, 0);
/* Wait SPM's response, can't use sleep api */
while (mmio_read_32(SPM_PCM_REG6_DATA) != PCM_MCDI_HANDSHAKE_ACK)
;
if (disable_dormant_power) {
mmio_setbits_32(SPM_CLK_CON, CC_DISABLE_DORM_PWR);
while (mmio_read_32(SPM_CLK_CON) !=
(mmio_read_32(SPM_CLK_CON) | CC_DISABLE_DORM_PWR))
;
} else {
mmio_clrbits_32(SPM_CLK_CON, CC_DISABLE_DORM_PWR);
while (mmio_read_32(SPM_CLK_CON) !=
(mmio_read_32(SPM_CLK_CON) & ~CC_DISABLE_DORM_PWR))
;
}
mmio_write_32(SPM_SLEEP_CPU_WAKEUP_EVENT, wake_up_event);
while (mmio_read_32(SPM_SLEEP_CPU_WAKEUP_EVENT) != wake_up_event)
;
/* Inform SPM to see updated setting */
mmio_write_32(SPM_PCM_REG_DATA_INI, PCM_MCDI_UPDATE_INFORM);
mmio_write_32(SPM_PCM_PWR_IO_EN, PCM_RF_SYNC_R6);
mmio_write_32(SPM_PCM_PWR_IO_EN, 0);
while (mmio_read_32(SPM_PCM_REG6_DATA) != PCM_MCDI_CKECK_DONE)
;
/* END OF sequence */
mmio_write_32(SPM_PCM_REG_DATA_INI, 0x0);
mmio_write_32(SPM_PCM_PWR_IO_EN, PCM_RF_SYNC_R6);
mmio_write_32(SPM_PCM_PWR_IO_EN, 0);
}
void spm_mcdi_wakeup_all_cores(void)
{
if (is_mcdi_ready() == 0)
return;
spm_mcdi_cpu_wake_up_event(1, 1);
while (mmio_read_32(SPM_PCM_REG5_DATA) != PCM_MCDI_ALL_CORE_AWAKE)
;
spm_mcdi_cpu_wake_up_event(1, 0);
while (mmio_read_32(SPM_PCM_REG5_DATA) != PCM_MCDI_OFFLOADED)
;
spm_clean_after_wakeup();
clear_all_ready();
}
void spm_mcdi_wfi_sel_enter(unsigned long mpidr)
{
int core_id_val = mpidr & MPIDR_CPU_MASK;
int cluster_id = (mpidr & MPIDR_CLUSTER_MASK) >> MPIDR_AFFINITY_BITS;
/* SPM WFI Select by core number */
if (cluster_id) {
switch (core_id_val) {
case 0:
mmio_write_32(SPM_CA15_CPU0_IRQ_MASK, 1);
mmio_write_32(SPM_SLEEP_CA15_WFI0_EN, 1);
break;
case 1:
mmio_write_32(SPM_CA15_CPU1_IRQ_MASK, 1);
mmio_write_32(SPM_SLEEP_CA15_WFI1_EN, 1);
break;
case 2:
mmio_write_32(SPM_CA15_CPU2_IRQ_MASK, 1);
mmio_write_32(SPM_SLEEP_CA15_WFI2_EN, 1);
break;
case 3:
mmio_write_32(SPM_CA15_CPU3_IRQ_MASK, 1);
mmio_write_32(SPM_SLEEP_CA15_WFI3_EN, 1);
break;
default:
break;
}
} else {
switch (core_id_val) {
case 0:
mmio_write_32(SPM_CA7_CPU0_IRQ_MASK, 1);
mmio_write_32(SPM_SLEEP_CA7_WFI0_EN, 1);
break;
case 1:
mmio_write_32(SPM_CA7_CPU1_IRQ_MASK, 1);
mmio_write_32(SPM_SLEEP_CA7_WFI1_EN, 1);
break;
case 2:
mmio_write_32(SPM_CA7_CPU2_IRQ_MASK, 1);
mmio_write_32(SPM_SLEEP_CA7_WFI2_EN, 1);
break;
case 3:
mmio_write_32(SPM_CA7_CPU3_IRQ_MASK, 1);
mmio_write_32(SPM_SLEEP_CA7_WFI3_EN, 1);
break;
default:
break;
}
}
}
void spm_mcdi_wfi_sel_leave(unsigned long mpidr)
{
int core_id_val = mpidr & MPIDR_CPU_MASK;
int cluster_id = (mpidr & MPIDR_CLUSTER_MASK) >> MPIDR_AFFINITY_BITS;
/* SPM WFI Select by core number */
if (cluster_id) {
switch (core_id_val) {
case 0:
mmio_write_32(SPM_SLEEP_CA15_WFI0_EN, 0);
mmio_write_32(SPM_CA15_CPU0_IRQ_MASK, 0);
break;
case 1:
mmio_write_32(SPM_SLEEP_CA15_WFI1_EN, 0);
mmio_write_32(SPM_CA15_CPU1_IRQ_MASK, 0);
break;
case 2:
mmio_write_32(SPM_SLEEP_CA15_WFI2_EN, 0);
mmio_write_32(SPM_CA15_CPU2_IRQ_MASK, 0);
break;
case 3:
mmio_write_32(SPM_SLEEP_CA15_WFI3_EN, 0);
mmio_write_32(SPM_CA15_CPU3_IRQ_MASK, 0);
break;
default:
break;
}
} else {
switch (core_id_val) {
case 0:
mmio_write_32(SPM_SLEEP_CA7_WFI0_EN, 0);
mmio_write_32(SPM_CA7_CPU0_IRQ_MASK, 0);
break;
case 1:
mmio_write_32(SPM_SLEEP_CA7_WFI1_EN, 0);
mmio_write_32(SPM_CA7_CPU1_IRQ_MASK, 0);
break;
case 2:
mmio_write_32(SPM_SLEEP_CA7_WFI2_EN, 0);
mmio_write_32(SPM_CA7_CPU2_IRQ_MASK, 0);
break;
case 3:
mmio_write_32(SPM_SLEEP_CA7_WFI3_EN, 0);
mmio_write_32(SPM_CA7_CPU3_IRQ_MASK, 0);
break;
default:
break;
}
}
}
void spm_mcdi_prepare(unsigned long mpidr)
{
const struct pcm_desc *pcmdesc = spm_mcdi.pcmdesc;
struct pwr_ctrl *pwrctrl = spm_mcdi.pwrctrl;
spm_lock_get();
if (is_mcdi_ready() == 0) {
if (is_hotplug_ready() == 1)
spm_clear_hotplug();
set_pwrctrl_pcm_flags(pwrctrl, 0);
spm_reset_and_init_pcm();
spm_kick_im_to_fetch(pcmdesc);
spm_set_power_control(pwrctrl);
spm_set_wakeup_event(pwrctrl);
spm_kick_pcm_to_run(pwrctrl);
set_mcdi_ready();
}
spm_mcdi_wfi_sel_enter(mpidr);
spm_lock_release();
}
void spm_mcdi_finish(unsigned long mpidr)
{
unsigned long linear_id = platform_get_core_pos(mpidr);
spm_lock_get();
spm_mcdi_wfi_sel_leave(mpidr);
mmio_write_32(SPM_PCM_SW_INT_CLEAR, (0x1 << linear_id));
spm_lock_release();
}

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/*
* Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* Neither the name of ARM nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __SPM_MCDI_H__
#define __SPM_MCDI_H__
void spm_mcdi_wakeup_all_cores(void);
void spm_mcdi_wfi_sel_enter(unsigned long mpidr);
void spm_mcdi_wfi_sel_leave(unsigned long mpidr);
void spm_mcdi_prepare(unsigned long mpidr);
void spm_mcdi_finish(unsigned long mpidr);
#endif /* __SPM_MCDI_H__ */

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/*
* Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* Neither the name of ARM nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#include <bakery_lock.h>
#include <debug.h>
#include <spm.h>
#include <spm_suspend.h>
/*
* System Power Manager (SPM) is a hardware module, which controls cpu or
* system power for different power scenarios using different firmware.
* This driver controls the system power in system suspend flow.
*/
#define WAIT_UART_ACK_TIMES 80 /* 80 * 10us */
#define WAKE_SRC_FOR_SUSPEND \
(WAKE_SRC_KP | WAKE_SRC_EINT | WAKE_SRC_MD32 | \
WAKE_SRC_USB_CD | WAKE_SRC_USB_PDN | WAKE_SRC_THERM | \
WAKE_SRC_SYSPWREQ | WAKE_SRC_SEJ | WAKE_SRC_ALL_MD32)
#define WAKE_SRC_FOR_MD32 0
#define spm_is_wakesrc_invalid(wakesrc) \
(!!((unsigned int)(wakesrc) & 0xc0003803))
const unsigned int spm_flags =
SPM_DUALVCORE_PDN_DIS | SPM_PASR_DIS | SPM_DPD_DIS |
SPM_CPU_DVS_DIS | SPM_OPT | SPM_INFRA_PDN_DIS;
enum wake_reason_t spm_wake_reason = WR_NONE;
/**********************************************************
* PCM sequence for cpu suspend
**********************************************************/
static const unsigned int suspend_binary_ca7[] = {
0x81f58407, 0x81f68407, 0x803a0400, 0x803a8400, 0x1b80001f, 0x20000000,
0x80300400, 0x80318400, 0x80328400, 0xa1d28407, 0x81f20407, 0x81409801,
0xd8000245, 0x17c07c1f, 0x18c0001f, 0x10006234, 0xc0c031a0, 0x1200041f,
0x80310400, 0x1b80001f, 0x2000000a, 0xa0110400, 0x18c0001f, 0x100062c8,
0xe0e00010, 0xe0e00030, 0xe0e00070, 0xe0e000f0, 0x1b80001f, 0x2000001a,
0xe0e00ff0, 0xe8208000, 0x10006354, 0xfffe7fff, 0xe8208000, 0x10006834,
0x00000010, 0x81f00407, 0xa1dd0407, 0x81fd0407, 0xc2803780, 0x1290041f,
0x8880000c, 0x2f7be75f, 0xd8200642, 0x17c07c1f, 0x1b00001f, 0x7fffe7ff,
0xd0000680, 0x17c07c1f, 0x1b00001f, 0x7ffff7ff, 0xf0000000, 0x17c07c1f,
0x80880001, 0xd8000762, 0x17c07c1f, 0xd00027a0, 0x1200041f, 0xe8208000,
0x10006834, 0x00000000, 0x1b00001f, 0x3fffe7ff, 0x1b80001f, 0x20000004,
0xd820092c, 0x17c07c1f, 0xe8208000, 0x10006834, 0x00000010, 0xd00011a0,
0x17c07c1f, 0x18c0001f, 0x10006608, 0x1910001f, 0x10006608, 0x813b0404,
0xe0c00004, 0x1880001f, 0x10006320, 0xc0c03680, 0xe080000f, 0xd8200b23,
0x17c07c1f, 0x1b00001f, 0x7ffff7ff, 0xd00011a0, 0x17c07c1f, 0xe080001f,
0xe8208000, 0x10006354, 0xffffffff, 0x18c0001f, 0x100062c8, 0xe0e000f0,
0xe0e00030, 0xe0e00000, 0x81409801, 0xd8000fe5, 0x17c07c1f, 0x18c0001f,
0x10004094, 0x1910001f, 0x1020e374, 0xe0c00004, 0x18c0001f, 0x10004098,
0x1910001f, 0x1020e378, 0xe0c00004, 0x18c0001f, 0x10011094, 0x1910001f,
0x10213374, 0xe0c00004, 0x18c0001f, 0x10011098, 0x1910001f, 0x10213378,
0xe0c00004, 0x1910001f, 0x10213378, 0x18c0001f, 0x10006234, 0xc0c03360,
0x17c07c1f, 0xc2803780, 0x1290841f, 0xa1d20407, 0x81f28407, 0xa1d68407,
0xa0128400, 0xa0118400, 0xa0100400, 0xa01a8400, 0xa01a0400, 0x19c0001f,
0x001c239f, 0x1b00001f, 0x3fffefff, 0xf0000000, 0x17c07c1f, 0x808d8001,
0xd8201422, 0x17c07c1f, 0x803d8400, 0x1b80001f, 0x2000001a, 0x80340400,
0x17c07c1f, 0x17c07c1f, 0x80310400, 0x81fa0407, 0x81f18407, 0x81f08407,
0xa1dc0407, 0x1b80001f, 0x200000b6, 0xd00020e0, 0x17c07c1f, 0x1880001f,
0x20000208, 0x81411801, 0xd8001605, 0x17c07c1f, 0xe8208000, 0x1000f600,
0xd2000000, 0x1380081f, 0x18c0001f, 0x10006240, 0xe0e00016, 0xe0e0001e,
0xe0e0000e, 0xe0e0000f, 0x80368400, 0x1380081f, 0x80370400, 0x1380081f,
0x80360400, 0x803e0400, 0x1380081f, 0x80380400, 0x803b0400, 0xa01d8400,
0x1b80001f, 0x20000034, 0x803d8400, 0x1b80001f, 0x20000152, 0x803d0400,
0x1380081f, 0x18c0001f, 0x1000f5c8, 0x1910001f, 0x1000f5c8, 0xa1000404,
0xe0c00004, 0x18c0001f, 0x100125c8, 0x1910001f, 0x100125c8, 0xa1000404,
0xe0c00004, 0x1910001f, 0x100125c8, 0x80340400, 0x17c07c1f, 0x17c07c1f,
0x80310400, 0xe8208000, 0x10000044, 0x00000100, 0x1b80001f, 0x20000068,
0x1b80001f, 0x2000000a, 0x18c0001f, 0x10006240, 0xe0e0000d, 0xd8001e65,
0x17c07c1f, 0x18c0001f, 0x100040f4, 0x1910001f, 0x100040f4, 0xa11c8404,
0xe0c00004, 0x1b80001f, 0x2000000a, 0x813c8404, 0xe0c00004, 0x18c0001f,
0x100110f4, 0x1910001f, 0x100110f4, 0xa11c8404, 0xe0c00004, 0x1b80001f,
0x2000000a, 0x813c8404, 0xe0c00004, 0x1b80001f, 0x20000100, 0x81fa0407,
0x81f18407, 0x81f08407, 0xe8208000, 0x10006354, 0xfffe7b47, 0x18c0001f,
0x65930003, 0xc0c03080, 0x17c07c1f, 0xa1d80407, 0xa1dc0407, 0x18c0001f,
0x10006608, 0x1910001f, 0x10006608, 0xa11b0404, 0xe0c00004, 0xc2803780,
0x1291041f, 0x8880000c, 0x2f7be75f, 0xd8202222, 0x17c07c1f, 0x1b00001f,
0x3fffe7ff, 0xd0002260, 0x17c07c1f, 0x1b00001f, 0xbfffe7ff, 0xf0000000,
0x17c07c1f, 0x1890001f, 0x10006608, 0x808b0801, 0xd8202502, 0x17c07c1f,
0x1880001f, 0x10006320, 0xc0c03400, 0xe080000f, 0xd8002663, 0x17c07c1f,
0xe080001f, 0xa1da0407, 0x81fc0407, 0xa0110400, 0xa0140400, 0xa01d8400,
0xd0002fc0, 0x17c07c1f, 0x1b80001f, 0x20000fdf, 0x1890001f, 0x10006608,
0x80c98801, 0x810a8801, 0x10918c1f, 0xa0939002, 0x8080080d, 0xd82027a2,
0x12007c1f, 0x1b00001f, 0x3fffe7ff, 0x1b80001f, 0x20000004, 0xd800304c,
0x17c07c1f, 0x1b00001f, 0xbfffe7ff, 0xd0003040, 0x17c07c1f, 0x81f80407,
0x81fc0407, 0x18c0001f, 0x65930006, 0xc0c03080, 0x17c07c1f, 0x18c0001f,
0x65930007, 0xc0c03080, 0x17c07c1f, 0x1880001f, 0x10006320, 0xc0c03400,
0xe080000f, 0xd8002663, 0x17c07c1f, 0xe080001f, 0x18c0001f, 0x65930005,
0xc0c03080, 0x17c07c1f, 0xa1da0407, 0xe8208000, 0x10000048, 0x00000100,
0x1b80001f, 0x20000068, 0xa0110400, 0xa0140400, 0x18c0001f, 0x1000f5c8,
0x1910001f, 0x1000f5c8, 0x81200404, 0xe0c00004, 0x18c0001f, 0x100125c8,
0x1910001f, 0x100125c8, 0x81200404, 0xe0c00004, 0x1910001f, 0x100125c8,
0xa01d0400, 0xa01b0400, 0xa0180400, 0x803d8400, 0xa01e0400, 0xa0160400,
0xa0170400, 0xa0168400, 0x1b80001f, 0x20000104, 0x81411801, 0xd8002f85,
0x17c07c1f, 0x18c0001f, 0x10006240, 0xc0c03360, 0x17c07c1f, 0xe8208000,
0x1000f600, 0xd2000001, 0xd8000768, 0x17c07c1f, 0xc2803780, 0x1291841f,
0x1b00001f, 0x7ffff7ff, 0xf0000000, 0x17c07c1f, 0x1900001f, 0x10006830,
0xe1000003, 0x18c0001f, 0x10006834, 0xe0e00000, 0xe0e00001, 0xf0000000,
0x17c07c1f, 0xe0f07f16, 0x1380201f, 0xe0f07f1e, 0x1380201f, 0xe0f07f0e,
0x1b80001f, 0x20000104, 0xe0f07f0c, 0xe0f07f0d, 0xe0f07e0d, 0xe0f07c0d,
0xe0f0780d, 0xf0000000, 0xe0f0700d, 0xe0f07f0d, 0xe0f07f0f, 0xe0f07f1e,
0xf0000000, 0xe0f07f12, 0x11407c1f, 0x81f08407, 0x81f18407, 0x1b80001f,
0x20000001, 0xa1d08407, 0xa1d18407, 0x1392841f, 0x812ab401, 0x80ebb401,
0xa0c00c04, 0xd8203603, 0x17c07c1f, 0x80c01403, 0xd8203423, 0x01400405,
0x1900001f, 0x10006814, 0xf0000000, 0xe1000003, 0xa1d00407, 0x1b80001f,
0x20000208, 0x80ea3401, 0x1a00001f, 0x10006814, 0xf0000000, 0xe2000003,
0x18c0001f, 0x10006b6c, 0x1910001f, 0x10006b6c, 0xa1002804, 0xf0000000,
0xe0c00004, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f, 0x17c07c1f,
0x17c07c1f, 0x17c07c1f, 0x1840001f, 0x00000001, 0xa1d48407, 0x1990001f,
0x10006b08, 0x1a50001f, 0x10006610, 0x8246a401, 0xe8208000, 0x10006b6c,
0x00000000, 0x1b00001f, 0x2f7be75f, 0x81469801, 0xd8004305, 0x17c07c1f,
0x1b80001f, 0xd00f0000, 0x8880000c, 0x2f7be75f, 0xd8005d62, 0x17c07c1f,
0xd0004340, 0x17c07c1f, 0x1b80001f, 0x500f0000, 0xe8208000, 0x10006354,
0xfffe7b47, 0xc0c06900, 0x81401801, 0xd80048a5, 0x17c07c1f, 0x81f60407,
0x18c0001f, 0x10006200, 0xc0c05e20, 0x12807c1f, 0xe8208000, 0x1000625c,
0x00000001, 0x1b80001f, 0x20000080, 0xc0c05e20, 0x1280041f, 0x18c0001f,
0x10006204, 0xc0c061c0, 0x1280041f, 0x18c0001f, 0x10006208, 0xc0c05e20,
0x12807c1f, 0xe8208000, 0x10006244, 0x00000001, 0x1b80001f, 0x20000080,
0xc0c05e20, 0x1280041f, 0x18c0001f, 0x10006290, 0xc0c05e20, 0x1280041f,
0xe8208000, 0x10006404, 0x00003101, 0xc2803780, 0x1292041f, 0x81469801,
0xd8204a05, 0x17c07c1f, 0x1b00001f, 0x2f7be75f, 0x1b80001f, 0x30000004,
0x8880000c, 0x2f7be75f, 0xd80057c2, 0x17c07c1f, 0xc0c06480, 0x17c07c1f,
0x18c0001f, 0x10006294, 0xe0f07fff, 0xe0e00fff, 0xe0e000ff, 0x81449801,
0xd8004c45, 0x17c07c1f, 0x1a00001f, 0x10006604, 0xe2200003, 0xc0c06540,
0x17c07c1f, 0xe2200005, 0xc0c06540, 0x17c07c1f, 0xa1d38407, 0xa1d98407,
0x1800001f, 0x00000012, 0x1800001f, 0x00000e12, 0x1800001f, 0x03800e12,
0x1800001f, 0x038e0e12, 0xe8208000, 0x10006310, 0x0b1600f8, 0x1b00001f,
0xbfffe7ff, 0x1b80001f, 0x90100000, 0x80c00400, 0xd8204f63, 0xa1d58407,
0xa1dd8407, 0x1b00001f, 0x3fffefff, 0xd0004e20, 0x17c07c1f, 0x1890001f,
0x100063e8, 0x88c0000c, 0x2f7be75f, 0xd8005183, 0x17c07c1f, 0x80c40001,
0xd8005103, 0x17c07c1f, 0x1b00001f, 0xbfffe7ff, 0xd0005140, 0x17c07c1f,
0x1b00001f, 0x7ffff7ff, 0xd0004e20, 0x17c07c1f, 0x80c40001, 0xd8205283,
0x17c07c1f, 0xa1de0407, 0x1b00001f, 0x7fffe7ff, 0xd0004e20, 0x17c07c1f,
0x18c0001f, 0x10006294, 0xe0e001fe, 0xe0e003fc, 0xe0e007f8, 0xe0e00ff0,
0x1b80001f, 0x20000020, 0xe0f07ff0, 0xe0f07f00, 0x81449801, 0xd8005565,
0x17c07c1f, 0x1a00001f, 0x10006604, 0xe2200002, 0xc0c06540, 0x17c07c1f,
0xe2200004, 0xc0c06540, 0x17c07c1f, 0x1b80001f, 0x200016a8, 0x1800001f,
0x03800e12, 0x1b80001f, 0x20000300, 0x1800001f, 0x00000e12, 0x1b80001f,
0x20000300, 0x1800001f, 0x00000012, 0x1b80001f, 0x20000104, 0x10007c1f,
0x81f38407, 0x81f98407, 0x81f90407, 0x81f40407, 0x1b80001f, 0x200016a8,
0x81401801, 0xd8005d65, 0x17c07c1f, 0xe8208000, 0x10006404, 0x00002101,
0x18c0001f, 0x10006290, 0x1212841f, 0xc0c05fa0, 0x12807c1f, 0xc0c05fa0,
0x1280041f, 0x18c0001f, 0x10006208, 0x1212841f, 0xc0c05fa0, 0x12807c1f,
0xe8208000, 0x10006244, 0x00000000, 0x1b80001f, 0x20000080, 0xc0c05fa0,
0x1280041f, 0xe8208000, 0x10200268, 0x000ffffe, 0x18c0001f, 0x10006204,
0x1212841f, 0xc0c06300, 0x1280041f, 0x18c0001f, 0x10006200, 0x1212841f,
0xc0c05fa0, 0x12807c1f, 0xe8208000, 0x1000625c, 0x00000000, 0x1b80001f,
0x20000080, 0xc0c05fa0, 0x1280041f, 0x19c0001f, 0x01411820, 0x1ac0001f,
0x55aa55aa, 0x10007c1f, 0xf0000000, 0xd8005eca, 0x17c07c1f, 0xe2e0004f,
0xe2e0006f, 0xe2e0002f, 0xd8205f6a, 0x17c07c1f, 0xe2e0002e, 0xe2e0003e,
0xe2e00032, 0xf0000000, 0x17c07c1f, 0xd800606a, 0x17c07c1f, 0xe2e00036,
0xe2e0003e, 0x1380201f, 0xe2e0003c, 0xd820618a, 0x17c07c1f, 0x1380201f,
0xe2e0007c, 0x1b80001f, 0x20000003, 0xe2e0005c, 0xe2e0004c, 0xe2e0004d,
0xf0000000, 0x17c07c1f, 0xd82062c9, 0x17c07c1f, 0xe2e0000d, 0xe2e0000c,
0xe2e0001c, 0xe2e0001e, 0xe2e00016, 0xe2e00012, 0xf0000000, 0x17c07c1f,
0xd8206449, 0x17c07c1f, 0xe2e00016, 0x1380201f, 0xe2e0001e, 0x1380201f,
0xe2e0001c, 0x1380201f, 0xe2e0000c, 0xe2e0000d, 0xf0000000, 0x17c07c1f,
0xa1d40407, 0x1391841f, 0xa1d90407, 0x1393041f, 0xf0000000, 0x17c07c1f,
0x18d0001f, 0x10006604, 0x10cf8c1f, 0xd8206543, 0x17c07c1f, 0xf0000000,
0x17c07c1f, 0xe8208000, 0x11008014, 0x00000002, 0xe8208000, 0x11008020,
0x00000101, 0xe8208000, 0x11008004, 0x000000d0, 0x1a00001f, 0x11008000,
0xd800680a, 0xe220005d, 0xd820682a, 0xe2200000, 0xe2200001, 0xe8208000,
0x11008024, 0x00000001, 0x1b80001f, 0x20000424, 0xf0000000, 0x17c07c1f,
0xa1d10407, 0x1b80001f, 0x20000020, 0xf0000000, 0x17c07c1f
};
/*
* PCM binary for suspend scenario
*/
static const struct pcm_desc suspend_pcm_ca7 = {
.version = "pcm_suspend_v32.18_20140721_mt8173_v00.03_MD32_EMPTY_CA7",
.base = suspend_binary_ca7,
.size = 845,
.sess = 2,
.replace = 0,
.vec0 = EVENT_VEC(11, 1, 0, 0),
.vec1 = EVENT_VEC(12, 1, 0, 54),
.vec2 = EVENT_VEC(30, 1, 0, 143),
.vec3 = EVENT_VEC(31, 1, 0, 277),
};
/*
* SPM settings for suspend scenario
*/
static struct pwr_ctrl spm_ctrl = {
.wake_src = WAKE_SRC_FOR_SUSPEND,
.wake_src_md32 = WAKE_SRC_FOR_MD32,
.r0_ctrl_en = 1,
.r7_ctrl_en = 1,
.infra_dcm_lock = 1,
.wfi_op = WFI_OP_AND,
.pcm_apsrc_req = 0,
.ca7top_idle_mask = 0,
.ca15top_idle_mask = 0,
.mcusys_idle_mask = 0,
.disp_req_mask = 0,
.mfg_req_mask = 0,
.md32_req_mask = 1,
.srclkenai_mask = 1,
.ca7_wfi0_en = 1,
.ca7_wfi1_en = 1,
.ca7_wfi2_en = 1,
.ca7_wfi3_en = 1,
.ca15_wfi0_en = 1,
.ca15_wfi1_en = 1,
.ca15_wfi2_en = 1,
.ca15_wfi3_en = 1,
};
/*
* go_to_sleep_before_wfi() - trigger SPM to enter suspend scenario
*/
static void go_to_sleep_before_wfi(const unsigned int spm_flags)
{
struct pwr_ctrl *pwrctrl;
pwrctrl = &spm_ctrl;
set_pwrctrl_pcm_flags(pwrctrl, spm_flags);
spm_set_sysclk_settle();
INFO("sec = %u, wakesrc = 0x%x (%u)(%u)\n",
pwrctrl->timer_val, pwrctrl->wake_src,
is_cpu_pdn(pwrctrl->pcm_flags),
is_infra_pdn(pwrctrl->pcm_flags));
spm_reset_and_init_pcm();
spm_init_pcm_register();
spm_set_power_control(pwrctrl);
spm_set_wakeup_event(pwrctrl);
spm_kick_pcm_to_run(pwrctrl);
spm_init_event_vector(&suspend_pcm_ca7);
spm_kick_im_to_fetch(&suspend_pcm_ca7);
}
/*
* go_to_sleep_after_wfi() - get wakeup reason after
* leaving suspend scenario and clean up SPM settings
*/
static enum wake_reason_t go_to_sleep_after_wfi(void)
{
struct wake_status wakesta;
static enum wake_reason_t last_wr = WR_NONE;
spm_get_wakeup_status(&wakesta);
spm_clean_after_wakeup();
last_wr = spm_output_wake_reason(&wakesta);
return last_wr;
}
void spm_system_suspend(void)
{
spm_lock_get();
go_to_sleep_before_wfi(spm_flags);
set_suspend_ready();
spm_lock_release();
}
void spm_system_suspend_finish(void)
{
spm_lock_get();
spm_wake_reason = go_to_sleep_after_wfi();
INFO("spm_wake_reason=%d\n", spm_wake_reason);
clear_all_ready();
spm_lock_release();
}

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/*
* Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* Neither the name of ARM nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __SPM_SUSPEND_H__
#define __SPM_SUSPEND_H__
/* cpu dormant return code */
#define CPU_DORMANT_RESET 0
#define CPU_DORMANT_ABORT 1
void spm_system_suspend(void);
void spm_system_suspend_finish(void);
#endif /* __SPM_SUSPEND_H__*/

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/*
* Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* Neither the name of ARM nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#include <arch_helpers.h>
#include <mcucfg.h>
#include <mmio.h>
#include <mt8173_def.h>
#include <mt_cpuxgpt.h>
static void write_cpuxgpt(unsigned int reg_index, unsigned int value)
{
mmio_write_32((uintptr_t)&mt8173_mcucfg->xgpt_idx, reg_index);
mmio_write_32((uintptr_t)&mt8173_mcucfg->xgpt_ctl, value);
}
static void cpuxgpt_set_init_cnt(unsigned int countH, unsigned int countL)
{
write_cpuxgpt(INDEX_CNT_H_INIT, countH);
/* update count when countL programmed */
write_cpuxgpt(INDEX_CNT_L_INIT, countL);
}
void generic_timer_backup(void)
{
uint64_t cval;
cval = read_cntpct_el0();
cpuxgpt_set_init_cnt((uint32_t)(cval >> 32),
(uint32_t)(cval & 0xffffffff));
}

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/*
* Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* Neither the name of ARM nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __MT_CPUXGPT_H__
#define __MT_CPUXGPT_H__
/* REG */
#define INDEX_CNT_L_INIT 0x008
#define INDEX_CNT_H_INIT 0x00C
void generic_timer_backup(void);
#endif /* __MT_CPUXGPT_H__ */

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/*
* Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* Neither the name of ARM nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#include <asm_macros.S>
#include <uart8250.h>
.globl console_core_init
.globl console_core_putc
.globl console_core_getc
/* -----------------------------------------------
* int console_core_init(unsigned long base_addr,
* unsigned int uart_clk, unsigned int baud_rate)
* Function to initialize the console without a
* C Runtime to print debug information. This
* function will be accessed by console_init and
* crash reporting.
* In: x0 - console base address
* w1 - Uart clock in Hz
* w2 - Baud rate
* Out: return 1 on success else 0 on error
* Clobber list : x1, x2, x3
* -----------------------------------------------
*/
func console_core_init
/* Check the input base address */
cbz x0, core_init_fail
/* Check baud rate and uart clock for sanity */
cbz w1, core_init_fail
cbz w2, core_init_fail
/* Disable interrupt */
str wzr, [x0, #UART_IER]
/* Force DTR and RTS to high */
mov w3, #(UART_MCR_DTR | UART_MCR_RTS)
str w3, [x0, #UART_MCR]
/* Check high speed */
movz w3, #:abs_g1:115200
movk w3, #:abs_g0_nc:115200
cmp w2, w3
b.hi 1f
/* Non high speed */
lsl w2, w2, #4
mov w3, wzr
b 2f
/* High speed */
1: lsl w2, w2, #2
mov w3, #2
/* Set high speed UART register */
2: str w3, [x0, #UART_HIGHSPEED]
/* Calculate divisor */
udiv w3, w1, w2 /* divisor = uartclk / (quot * baudrate) */
msub w1, w3, w2, w1 /* remainder = uartclk % (quot * baudrate) */
lsr w2, w2, #1
cmp w1, w2
cinc w3, w3, hs
/* Set line configuration, access divisor latches */
mov w1, #(UART_LCR_DLAB | UART_LCR_WLS_8)
str w1, [x0, #UART_LCR]
/* Set the divisor */
and w1, w3, #0xff
str w1, [x0, #UART_DLL]
lsr w1, w3, #8
and w1, w1, #0xff
str w1, [x0, #UART_DLH]
/* Hide the divisor latches */
mov w1, #UART_LCR_WLS_8
str w1, [x0, #UART_LCR]
/* Enable FIFOs, and clear receive and transmit */
mov w1, #(UART_FCR_FIFO_EN | UART_FCR_CLEAR_RCVR | \
UART_FCR_CLEAR_XMIT)
str w1, [x0, #UART_FCR]
mov w0, #1
ret
core_init_fail:
mov w0, wzr
ret
endfunc console_core_init
/* --------------------------------------------------------
* int console_core_putc(int c, unsigned long base_addr)
* Function to output a character over the console. It
* returns the character printed on success or -1 on error.
* In : w0 - character to be printed
* x1 - console base address
* Out : return -1 on error else return character.
* Clobber list : x2
* --------------------------------------------------------
*/
func console_core_putc
/* Check the input parameter */
cbz x1, putc_error
/* Prepend '\r' to '\n' */
cmp w0, #0xA
b.ne 2f
/* Check if the transmit FIFO is full */
1: ldr w2, [x1, #UART_LSR]
and w2, w2, #UART_LSR_THRE
cbz w2, 1b
mov w2, #0xD
str w2, [x1, #UART_THR]
/* Check if the transmit FIFO is full */
2: ldr w2, [x1, #UART_LSR]
and w2, w2, #UART_LSR_THRE
cbz w2, 2b
str w0, [x1, #UART_THR]
ret
putc_error:
mov w0, #-1
ret
endfunc console_core_putc
/* ---------------------------------------------
* int console_core_getc(unsigned long base_addr)
* Function to get a character from the console.
* It returns the character grabbed on success
* or -1 on error.
* In : x0 - console base address
* Clobber list : x0, x1
* ---------------------------------------------
*/
func console_core_getc
cbz x0, getc_error
/* Check if the receive FIFO is empty */
1: ldr w1, [x0, #UART_LSR]
tbz w1, #UART_LSR_DR, 1b
ldr w0, [x0, #UART_RBR]
ret
getc_error:
mov w0, #-1
ret
endfunc console_core_getc

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/*
* Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* Neither the name of ARM nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __UART8250_H__
#define __UART8250_H__
/* UART register */
#define UART_RBR 0x00 /* Receive buffer register */
#define UART_DLL 0x00 /* Divisor latch lsb */
#define UART_THR 0x00 /* Transmit holding register */
#define UART_DLH 0x04 /* Divisor latch msb */
#define UART_IER 0x04 /* Interrupt enable register */
#define UART_FCR 0x08 /* FIFO control register */
#define UART_LCR 0x0c /* Line control register */
#define UART_MCR 0x10 /* Modem control register */
#define UART_LSR 0x14 /* Line status register */
#define UART_HIGHSPEED 0x24 /* High speed UART */
/* FCR */
#define UART_FCR_FIFO_EN 0x01 /* enable FIFO */
#define UART_FCR_CLEAR_RCVR 0x02 /* clear the RCVR FIFO */
#define UART_FCR_CLEAR_XMIT 0x04 /* clear the XMIT FIFO */
/* LCR */
#define UART_LCR_WLS_8 0x03 /* 8 bit character length */
#define UART_LCR_DLAB 0x80 /* divisor latch access bit */
/* MCR */
#define UART_MCR_DTR 0x01
#define UART_MCR_RTS 0x02
/* LSR */
#define UART_LSR_DR 0x01 /* Data ready */
#define UART_LSR_THRE 0x20 /* Xmit holding register empty */
#endif /* __UART8250_H__ */

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/*
* Copyright (c) 2014-2015, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* Neither the name of ARM nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __MCUCFG_H__
#define __MCUCFG_H__
#include <mt8173_def.h>
#include <stdint.h>
struct mt8173_mcucfg_regs {
uint32_t mp0_ca7l_cache_config;
struct {
uint32_t mem_delsel0;
uint32_t mem_delsel1;
} mp0_cpu[4];
uint32_t mp0_cache_mem_delsel0;
uint32_t mp0_cache_mem_delsel1;
uint32_t mp0_axi_config;
uint32_t mp0_misc_config[2];
struct {
uint32_t rv_addr_lw;
uint32_t rv_addr_hw;
} mp0_rv_addr[4];
uint32_t mp0_ca7l_cfg_dis;
uint32_t mp0_ca7l_clken_ctrl;
uint32_t mp0_ca7l_rst_ctrl;
uint32_t mp0_ca7l_misc_config;
uint32_t mp0_ca7l_dbg_pwr_ctrl;
uint32_t mp0_rw_rsvd0;
uint32_t mp0_rw_rsvd1;
uint32_t mp0_ro_rsvd;
uint32_t reserved0_0[100];
uint32_t mp1_cpucfg;
uint32_t mp1_miscdbg;
uint32_t reserved0_1[13];
uint32_t mp1_rst_ctl;
uint32_t mp1_clkenm_div;
uint32_t reserved0_2[7];
uint32_t mp1_config_res;
uint32_t reserved0_3[13];
struct {
uint32_t rv_addr_lw;
uint32_t rv_addr_hw;
} mp1_rv_addr[2];
uint32_t reserved0_4[84];
uint32_t mp0_rst_status; /* 0x400 */
uint32_t mp0_dbg_ctrl;
uint32_t mp0_dbg_flag;
uint32_t mp0_ca7l_ir_mon;
struct {
uint32_t pc_lw;
uint32_t pc_hw;
uint32_t fp_arch32;
uint32_t sp_arch32;
uint32_t fp_arch64_lw;
uint32_t fp_arch64_hw;
uint32_t sp_arch64_lw;
uint32_t sp_arch64_hw;
} mp0_dbg_core[4];
uint32_t dfd_ctrl;
uint32_t dfd_cnt_l;
uint32_t dfd_cnt_h;
uint32_t misccfg_mp0_rw_rsvd;
uint32_t misccfg_sec_vio_status0;
uint32_t misccfg_sec_vio_status1;
uint32_t reserved1[22];
uint32_t misccfg_rw_rsvd; /* 0x500 */
uint32_t mcusys_dbg_mon_sel_a;
uint32_t mcusys_dbg_mon;
uint32_t reserved2[61];
uint32_t mcusys_config_a; /* 0x600 */
uint32_t mcusys_config1_a;
uint32_t mcusys_gic_peribase_a;
uint32_t reserved3;
uint32_t sec_range0_start; /* 0x610 */
uint32_t sec_range0_end;
uint32_t sec_range_enable;
uint32_t reserved4;
uint32_t int_pol_ctl[8]; /* 0x620 */
uint32_t aclken_div; /* 0x640 */
uint32_t pclken_div;
uint32_t l2c_sram_ctrl;
uint32_t armpll_jit_ctrl;
uint32_t cci_addrmap; /* 0x650 */
uint32_t cci_config;
uint32_t cci_periphbase;
uint32_t cci_nevntcntovfl;
uint32_t cci_clk_ctrl; /* 0x660 */
uint32_t cci_acel_s1_ctrl;
uint32_t bus_fabric_dcm_ctrl;
uint32_t reserved5;
uint32_t xgpt_ctl; /* 0x670 */
uint32_t xgpt_idx;
uint32_t ptpod2_ctl0;
uint32_t ptpod2_ctl1;
uint32_t mcusys_revid;
uint32_t mcusys_rw_rsvd0;
uint32_t mcusys_rw_rsvd1;
};
static struct mt8173_mcucfg_regs *const mt8173_mcucfg = (void *)MCUCFG_BASE;
/* cpu boot mode */
enum {
MP0_CPUCFG_64BIT_SHIFT = 12,
MP1_CPUCFG_64BIT_SHIFT = 28,
MP0_CPUCFG_64BIT = 0xf << MP0_CPUCFG_64BIT_SHIFT,
MP1_CPUCFG_64BIT = 0xf << MP1_CPUCFG_64BIT_SHIFT
};
/* scu related */
enum {
MP0_ACINACTM_SHIFT = 4,
MP1_ACINACTM_SHIFT = 0,
MP0_ACINACTM = 1 << MP0_ACINACTM_SHIFT,
MP1_ACINACTM = 1 << MP1_ACINACTM_SHIFT
};
enum {
MP1_DIS_RGU0_WAIT_PD_CPUS_L1_ACK_SHIFT = 0,
MP1_DIS_RGU1_WAIT_PD_CPUS_L1_ACK_SHIFT = 4,
MP1_DIS_RGU2_WAIT_PD_CPUS_L1_ACK_SHIFT = 8,
MP1_DIS_RGU3_WAIT_PD_CPUS_L1_ACK_SHIFT = 12,
MP1_DIS_RGU_NOCPU_WAIT_PD_CPUS_L1_ACK_SHIFT = 16,
MP1_DIS_RGU0_WAIT_PD_CPUS_L1_ACK =
0xf << MP1_DIS_RGU0_WAIT_PD_CPUS_L1_ACK_SHIFT,
MP1_DIS_RGU1_WAIT_PD_CPUS_L1_ACK =
0xf << MP1_DIS_RGU1_WAIT_PD_CPUS_L1_ACK_SHIFT,
MP1_DIS_RGU2_WAIT_PD_CPUS_L1_ACK =
0xf << MP1_DIS_RGU2_WAIT_PD_CPUS_L1_ACK_SHIFT,
MP1_DIS_RGU3_WAIT_PD_CPUS_L1_ACK =
0xf << MP1_DIS_RGU3_WAIT_PD_CPUS_L1_ACK_SHIFT,
MP1_DIS_RGU_NOCPU_WAIT_PD_CPUS_L1_ACK =
0xf << MP1_DIS_RGU_NOCPU_WAIT_PD_CPUS_L1_ACK_SHIFT
};
enum {
MP1_AINACTS_SHIFT = 4,
MP1_AINACTS = 1 << MP1_AINACTS_SHIFT
};
enum {
MP1_SW_CG_GEN_SHIFT = 12,
MP1_SW_CG_GEN = 1 << MP1_SW_CG_GEN_SHIFT
};
enum {
MP1_L2RSTDISABLE_SHIFT = 14,
MP1_L2RSTDISABLE = 1 << MP1_L2RSTDISABLE_SHIFT
};
#endif /* __MCUCFG_H__ */

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/*
* Copyright (c) 2014-2015, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* Neither the name of ARM nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#include <cci.h>
#include <gic_v2.h>
#include <mt8173_def.h>
.section .rodata.gic_reg_name, "aS"
gicc_regs:
.asciz "gicc_hppir", "gicc_ahppir", "gicc_ctlr", ""
gicd_pend_reg:
.asciz "gicd_ispendr regs (Offsets 0x200 - 0x278)\n" \
" Offset:\t\t\tvalue\n"
newline:
.asciz "\n"
spacer:
.asciz ":\t\t0x"
/* ---------------------------------------------
* The below macro prints out relevant GIC
* registers whenever an unhandled exception is
* taken in BL3-1.
* Clobbers: x0 - x10, x16, x17, sp
* ---------------------------------------------
*/
.macro plat_print_gic_regs
mov_imm x16, BASE_GICD_BASE
mov_imm x17, BASE_GICC_BASE
/* Load the gicc reg list to x6 */
adr x6, gicc_regs
/* Load the gicc regs to gp regs used by str_in_crash_buf_print */
ldr w8, [x17, #GICC_HPPIR]
ldr w9, [x17, #GICC_AHPPIR]
ldr w10, [x17, #GICC_CTLR]
/* Store to the crash buf and print to console */
bl str_in_crash_buf_print
/* Print the GICD_ISPENDR regs */
add x7, x16, #GICD_ISPENDR
adr x4, gicd_pend_reg
bl asm_print_str
gicd_ispendr_loop:
sub x4, x7, x16
cmp x4, #0x280
b.eq exit_print_gic_regs
bl asm_print_hex
adr x4, spacer
bl asm_print_str
ldr x4, [x7], #8
bl asm_print_hex
adr x4, newline
bl asm_print_str
b gicd_ispendr_loop
exit_print_gic_regs:
.endm
.section .rodata.cci_reg_name, "aS"
cci_iface_regs:
.asciz "cci_snoop_ctrl_cluster0", "cci_snoop_ctrl_cluster1" , ""
/* ------------------------------------------------
* The below macro prints out relevant interconnect
* registers whenever an unhandled exception is
* taken in BL3-1.
* Clobbers: x0 - x9, sp
* ------------------------------------------------
*/
.macro plat_print_interconnect_regs
adr x6, cci_iface_regs
/* Store in x7 the base address of the first interface */
mov_imm x7, (PLAT_MT_CCI_BASE + SLAVE_IFACE_OFFSET( \
PLAT_MT_CCI_CLUSTER0_SL_IFACE_IX))
ldr w8, [x7, #SNOOP_CTRL_REG]
/* Store in x7 the base address of the second interface */
mov_imm x7, (PLAT_MT_CCI_BASE + SLAVE_IFACE_OFFSET( \
PLAT_MT_CCI_CLUSTER1_SL_IFACE_IX))
ldr w9, [x7, #SNOOP_CTRL_REG]
/* Store to the crash buf and print to console */
bl str_in_crash_buf_print
.endm

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/*
* Copyright (c) 2014-2015, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* Neither the name of ARM nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __PLATFORM_DEF_H__
#define __PLATFORM_DEF_H__
#define DEBUG_XLAT_TABLE 0
/*******************************************************************************
* Platform binary types for linking
******************************************************************************/
#define PLATFORM_LINKER_FORMAT "elf64-littleaarch64"
#define PLATFORM_LINKER_ARCH aarch64
/*******************************************************************************
* Generic platform constants
******************************************************************************/
/* Size of cacheable stacks */
#if DEBUG_XLAT_TABLE
#define PLATFORM_STACK_SIZE 0x800
#elif IMAGE_BL1
#define PLATFORM_STACK_SIZE 0x440
#elif IMAGE_BL2
#define PLATFORM_STACK_SIZE 0x400
#elif IMAGE_BL31
#define PLATFORM_STACK_SIZE 0x800
#elif IMAGE_BL32
#define PLATFORM_STACK_SIZE 0x440
#endif
#define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n"
#define PLATFORM_MAX_AFFLVL MPIDR_AFFLVL2
#define PLATFORM_SYSTEM_COUNT 1
#define PLATFORM_CLUSTER_COUNT 2
#define PLATFORM_CLUSTER0_CORE_COUNT 4
#define PLATFORM_CLUSTER1_CORE_COUNT 2
#define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER1_CORE_COUNT + \
PLATFORM_CLUSTER0_CORE_COUNT)
#define PLATFORM_MAX_CPUS_PER_CLUSTER 4
#define PLATFORM_NUM_AFFS (PLATFORM_SYSTEM_COUNT + \
PLATFORM_CLUSTER_COUNT + \
PLATFORM_CORE_COUNT)
/*******************************************************************************
* Platform memory map related constants
******************************************************************************/
/* TF txet, ro, rw, internal SRAM, Size: release: 80KB, debug: 92KB */
#define TZRAM_BASE (0x100000)
#if DEBUG
#define TZRAM_SIZE (0x20000)
#else
#define TZRAM_SIZE (0x20000)
#endif
/* xlat_table , coherence ram, 64KB */
#define TZRAM2_BASE (TZRAM_BASE + TZRAM_SIZE)
#define TZRAM2_SIZE (0x10000)
/*******************************************************************************
* BL31 specific defines.
******************************************************************************/
/*
* Put BL3-1 at the top of the Trusted SRAM (just below the shared memory, if
* present). BL31_BASE is calculated using the current BL3-1 debug size plus a
* little space for growth.
*/
#define BL31_BASE (TZRAM_BASE + 0x1000)
#define BL31_LIMIT (TZRAM_BASE + TZRAM_SIZE)
#define TZRAM2_LIMIT (TZRAM2_BASE + TZRAM2_SIZE)
/*******************************************************************************
* Platform specific page table and MMU setup constants
******************************************************************************/
#define ADDR_SPACE_SIZE (1ull << 32)
#define MAX_XLAT_TABLES 4
#define MAX_MMAP_REGIONS 16
/*******************************************************************************
* Declarations and constants to access the mailboxes safely. Each mailbox is
* aligned on the biggest cache line size in the platform. This is known only
* to the platform as it might have a combination of integrated and external
* caches. Such alignment ensures that two maiboxes do not sit on the same cache
* line at any cache level. They could belong to different cpus/clusters &
* get written while being protected by different locks causing corruption of
* a valid mailbox address.
******************************************************************************/
#define CACHE_WRITEBACK_SHIFT 6
#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT)
#endif /* __PLATFORM_DEF_H__ */

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/*
* Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* Neither the name of ARM nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __POWER_TRACER_H__
#define __POWER_TRACER_H__
#define CPU_UP 0
#define CPU_DOWN 1
#define CPU_SUSPEND 2
#define CLUSTER_UP 3
#define CLUSTER_DOWN 4
#define CLUSTER_SUSPEND 5
void trace_power_flow(unsigned long mpidr, unsigned char mode);
#endif

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/*
* Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* Neither the name of ARM nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __SCU_H__
#define __SCU_H__
void disable_scu(unsigned long mpidr);
void enable_scu(unsigned long mpidr);
#endif

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/*
* Copyright (c) 2014-2015, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* Neither the name of ARM nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __PLAT_DEF_H__
#define __PLAT_DEF_H__
#define MT8173_PRIMARY_CPU 0x0
/* Special value used to verify platform parameters from BL2 to BL3-1 */
#define MT_BL31_PLAT_PARAM_VAL 0x0f1e2d3c4b5a6978ULL
#define IO_PHYS (0x10000000)
#define INFRACFG_AO_BASE (IO_PHYS + 0x1000)
#define GPIO_BASE (IO_PHYS + 0x5000)
#define SPM_BASE (IO_PHYS + 0x6000)
#define RGU_BASE (IO_PHYS + 0x7000)
#define PMIC_WRAP_BASE (IO_PHYS + 0xD000)
#define MCUCFG_BASE (IO_PHYS + 0x200000)
#define TRNG_base (IO_PHYS + 0x20F000)
#define MT_GIC_BASE (IO_PHYS + 0x220000)
#define PLAT_MT_CCI_BASE (IO_PHYS + 0x390000)
/* Aggregate of all devices in the first GB */
#define MTK_DEV_RNG0_BASE IO_PHYS
#define MTK_DEV_RNG0_SIZE 0x400000
#define MTK_DEV_RNG1_BASE (IO_PHYS + 0x1000000)
#define MTK_DEV_RNG1_SIZE 0x4000000
/*******************************************************************************
* UART related constants
******************************************************************************/
#define MT8173_UART0_BASE (IO_PHYS + 0x01002000)
#define MT8173_UART1_BASE (IO_PHYS + 0x01003000)
#define MT8173_UART2_BASE (IO_PHYS + 0x01004000)
#define MT8173_UART3_BASE (IO_PHYS + 0x01005000)
#define MT8173_BAUDRATE (115200)
#define MT8173_UART_CLOCK (26000000)
/*******************************************************************************
* System counter frequency related constants
******************************************************************************/
#define SYS_COUNTER_FREQ_IN_TICKS 13000000
#define SYS_COUNTER_FREQ_IN_MHZ 13
/*******************************************************************************
* GIC-400 & interrupt handling related constants
******************************************************************************/
/* Base MTK_platform compatible GIC memory map */
#define BASE_GICD_BASE (MT_GIC_BASE + 0x1000)
#define BASE_GICC_BASE (MT_GIC_BASE + 0x2000)
#define BASE_GICR_BASE 0 /* no GICR in GIC-400 */
#define BASE_GICH_BASE (MT_GIC_BASE + 0x4000)
#define BASE_GICV_BASE (MT_GIC_BASE + 0x6000)
#define INT_POL_CTL0 0x10200620
#define GIC_PRIVATE_SIGNALS (32)
/*******************************************************************************
* CCI-400 related constants
******************************************************************************/
#define PLAT_MT_CCI_CLUSTER0_SL_IFACE_IX 4
#define PLAT_MT_CCI_CLUSTER1_SL_IFACE_IX 3
/*******************************************************************************
* WDT related constants
******************************************************************************/
#define MTK_WDT_BASE (RGU_BASE + 0)
#define MTK_WDT_SWRST (MTK_WDT_BASE + 0x0014)
#define MTK_WDT_MODE_DUAL_MODE 0x0040
#define MTK_WDT_MODE_IRQ 0x0008
#define MTK_WDT_MODE_KEY 0x22000000
#define MTK_WDT_MODE_EXTEN 0x0004
#define MTK_WDT_SWRST_KEY 0x1209
/* FIQ platform related define */
#define MT_IRQ_SEC_SGI_0 8
#define MT_IRQ_SEC_SGI_1 9
#define MT_IRQ_SEC_SGI_2 10
#define MT_IRQ_SEC_SGI_3 11
#define MT_IRQ_SEC_SGI_4 12
#define MT_IRQ_SEC_SGI_5 13
#define MT_IRQ_SEC_SGI_6 14
#define MT_IRQ_SEC_SGI_7 15
#endif /* __PLAT_DEF_H__ */

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/*
* Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* Neither the name of ARM nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#include <arch_helpers.h>
#include <delay_timer.h>
#include <mt8173_def.h>
static uint32_t plat_get_timer_value(void)
{
/* Generic delay timer implementation expects the timer to be a down
* counter. We apply bitwise NOT operator to the tick values returned
* by read_cntpct_el0() to simulate the down counter. */
return (uint32_t)(~read_cntpct_el0());
}
static const timer_ops_t plat_timer_ops = {
.get_timer_value = plat_get_timer_value,
.clk_mult = 1,
.clk_div = SYS_COUNTER_FREQ_IN_MHZ,
};
void plat_delay_timer_init(void)
{
timer_init(&plat_timer_ops);
}

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/*
* Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* Neither the name of ARM nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#include <arm_gic.h>
#include <bl_common.h>
#include <mt8173_def.h>
const unsigned int mt_irq_sec_array[] = {
MT_IRQ_SEC_SGI_0,
MT_IRQ_SEC_SGI_1,
MT_IRQ_SEC_SGI_2,
MT_IRQ_SEC_SGI_3,
MT_IRQ_SEC_SGI_4,
MT_IRQ_SEC_SGI_5,
MT_IRQ_SEC_SGI_6,
MT_IRQ_SEC_SGI_7
};
void plat_mt_gic_init(void)
{
arm_gic_init(BASE_GICC_BASE,
BASE_GICD_BASE,
BASE_GICR_BASE,
mt_irq_sec_array,
ARRAY_SIZE(mt_irq_sec_array));
}

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/*
* Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* Neither the name of ARM nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#include <arch_helpers.h>
#include <arm_gic.h>
#include <assert.h>
#include <bakery_lock.h>
#include <cci.h>
#include <console.h>
#include <debug.h>
#include <errno.h>
#include <gpio.h>
#include <mcucfg.h>
#include <mmio.h>
#include <mt8173_def.h>
#include <mt_cpuxgpt.h> /* generic_timer_backup() */
#include <plat_private.h>
#include <power_tracer.h>
#include <psci.h>
#include <rtc.h>
#include <scu.h>
#include <spm_hotplug.h>
#include <spm_mcdi.h>
#include <spm_suspend.h>
struct core_context {
unsigned long timer_data[8];
unsigned int count;
unsigned int rst;
unsigned int abt;
unsigned int brk;
};
struct cluster_context {
struct core_context core[PLATFORM_MAX_CPUS_PER_CLUSTER];
};
/*
* Top level structure to hold the complete context of a multi cluster system
*/
struct system_context {
struct cluster_context cluster[PLATFORM_CLUSTER_COUNT];
};
/*
* Top level structure which encapsulates the context of the entire system
*/
static struct system_context dormant_data[1];
static inline struct cluster_context *system_cluster(
struct system_context *system,
uint32_t clusterid)
{
return &system->cluster[clusterid];
}
static inline struct core_context *cluster_core(struct cluster_context *cluster,
uint32_t cpuid)
{
return &cluster->core[cpuid];
}
static struct cluster_context *get_cluster_data(unsigned long mpidr)
{
uint32_t clusterid;
clusterid = (mpidr & MPIDR_CLUSTER_MASK) >> MPIDR_AFFINITY_BITS;
return system_cluster(dormant_data, clusterid);
}
static struct core_context *get_core_data(unsigned long mpidr)
{
struct cluster_context *cluster;
uint32_t cpuid;
cluster = get_cluster_data(mpidr);
cpuid = mpidr & MPIDR_CPU_MASK;
return cluster_core(cluster, cpuid);
}
static void mt_save_generic_timer(unsigned long *container)
{
uint64_t ctl;
uint64_t val;
__asm__ volatile("mrs %x0, cntkctl_el1\n\t"
"mrs %x1, cntp_cval_el0\n\t"
"stp %x0, %x1, [%2, #0]"
: "=&r" (ctl), "=&r" (val)
: "r" (container)
: "memory");
__asm__ volatile("mrs %x0, cntp_tval_el0\n\t"
"mrs %x1, cntp_ctl_el0\n\t"
"stp %x0, %x1, [%2, #16]"
: "=&r" (val), "=&r" (ctl)
: "r" (container)
: "memory");
__asm__ volatile("mrs %x0, cntv_tval_el0\n\t"
"mrs %x1, cntv_ctl_el0\n\t"
"stp %x0, %x1, [%2, #32]"
: "=&r" (val), "=&r" (ctl)
: "r" (container)
: "memory");
}
static void mt_restore_generic_timer(unsigned long *container)
{
uint64_t ctl;
uint64_t val;
__asm__ volatile("ldp %x0, %x1, [%2, #0]\n\t"
"msr cntkctl_el1, %x0\n\t"
"msr cntp_cval_el0, %x1"
: "=&r" (ctl), "=&r" (val)
: "r" (container)
: "memory");
__asm__ volatile("ldp %x0, %x1, [%2, #16]\n\t"
"msr cntp_tval_el0, %x0\n\t"
"msr cntp_ctl_el0, %x1"
: "=&r" (val), "=&r" (ctl)
: "r" (container)
: "memory");
__asm__ volatile("ldp %x0, %x1, [%2, #32]\n\t"
"msr cntv_tval_el0, %x0\n\t"
"msr cntv_ctl_el0, %x1"
: "=&r" (val), "=&r" (ctl)
: "r" (container)
: "memory");
}
static inline uint64_t read_cntpctl(void)
{
uint64_t cntpctl;
__asm__ volatile("mrs %x0, cntp_ctl_el0"
: "=r" (cntpctl) : : "memory");
return cntpctl;
}
static inline void write_cntpctl(uint64_t cntpctl)
{
__asm__ volatile("msr cntp_ctl_el0, %x0" : : "r"(cntpctl));
}
static void stop_generic_timer(void)
{
/*
* Disable the timer and mask the irq to prevent
* suprious interrupts on this cpu interface. It
* will bite us when we come back if we don't. It
* will be replayed on the inbound cluster.
*/
uint64_t cntpctl = read_cntpctl();
write_cntpctl(clr_cntp_ctl_enable(cntpctl));
}
static void mt_cpu_save(unsigned long mpidr)
{
struct core_context *core;
core = get_core_data(mpidr);
mt_save_generic_timer(core->timer_data);
/* disable timer irq, and upper layer should enable it again. */
stop_generic_timer();
}
static void mt_cpu_restore(unsigned long mpidr)
{
struct core_context *core;
core = get_core_data(mpidr);
mt_restore_generic_timer(core->timer_data);
}
static void mt_platform_save_context(unsigned long mpidr)
{
/* mcusys_save_context: */
mt_cpu_save(mpidr);
}
static void mt_platform_restore_context(unsigned long mpidr)
{
/* mcusys_restore_context: */
mt_cpu_restore(mpidr);
}
/*******************************************************************************
* Private function which is used to determine if any platform actions
* should be performed for the specified affinity instance given its
* state. Nothing needs to be done if the 'state' is not off or if this is not
* the highest affinity level which will enter the 'state'.
*******************************************************************************/
static int32_t plat_do_plat_actions(unsigned int afflvl, unsigned int state)
{
unsigned int max_phys_off_afflvl;
assert(afflvl <= MPIDR_AFFLVL2);
if (state != PSCI_STATE_OFF)
return -EAGAIN;
/*
* Find the highest affinity level which will be suspended and postpone
* all the platform specific actions until that level is hit.
*/
max_phys_off_afflvl = psci_get_max_phys_off_afflvl();
assert(max_phys_off_afflvl != PSCI_INVALID_DATA);
if (afflvl != max_phys_off_afflvl)
return -EAGAIN;
return 0;
}
/*******************************************************************************
* MTK_platform handler called when an affinity instance is about to enter
* standby.
******************************************************************************/
static void plat_affinst_standby(unsigned int power_state)
{
unsigned int target_afflvl;
/* Sanity check the requested state */
target_afflvl = psci_get_pstate_afflvl(power_state);
/*
* It's possible to enter standby only on affinity level 0 i.e. a cpu
* on the MTK_platform. Ignore any other affinity level.
*/
if (target_afflvl == MPIDR_AFFLVL0) {
/*
* Enter standby state. dsb is good practice before using wfi
* to enter low power states.
*/
dsb();
wfi();
}
}
/*******************************************************************************
* MTK_platform handler called when an affinity instance is about to be turned
* on. The level and mpidr determine the affinity instance.
******************************************************************************/
static int plat_affinst_on(unsigned long mpidr,
unsigned long sec_entrypoint,
unsigned int afflvl,
unsigned int state)
{
int rc = PSCI_E_SUCCESS;
unsigned long cpu_id;
unsigned long cluster_id;
uintptr_t rv;
/*
* It's possible to turn on only affinity level 0 i.e. a cpu
* on the MTK_platform. Ignore any other affinity level.
*/
if (afflvl != MPIDR_AFFLVL0)
return rc;
cpu_id = mpidr & MPIDR_CPU_MASK;
cluster_id = mpidr & MPIDR_CLUSTER_MASK;
if (cluster_id)
rv = (uintptr_t)&mt8173_mcucfg->mp1_rv_addr[cpu_id].rv_addr_lw;
else
rv = (uintptr_t)&mt8173_mcucfg->mp0_rv_addr[cpu_id].rv_addr_lw;
mmio_write_32(rv, sec_entrypoint);
INFO("mt_on[%ld:%ld], entry %x\n",
cluster_id, cpu_id, mmio_read_32(rv));
spm_hotplug_on(mpidr);
return rc;
}
/*******************************************************************************
* MTK_platform handler called when an affinity instance is about to be turned
* off. The level and mpidr determine the affinity instance. The 'state' arg.
* allows the platform to decide whether the cluster is being turned off and
* take apt actions.
*
* CAUTION: This function is called with coherent stacks so that caches can be
* turned off, flushed and coherency disabled. There is no guarantee that caches
* will remain turned on across calls to this function as each affinity level is
* dealt with. So do not write & read global variables across calls. It will be
* wise to do flush a write to the global to prevent unpredictable results.
******************************************************************************/
static void plat_affinst_off(unsigned int afflvl, unsigned int state)
{
unsigned long mpidr = read_mpidr_el1();
/* Determine if any platform actions need to be executed. */
if (plat_do_plat_actions(afflvl, state) == -EAGAIN)
return;
/* Prevent interrupts from spuriously waking up this cpu */
arm_gic_cpuif_deactivate();
spm_hotplug_off(mpidr);
trace_power_flow(mpidr, CPU_DOWN);
if (afflvl != MPIDR_AFFLVL0) {
/* Disable coherency if this cluster is to be turned off */
plat_cci_disable();
trace_power_flow(mpidr, CLUSTER_DOWN);
}
}
/*******************************************************************************
* MTK_platform handler called when an affinity instance is about to be
* suspended. The level and mpidr determine the affinity instance. The 'state'
* arg. allows the platform to decide whether the cluster is being turned off
* and take apt actions.
*
* CAUTION: This function is called with coherent stacks so that caches can be
* turned off, flushed and coherency disabled. There is no guarantee that caches
* will remain turned on across calls to this function as each affinity level is
* dealt with. So do not write & read global variables across calls. It will be
* wise to do flush a write to the global to prevent unpredictable results.
******************************************************************************/
static void plat_affinst_suspend(unsigned long sec_entrypoint,
unsigned int afflvl,
unsigned int state)
{
unsigned long mpidr = read_mpidr_el1();
unsigned long cluster_id;
unsigned long cpu_id;
uintptr_t rv;
/* Determine if any platform actions need to be executed. */
if (plat_do_plat_actions(afflvl, state) == -EAGAIN)
return;
cpu_id = mpidr & MPIDR_CPU_MASK;
cluster_id = mpidr & MPIDR_CLUSTER_MASK;
if (cluster_id)
rv = (uintptr_t)&mt8173_mcucfg->mp1_rv_addr[cpu_id].rv_addr_lw;
else
rv = (uintptr_t)&mt8173_mcucfg->mp0_rv_addr[cpu_id].rv_addr_lw;
mmio_write_32(rv, sec_entrypoint);
if (afflvl == MPIDR_AFFLVL0)
spm_mcdi_prepare(mpidr);
if (afflvl >= MPIDR_AFFLVL0)
mt_platform_save_context(mpidr);
/* Perform the common cluster specific operations */
if (afflvl >= MPIDR_AFFLVL1) {
/* Disable coherency if this cluster is to be turned off */
plat_cci_disable();
disable_scu(mpidr);
trace_power_flow(mpidr, CLUSTER_SUSPEND);
}
if (afflvl >= MPIDR_AFFLVL2) {
generic_timer_backup();
spm_system_suspend();
/* Prevent interrupts from spuriously waking up this cpu */
arm_gic_cpuif_deactivate();
}
}
/*******************************************************************************
* MTK_platform handler called when an affinity instance has just been powered
* on after being turned off earlier. The level and mpidr determine the affinity
* instance. The 'state' arg. allows the platform to decide whether the cluster
* was turned off prior to wakeup and do what's necessary to setup it up
* correctly.
******************************************************************************/
static void plat_affinst_on_finish(unsigned int afflvl, unsigned int state)
{
unsigned long mpidr = read_mpidr_el1();
/* Determine if any platform actions need to be executed. */
if (plat_do_plat_actions(afflvl, state) == -EAGAIN)
return;
/* Perform the common cluster specific operations */
if (afflvl >= MPIDR_AFFLVL1) {
enable_scu(mpidr);
/* Enable coherency if this cluster was off */
plat_cci_enable();
trace_power_flow(mpidr, CLUSTER_UP);
}
/* Enable the gic cpu interface */
arm_gic_cpuif_setup();
arm_gic_pcpu_distif_setup();
trace_power_flow(mpidr, CPU_UP);
}
/*******************************************************************************
* MTK_platform handler called when an affinity instance has just been powered
* on after having been suspended earlier. The level and mpidr determine the
* affinity instance.
******************************************************************************/
static void plat_affinst_suspend_finish(unsigned int afflvl, unsigned int state)
{
unsigned long mpidr = read_mpidr_el1();
/* Determine if any platform actions need to be executed. */
if (plat_do_plat_actions(afflvl, state) == -EAGAIN)
return;
if (afflvl >= MPIDR_AFFLVL2) {
/* Enable the gic cpu interface */
arm_gic_setup();
arm_gic_cpuif_setup();
spm_system_suspend_finish();
}
/* Perform the common cluster specific operations */
if (afflvl >= MPIDR_AFFLVL1) {
enable_scu(mpidr);
/* Enable coherency if this cluster was off */
plat_cci_enable();
trace_power_flow(mpidr, CLUSTER_UP);
}
if (afflvl >= MPIDR_AFFLVL0)
mt_platform_restore_context(mpidr);
if (afflvl == MPIDR_AFFLVL0)
spm_mcdi_finish(mpidr);
arm_gic_pcpu_distif_setup();
}
static unsigned int plat_get_sys_suspend_power_state(void)
{
/* StateID: 0, StateType: 1(power down), PowerLevel: 2(system) */
return psci_make_powerstate(0, 1, 2);
}
/*******************************************************************************
* MTK handlers to shutdown/reboot the system
******************************************************************************/
static void __dead2 plat_system_off(void)
{
INFO("MTK System Off\n");
gpio_set(GPIO120, GPIO_OUT_ZERO);
rtc_bbpu_power_down();
wfi();
ERROR("MTK System Off: operation not handled.\n");
panic();
}
static void __dead2 plat_system_reset(void)
{
/* Write the System Configuration Control Register */
INFO("MTK System Reset\n");
mmio_clrbits_32(MTK_WDT_BASE,
(MTK_WDT_MODE_DUAL_MODE | MTK_WDT_MODE_IRQ));
mmio_setbits_32(MTK_WDT_BASE, (MTK_WDT_MODE_KEY | MTK_WDT_MODE_EXTEN));
mmio_setbits_32(MTK_WDT_SWRST, MTK_WDT_SWRST_KEY);
wfi();
ERROR("MTK System Reset: operation not handled.\n");
panic();
}
/*******************************************************************************
* Export the platform handlers to enable psci to invoke them
******************************************************************************/
static const plat_pm_ops_t plat_plat_pm_ops = {
.affinst_standby = plat_affinst_standby,
.affinst_on = plat_affinst_on,
.affinst_off = plat_affinst_off,
.affinst_suspend = plat_affinst_suspend,
.affinst_on_finish = plat_affinst_on_finish,
.affinst_suspend_finish = plat_affinst_suspend_finish,
.system_off = plat_system_off,
.system_reset = plat_system_reset,
.get_sys_suspend_power_state = plat_get_sys_suspend_power_state,
};
/*******************************************************************************
* Export the platform specific power ops & initialize the mtk_platform power
* controller
******************************************************************************/
int platform_setup_pm(const plat_pm_ops_t **plat_ops)
{
*plat_ops = &plat_plat_pm_ops;
return 0;
}

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/*
* Copyright (c) 2014-2015, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* Neither the name of ARM nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __PLAT_PRIVATE_H__
#define __PLAT_PRIVATE_H__
/*******************************************************************************
* Function and variable prototypes
******************************************************************************/
void plat_configure_mmu_el3(unsigned long total_base,
unsigned long total_size,
unsigned long,
unsigned long,
unsigned long,
unsigned long);
void plat_cci_init(void);
void plat_cci_enable(void);
void plat_cci_disable(void);
/* Declarations for plat_mt_gic.c */
void plat_mt_gic_init(void);
/* Declarations for plat_topology.c */
int mt_setup_topology(void);
void plat_delay_timer_init(void);
#endif /* __PLAT_PRIVATE_H__ */

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/*
* Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* Neither the name of ARM nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#include <mmio.h>
#include <mtk_sip_svc.h>
/* Authorized secure register list */
enum {
SREG_HDMI_COLOR_EN = 0x14000904
};
static const uint32_t authorized_sreg[] = {
SREG_HDMI_COLOR_EN
};
#define authorized_sreg_cnt \
(sizeof(authorized_sreg) / sizeof(authorized_sreg[0]))
uint64_t mt_sip_set_authorized_sreg(uint32_t sreg, uint32_t val)
{
uint64_t i;
for (i = 0; i < authorized_sreg_cnt; i++) {
if (authorized_sreg[i] == sreg) {
mmio_write_32(sreg, val);
return MTK_SIP_E_SUCCESS;
}
}
return MTK_SIP_E_INVALID_PARAM;
}

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/*
* Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* Neither the name of ARM nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#include <arch.h>
#include <psci.h>
unsigned int plat_get_aff_count(unsigned int aff_lvl, unsigned long mpidr)
{
/* Report 1 (absent) instance at levels higher that the cluster level */
if (aff_lvl > MPIDR_AFFLVL1)
return 1;
if (aff_lvl == MPIDR_AFFLVL1)
return 2; /* We have two clusters */
return mpidr & 0x100 ? 2 : 2; /* 2 cpus in cluster 1, 2 in cluster 0 */
}
unsigned int plat_get_aff_state(unsigned int aff_lvl, unsigned long mpidr)
{
return aff_lvl <= MPIDR_AFFLVL2 ? PSCI_AFF_PRESENT : PSCI_AFF_ABSENT;
}
int mt_setup_topology(void)
{
/* [TODO] Make topology configurable via SCC */
return 0;
}

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#
# Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are met:
#
# Redistributions of source code must retain the above copyright notice, this
# list of conditions and the following disclaimer.
#
# Redistributions in binary form must reproduce the above copyright notice,
# this list of conditions and the following disclaimer in the documentation
# and/or other materials provided with the distribution.
#
# Neither the name of ARM nor the names of its contributors may be used
# to endorse or promote products derived from this software without specific
# prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
# POSSIBILITY OF SUCH DAMAGE.
#
MTK_PLAT := plat/mediatek
MTK_PLAT_SOC := ${MTK_PLAT}/${PLAT}
PLAT_INCLUDES := -I${MTK_PLAT}/common/ \
-I${MTK_PLAT_SOC}/ \
-I${MTK_PLAT_SOC}/drivers/gpio/ \
-I${MTK_PLAT_SOC}/drivers/mtcmos/ \
-I${MTK_PLAT_SOC}/drivers/pmic/ \
-I${MTK_PLAT_SOC}/drivers/rtc/ \
-I${MTK_PLAT_SOC}/drivers/spm/ \
-I${MTK_PLAT_SOC}/drivers/timer/ \
-I${MTK_PLAT_SOC}/drivers/uart/ \
-I${MTK_PLAT_SOC}/include/
PLAT_BL_COMMON_SOURCES := lib/aarch64/xlat_tables.c \
plat/common/aarch64/plat_common.c \
plat/common/plat_gic.c
BL31_SOURCES += drivers/arm/cci/cci.c \
drivers/arm/gic/arm_gic.c \
drivers/arm/gic/gic_v2.c \
drivers/arm/gic/gic_v3.c \
drivers/console/console.S \
drivers/delay_timer/delay_timer.c \
lib/cpus/aarch64/aem_generic.S \
lib/cpus/aarch64/cortex_a53.S \
lib/cpus/aarch64/cortex_a57.S \
lib/cpus/aarch64/cortex_a72.S \
plat/common/aarch64/platform_mp_stack.S \
${MTK_PLAT}/common/mtk_sip_svc.c \
${MTK_PLAT_SOC}/aarch64/plat_helpers.S \
${MTK_PLAT_SOC}/aarch64/platform_common.c \
${MTK_PLAT_SOC}/bl31_plat_setup.c \
${MTK_PLAT_SOC}/drivers/gpio/gpio.c \
${MTK_PLAT_SOC}/drivers/mtcmos/mtcmos.c \
${MTK_PLAT_SOC}/drivers/pmic/pmic_wrap_init.c \
${MTK_PLAT_SOC}/drivers/rtc/rtc.c \
${MTK_PLAT_SOC}/drivers/spm/spm.c \
${MTK_PLAT_SOC}/drivers/spm/spm_hotplug.c \
${MTK_PLAT_SOC}/drivers/spm/spm_mcdi.c \
${MTK_PLAT_SOC}/drivers/spm/spm_suspend.c \
${MTK_PLAT_SOC}/drivers/timer/mt_cpuxgpt.c \
${MTK_PLAT_SOC}/drivers/uart/8250_console.S \
${MTK_PLAT_SOC}/plat_delay_timer.c \
${MTK_PLAT_SOC}/plat_mt_gic.c \
${MTK_PLAT_SOC}/plat_pm.c \
${MTK_PLAT_SOC}/plat_sip_calls.c \
${MTK_PLAT_SOC}/plat_topology.c \
${MTK_PLAT_SOC}/power_tracer.c \
${MTK_PLAT_SOC}/scu.c
# Flag used by the MTK_platform port to determine the version of ARM GIC
# architecture to use for interrupt management in EL3.
ARM_GIC_ARCH := 2
$(eval $(call add_define,ARM_GIC_ARCH))
# Enable workarounds for selected Cortex-A53 erratas.
ERRATA_A53_826319 := 1
ERRATA_A53_836870 := 1
# indicate the reset vector address can be programmed
PROGRAMMABLE_RESET_ADDRESS := 1

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plat/mediatek/mt8173/power_tracer.c Normal file
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/*
* Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* Neither the name of ARM nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#include <arch.h>
#include <debug.h>
#include <power_tracer.h>
#define trace_log(...) INFO("psci: " __VA_ARGS__)
void trace_power_flow(unsigned long mpidr, unsigned char mode)
{
switch (mode) {
case CPU_UP:
trace_log("core %ld:%ld ON\n",
(mpidr & MPIDR_CLUSTER_MASK) >> MPIDR_AFFINITY_BITS,
(mpidr & MPIDR_CPU_MASK));
break;
case CPU_DOWN:
trace_log("core %ld:%ld OFF\n",
(mpidr & MPIDR_CLUSTER_MASK) >> MPIDR_AFFINITY_BITS,
(mpidr & MPIDR_CPU_MASK));
break;
case CPU_SUSPEND:
trace_log("core %ld:%ld SUSPEND\n",
(mpidr & MPIDR_CLUSTER_MASK) >> MPIDR_AFFINITY_BITS,
(mpidr & MPIDR_CPU_MASK));
break;
case CLUSTER_UP:
trace_log("cluster %ld ON\n",
(mpidr & MPIDR_CLUSTER_MASK) >> MPIDR_AFFINITY_BITS);
break;
case CLUSTER_DOWN:
trace_log("cluster %ld OFF\n",
(mpidr & MPIDR_CLUSTER_MASK) >> MPIDR_AFFINITY_BITS);
break;
case CLUSTER_SUSPEND:
trace_log("cluster %ld SUSPEND\n",
(mpidr & MPIDR_CLUSTER_MASK) >> MPIDR_AFFINITY_BITS);
break;
default:
trace_log("unknown power mode\n");
break;
}
}

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/*
* Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* Neither the name of ARM nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#include <arch.h>
#include <mcucfg.h>
#include <mmio.h>
void disable_scu(unsigned long mpidr)
{
if (mpidr & MPIDR_CLUSTER_MASK)
mmio_setbits_32((uintptr_t)&mt8173_mcucfg->mp1_miscdbg,
MP1_ACINACTM);
else
mmio_setbits_32((uintptr_t)&mt8173_mcucfg->mp0_axi_config,
MP0_ACINACTM);
}
void enable_scu(unsigned long mpidr)
{
if (mpidr & MPIDR_CLUSTER_MASK)
mmio_clrbits_32((uintptr_t)&mt8173_mcucfg->mp1_miscdbg,
MP1_ACINACTM);
else
mmio_clrbits_32((uintptr_t)&mt8173_mcucfg->mp0_axi_config,
MP0_ACINACTM);
}