fix(el3-runtime): set unset pstate bits to default
During a transition to a higher EL some of the PSTATE bits are not set by hardware, this means that their state may be leaked from lower ELs. This patch sets those bits to a default value upon entry to EL3. This patch was tested using a debugger to check the PSTATE values are correctly set. As well as adding a test in the next patch to ensure the PSTATE in lower ELs is still maintained after this change. Change-Id: Ie546acbca7b9aa3c86bd68185edded91b2a64ae5 Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>
This commit is contained in:
Daniel Boulby
parent
97215e0f25
commit
7d33ffe4c1
6
Makefile
6
Makefile
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@ -277,6 +277,10 @@ ifeq "8.6" "$(word 1, $(sort 8.6 $(ARM_ARCH_MAJOR).$(ARM_ARCH_MINOR)))"
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ENABLE_FEAT_ECV = 1
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endif
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ifeq "8.4" "$(word 1, $(sort 8.4 $(ARM_ARCH_MAJOR).$(ARM_ARCH_MINOR)))"
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ENABLE_FEAT_DIT = 1
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endif
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ifneq ($(findstring armclang,$(notdir $(CC))),)
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TF_CFLAGS_aarch32 = -target arm-arm-none-eabi $(march32-directive)
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TF_CFLAGS_aarch64 = -target aarch64-arm-none-eabi $(march64-directive)
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@ -1040,6 +1044,7 @@ $(eval $(call assert_booleans,\
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USE_SP804_TIMER \
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ENABLE_FEAT_RNG \
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ENABLE_FEAT_SB \
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ENABLE_FEAT_DIT \
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PSA_FWU_SUPPORT \
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ENABLE_TRBE_FOR_NS \
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ENABLE_SYS_REG_TRACE_FOR_NS \
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@ -1154,6 +1159,7 @@ $(eval $(call add_defines,\
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USE_SP804_TIMER \
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ENABLE_FEAT_RNG \
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ENABLE_FEAT_SB \
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ENABLE_FEAT_DIT \
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NR_OF_FW_BANKS \
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NR_OF_IMAGES_IN_FW_BANK \
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PSA_FWU_SUPPORT \
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@ -92,6 +92,7 @@ func enter_lower_el_sync_ea
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* Save general purpose and ARMv8.3-PAuth registers (if enabled).
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* If Secure Cycle Counter is not disabled in MDCR_EL3 when
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* ARMv8.5-PMU is implemented, save PMCR_EL0 and disable Cycle Counter.
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* Also set the PSTATE to a known state.
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*/
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bl prepare_el3_entry
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@ -139,6 +140,7 @@ handle_lower_el_async_ea:
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* Save general purpose and ARMv8.3-PAuth registers (if enabled).
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* If Secure Cycle Counter is not disabled in MDCR_EL3 when
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* ARMv8.5-PMU is implemented, save PMCR_EL0 and disable Cycle Counter.
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* Also set the PSTATE to a known state.
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*/
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bl prepare_el3_entry
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@ -71,6 +71,7 @@
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* Save general purpose and ARMv8.3-PAuth registers (if enabled).
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* If Secure Cycle Counter is not disabled in MDCR_EL3 when
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* ARMv8.5-PMU is implemented, save PMCR_EL0 and disable Cycle Counter.
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* Also set the PSTATE to a known state.
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*/
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bl prepare_el3_entry
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@ -209,6 +210,7 @@ exp_from_EL3:
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* Save general purpose and ARMv8.3-PAuth registers (if enabled).
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* If Secure Cycle Counter is not disabled in MDCR_EL3 when
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* ARMv8.5-PMU is implemented, save PMCR_EL0 and disable Cycle Counter.
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* Also set the PSTATE to a known state.
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*/
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bl prepare_el3_entry
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@ -462,6 +464,7 @@ smc_handler64:
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* Save general purpose and ARMv8.3-PAuth registers (if enabled).
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* If Secure Cycle Counter is not disabled in MDCR_EL3 when
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* ARMv8.5-PMU is implemented, save PMCR_EL0 and disable Cycle Counter.
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* Also set the PSTATE to a known state.
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*/
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bl prepare_el3_entry
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2015-2021, Arm Limited and Contributors. All rights reserved.
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* Copyright (c) 2015-2022, Arm Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -9,6 +9,7 @@
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#include <arch.h>
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#include <asm_macros.S>
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#include <assert_macros.S>
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#include <context.h>
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#include <lib/xlat_tables/xlat_tables_defs.h>
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@ -237,15 +238,20 @@
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/*
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* If Data Independent Timing (DIT) functionality is implemented,
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* always enable DIT in EL3
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* always enable DIT in EL3.
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* First assert that the FEAT_DIT build flag matches the feature id
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* register value for DIT.
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*/
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#if ENABLE_FEAT_DIT
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#if ENABLE_ASSERTIONS
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mrs x0, id_aa64pfr0_el1
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ubfx x0, x0, #ID_AA64PFR0_DIT_SHIFT, #ID_AA64PFR0_DIT_LENGTH
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cmp x0, #ID_AA64PFR0_DIT_SUPPORTED
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bne 1f
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ASM_ASSERT(eq)
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#endif /* ENABLE_ASSERTIONS */
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mov x0, #DIT_BIT
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msr DIT, x0
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1:
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#endif
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.endm
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/* -----------------------------------------------------------------------------
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@ -682,6 +682,22 @@ func fpregs_context_restore
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endfunc fpregs_context_restore
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#endif /* CTX_INCLUDE_FPREGS */
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/*
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* Set the PSTATE bits not set when the exception was taken as
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* described in the AArch64.TakeException() pseudocode function
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* in ARM DDI 0487F.c page J1-7635 to a default value.
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*/
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.macro set_unset_pstate_bits
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/*
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* If Data Independent Timing (DIT) functionality is implemented,
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* always enable DIT in EL3
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*/
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#if ENABLE_FEAT_DIT
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mov x8, #DIT_BIT
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msr DIT, x8
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#endif /* ENABLE_FEAT_DIT */
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.endm /* set_unset_pstate_bits */
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/* ------------------------------------------------------------------
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* The following macro is used to save and restore all the general
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* purpose and ARMv8.3-PAuth (if enabled) registers.
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@ -767,17 +783,26 @@ endfunc fpregs_context_restore
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stp x26, x27, [x19, #CTX_PACDBKEY_LO]
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stp x28, x29, [x19, #CTX_PACGAKEY_LO]
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#endif /* CTX_INCLUDE_PAUTH_REGS */
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.endm /* save_gp_pmcr_pauth_regs */
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/* -----------------------------------------------------------------
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* This function saves the context preparing entry to el3.
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* This function saves the context and sets the PSTATE to a known
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* state, preparing entry to el3.
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* Save all the general purpose and ARMv8.3-PAuth (if enabled)
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* registers.
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* Then set any of the PSTATE bits that are not set by hardware
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* according to the Aarch64.TakeException pseudocode in the Arm
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* Architecture Reference Manual to a default value for EL3.
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* clobbers: x17
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* -----------------------------------------------------------------
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*/
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func prepare_el3_entry
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save_gp_pmcr_pauth_regs
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/*
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* Set the PSTATE bits not described in the Aarch64.TakeException
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* pseudocode to their default values.
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*/
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set_unset_pstate_bits
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ret
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endfunc prepare_el3_entry
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@ -1,5 +1,5 @@
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#
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# Copyright (c) 2016-2021, Arm Limited. All rights reserved.
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# Copyright (c) 2016-2022, Arm Limited. All rights reserved.
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#
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# SPDX-License-Identifier: BSD-3-Clause
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#
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@ -145,6 +145,9 @@ ENABLE_FEAT_FGT := 0
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# Flag to enable access to the CNTPOFF_EL2 register
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ENABLE_FEAT_ECV := 0
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# Flag to enable use of the DIT feature.
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ENABLE_FEAT_DIT := 0
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# By default BL31 encryption disabled
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ENCRYPT_BL31 := 0
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