andrius
/
arm-trusted-firmware
1
0
Fork 0
Code Issues Pull Requests Releases Wiki Activity

fix(intel): define macros to handle buffer entries 

This patch defines a macro to handle Secure Device Manager's (SDM)
pointer to command & response buffer entries and convert them to the
correct physical address.

Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I4cf9f1d90e0d5ae4e1a2ce84165864b48c2862e7
This commit is contained in:
Abdul Halim, Muhammad Hadi Asyrafi 2020-06-05 15:12:29 +08:00 committed by Sieu Mun Tang
parent 108514ff71
commit 7db1895f0b
2 changed files with 10 additions and 12 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
plat/intel/soc/common/include/socfpga_mailbox.h
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2019-2020, Intel Corporation. All rights reserved.
* Copyright (c) 2019-2022, Intel Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -69,6 +69,7 @@
#define CMD_CASUAL 0
#define CMD_URGENT 1
#define MBOX_WORD_BYTE 4U
#define MBOX_RESP_BUFFER_SIZE 16
#define MBOX_CMD_BUFFER_SIZE 32
@ -108,6 +109,9 @@
/* Mailbox Macros */
#define MBOX_ENTRY_TO_ADDR(_buf, ptr) (MBOX_OFFSET + (MBOX_##_buf##_BUFFER) \
+ MBOX_WORD_BYTE * (ptr))
/* Mailbox interrupt flags and masks */
#define MBOX_INT_FLAG_COE 0x1
#define MBOX_INT_FLAG_RIE 0x2

16
plat/intel/soc/common/soc/socfpga_mailbox.c
View File

@ -59,9 +59,7 @@ static int write_mailbox_cmd_buffer(uint32_t *cin, uint32_t cout,
}
mdelay(10U);
} else {
mmio_write_32(MBOX_OFFSET + MBOX_CMD_BUFFER +
(*cin * 4), data);
(*cin)++;
mmio_write_32(MBOX_ENTRY_TO_ADDR(CMD, (*cin)++), data);
*cin %= MBOX_CMD_BUFFER_SIZE;
mmio_write_32(MBOX_OFFSET + MBOX_CIN, *cin);
break;
@ -144,8 +142,7 @@ int mailbox_read_response(unsigned int *job_id, uint32_t *response,
rout = mmio_read_32(MBOX_OFFSET + MBOX_ROUT);
if (rout != rin) {
resp_data = mmio_read_32(MBOX_OFFSET +
MBOX_RESP_BUFFER + ((rout++)*4U));
resp_data = mmio_read_32(MBOX_ENTRY_TO_ADDR(RESP, (rout)++));
rout %= MBOX_RESP_BUFFER_SIZE;
mmio_write_32(MBOX_OFFSET + MBOX_ROUT, rout);
@ -219,8 +216,8 @@ int mailbox_poll_response(uint32_t job_id, uint32_t urgent, uint32_t *response,
rout = mmio_read_32(MBOX_OFFSET + MBOX_ROUT);
while (rout != rin) {
resp_data = mmio_read_32(MBOX_OFFSET +
MBOX_RESP_BUFFER + ((rout++)*4U));
resp_data = mmio_read_32(MBOX_ENTRY_TO_ADDR(RESP,
(rout)++));
rout %= MBOX_RESP_BUFFER_SIZE;
mmio_write_32(MBOX_OFFSET + MBOX_ROUT, rout);
@ -264,9 +261,7 @@ unsigned int iterate_resp(uint32_t mbox_resp_len, uint32_t *resp_buf,
while (mbox_resp_len > 0U) {
timeout = 100U;
mbox_resp_len--;
resp_data = mmio_read_32(MBOX_OFFSET +
MBOX_RESP_BUFFER +
(rout)*4U);
resp_data = mmio_read_32(MBOX_ENTRY_TO_ADDR(RESP, (rout)++));
if ((resp_buf != NULL) && (resp_len != 0U)) {
*(resp_buf + total_resp_len)
@ -274,7 +269,6 @@ unsigned int iterate_resp(uint32_t mbox_resp_len, uint32_t *resp_buf,
resp_len--;
total_resp_len++;
}
rout++;
rout %= MBOX_RESP_BUFFER_SIZE;
mmio_write_32(MBOX_OFFSET + MBOX_ROUT, rout);