Tegra186: add Video memory carveout settings
This patch supports the TEGRA_SIP_NEW_VIDEOMEM_REGION SiP call to program new video memory carveout settings from the NS world. Change-Id: If9ed818fe71e6cb7461f225090105a4d8883b7a2 Signed-off-by: Wayne Lin <wlin@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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@ -36,6 +36,7 @@
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#include <debug.h>
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#include <errno.h>
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#include <mce.h>
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#include <memctrl.h>
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#include <runtime_svc.h>
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#include <t18x_ari.h>
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#include <tegra_private.h>
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@ -106,6 +107,32 @@ int plat_sip_handler(uint32_t smc_fid,
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return 0;
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case TEGRA_SIP_NEW_VIDEOMEM_REGION:
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/* clean up the high bits */
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x1 = (uint32_t)x1;
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x2 = (uint32_t)x2;
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/*
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* Check if Video Memory overlaps TZDRAM (contains bl31/bl32)
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* or falls outside of the valid DRAM range
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*/
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mce_ret = bl31_check_ns_address(x1, x2);
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if (mce_ret)
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return -ENOTSUP;
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/*
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* Check if Video Memory is aligned to 1MB.
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*/
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if ((x1 & 0xFFFFF) || (x2 & 0xFFFFF)) {
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ERROR("Unaligned Video Memory base address!\n");
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return -ENOTSUP;
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}
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/* new video memory carveout settings */
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tegra_memctrl_videomem_setup(x1, x2);
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return 0;
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default:
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ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid);
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break;
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