Merge pull request #274 from sandrine-bailleux/sb/juno-r1
Add support for Juno r1 in the platform reset handler
This commit is contained in:
commit
7e2d659e13
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@ -112,43 +112,88 @@ func platform_get_core_pos
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func platform_mem_init
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func platform_mem_init
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ret
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ret
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/* -----------------------------------------------------
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/* --------------------------------------------------------------------
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* void plat_reset_handler(void);
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* void plat_reset_handler(void);
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*
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*
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* Before adding code in this function, refer to the
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* Before adding code in this function, refer to the guidelines in
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* guidelines in docs/firmware-design.md to determine
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* docs/firmware-design.md to determine whether the code should reside
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* whether the code should reside within the
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* within the FIRST_RESET_HANDLER_CALL block or not.
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* FIRST_RESET_HANDLER_CALL block or not.
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*
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*
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* Implement workaround for defect id 831273 by enabling
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* For Juno r0:
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* an event stream every 65536 cycles and set the L2 RAM
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* - Implement workaround for defect id 831273 by enabling an event
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* latencies for Cortex-A57. This code is included only
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* stream every 65536 cycles.
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* when FIRST_RESET_HANDLER_CALL is defined since it
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* - Set the L2 Data RAM latency to 2 (i.e. 3 cycles) for Cortex-A57
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* should be executed only during BL1.
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* - Set the L2 Tag RAM latency to 2 (i.e. 3 cycles) for Cortex-A57
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* -----------------------------------------------------
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*
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* For Juno r1:
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* - Set the L2 Data RAM latency to 2 (i.e. 3 cycles) for Cortex-A57
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* Note that:
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* - The default value for the L2 Tag RAM latency for Cortex-A57 is
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* suitable.
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* - Defect #831273 doesn't affect Juno r1.
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*
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* This code is included only when FIRST_RESET_HANDLER_CALL is defined
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* since it should be executed only during BL1.
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* --------------------------------------------------------------------
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*/
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*/
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func plat_reset_handler
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func plat_reset_handler
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#ifdef FIRST_RESET_HANDLER_CALL
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#ifdef FIRST_RESET_HANDLER_CALL
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/* Read the MIDR_EL1 */
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/* --------------------------------------------------------------------
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* Determine whether this code is running on Juno r0 or Juno r1.
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* Keep this information in x2.
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* --------------------------------------------------------------------
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*/
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/* Read the V2M SYS_ID register */
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mov_imm x0, (VE_SYSREGS_BASE + V2M_SYS_ID)
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ldr w1, [x0]
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/* Extract board revision from the SYS_ID */
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ubfx x1, x1, #SYS_ID_REV_SHIFT, #4
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/*
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* On Juno R0: x2 := REV_JUNO_R0 - 1 = 0
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* On Juno R1: x2 := REV_JUNO_R1 - 1 = 1
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*/
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sub x2, x1, #1
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/* --------------------------------------------------------------------
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* Determine whether this code is executed on a Cortex-A53 or on a
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* Cortex-A57 core.
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* --------------------------------------------------------------------
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*/
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mrs x0, midr_el1
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mrs x0, midr_el1
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ubfx x1, x0, MIDR_PN_SHIFT, #12
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ubfx x1, x0, MIDR_PN_SHIFT, #12
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cmp w1, #((CORTEX_A57_MIDR >> MIDR_PN_SHIFT) & MIDR_PN_MASK)
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cmp w1, #((CORTEX_A57_MIDR >> MIDR_PN_SHIFT) & MIDR_PN_MASK)
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b.ne 1f
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b.eq A57
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/* Change the L2 Data and Tag Ram latency to 3 cycles */
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/* Nothing needs to be done for the Cortex-A53 on Juno r1 */
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mov x0, #(L2_DATA_RAM_LATENCY_3_CYCLES | \
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cbz x2, apply_831273
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(L2_TAG_RAM_LATENCY_3_CYCLES << \
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ret
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L2CTLR_TAG_RAM_LATENCY_SHIFT))
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A57:
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/* --------------------------------------------------------------------
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* Cortex-A57 specific settings
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* --------------------------------------------------------------------
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*/
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/* Change the L2 Data RAM latency to 3 cycles */
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mov x0, #L2_DATA_RAM_LATENCY_3_CYCLES
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cbnz x2, apply_l2_ram_latencies
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/* On Juno r0, also change the L2 Tag RAM latency to 3 cycles */
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orr x0, x0, #(L2_TAG_RAM_LATENCY_3_CYCLES << L2CTLR_TAG_RAM_LATENCY_SHIFT)
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apply_l2_ram_latencies:
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msr L2CTLR_EL1, x0
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msr L2CTLR_EL1, x0
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1:
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/* Juno r1 doesn't suffer from defect #831273 */
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/* ---------------------------------------------
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cbnz x2, ret
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* Enable the event stream every 65536 cycles
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* ---------------------------------------------
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apply_831273:
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/* --------------------------------------------------------------------
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* On Juno r0, enable the event stream every 65536 cycles
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* --------------------------------------------------------------------
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*/
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*/
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mov x0, #(0xf << EVNTI_SHIFT)
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mov x0, #(0xf << EVNTI_SHIFT)
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orr x0, x0, #EVNTEN_BIT
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orr x0, x0, #EVNTEN_BIT
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msr CNTKCTL_EL1, x0
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msr CNTKCTL_EL1, x0
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ret:
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isb
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isb
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#endif /* FIRST_RESET_HANDLER_CALL */
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#endif /* FIRST_RESET_HANDLER_CALL */
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ret
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ret
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@ -122,10 +122,23 @@
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#define SYS_CNTREAD_BASE 0x2a800000
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#define SYS_CNTREAD_BASE 0x2a800000
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#define SYS_TIMCTL_BASE 0x2a810000
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#define SYS_TIMCTL_BASE 0x2a810000
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/* V2M motherboard system registers & offsets */
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/*
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* Base memory address of the V2M-Juno motherboard APB system registers in the
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* IOFPGA
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*/
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#define VE_SYSREGS_BASE 0x1c010000
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#define VE_SYSREGS_BASE 0x1c010000
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/* APB system registers in address offset order from the base memory address */
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#define V2M_SYS_ID 0x0
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#define V2M_SYS_LED 0x8
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#define V2M_SYS_LED 0x8
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/* V2M SYS_ID register bits */
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#define SYS_ID_REV_SHIFT 28
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#define SYS_ID_REV_MASK 0xf
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/* Board revisions */
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#define REV_JUNO_R0 0x1 /* Rev B */
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#define REV_JUNO_R1 0x2 /* Rev C */
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/*
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/*
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* V2M sysled bit definitions. The values written to this
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* V2M sysled bit definitions. The values written to this
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* register are defined in arch.h & runtime_svc.h. Only
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* register are defined in arch.h & runtime_svc.h. Only
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