diff --git a/docs/design/cpu-specific-build-macros.rst b/docs/design/cpu-specific-build-macros.rst index 771700c11..fbd2cbca4 100644 --- a/docs/design/cpu-specific-build-macros.rst +++ b/docs/design/cpu-specific-build-macros.rst @@ -576,6 +576,12 @@ For DSU errata, the following build flags are defined: r2p0 it is fixed). However, please note that this workaround results in increased DSU power consumption on idle. +- ``ERRATA_DSU_2313941``: This applies errata 2313941 workaround for the + affected DSU configurations. This errata applies for those DSUs with + revisions r0p0, r1p0, r2p0, r2p1, r3p0, r3p1 and is still open. However, + please note that this workaround results in increased DSU power consumption + on idle. + CPU Specific optimizations -------------------------- diff --git a/include/lib/cpus/aarch64/dsu_def.h b/include/lib/cpus/aarch64/dsu_def.h index 0969acf53..577de6199 100644 --- a/include/lib/cpus/aarch64/dsu_def.h +++ b/include/lib/cpus/aarch64/dsu_def.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2022, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -32,6 +32,7 @@ #define CLUSTERACTLR_EL1 S3_0_C15_C3_3 #define CLUSTERACTLR_EL1_DISABLE_CLOCK_GATING (ULL(1) << 15) +#define CLUSTERACTLR_EL1_DISABLE_SCLK_GATING (ULL(3) << 15) /******************************************************************** * Masks applied for DSU errata workarounds diff --git a/lib/cpus/aarch64/cortex_a510.S b/lib/cpus/aarch64/cortex_a510.S index 34e108245..f44407775 100644 --- a/lib/cpus/aarch64/cortex_a510.S +++ b/lib/cpus/aarch64/cortex_a510.S @@ -301,6 +301,7 @@ func cortex_a510_errata_report report_errata ERRATA_A510_2250311, cortex_a510, 2250311 report_errata ERRATA_A510_2218950, cortex_a510, 2218950 report_errata ERRATA_A510_2172148, cortex_a510, 2172148 + report_errata ERRATA_DSU_2313941, cortex_a510, dsu_2313941 ldp x8, x30, [sp], #16 ret @@ -312,12 +313,15 @@ func cortex_a510_reset_func /* Disable speculative loads */ msr SSBS, xzr - isb /* Get the CPU revision and stash it in x18. */ bl cpu_get_rev_var mov x18, x0 +#if ERRATA_DSU_2313941 + bl errata_dsu_2313941_wa +#endif + #if ERRATA_A510_1922240 mov x0, x18 bl errata_cortex_a510_1922240_wa @@ -353,6 +357,7 @@ func cortex_a510_reset_func bl errata_cortex_a510_2172148_wa #endif + isb ret x19 endfunc cortex_a510_reset_func diff --git a/lib/cpus/aarch64/cortex_a710.S b/lib/cpus/aarch64/cortex_a710.S index 63d55bbc0..5d8e9a603 100644 --- a/lib/cpus/aarch64/cortex_a710.S +++ b/lib/cpus/aarch64/cortex_a710.S @@ -411,6 +411,7 @@ func cortex_a710_errata_report report_errata ERRATA_A710_2282622, cortex_a710, 2282622 report_errata ERRATA_A710_2008768, cortex_a710, 2008768 report_errata WORKAROUND_CVE_2022_23960, cortex_a710, cve_2022_23960 + report_errata ERRATA_DSU_2313941, cortex_a710, dsu_2313941 ldp x8, x30, [sp], #16 ret @@ -426,6 +427,10 @@ func cortex_a710_reset_func bl cpu_get_rev_var mov x18, x0 +#if ERRATA_DSU_2313941 + bl errata_dsu_2313941_wa +#endif + #if ERRATA_A710_1987031 mov x0, x18 bl errata_a710_1987031_wa diff --git a/lib/cpus/aarch64/cortex_x2.S b/lib/cpus/aarch64/cortex_x2.S index 90a906b25..3e0810ba0 100644 --- a/lib/cpus/aarch64/cortex_x2.S +++ b/lib/cpus/aarch64/cortex_x2.S @@ -305,6 +305,7 @@ func cortex_x2_errata_report report_errata ERRATA_X2_2147715, cortex_x2, 2147715 report_errata ERRATA_X2_2216384, cortex_x2, 2216384 report_errata WORKAROUND_CVE_2022_23960, cortex_x2, cve_2022_23960 + report_errata ERRATA_DSU_2313941, cortex_x2, dsu_2313941 ldp x8, x30, [sp], #16 ret @@ -316,12 +317,15 @@ func cortex_x2_reset_func /* Disable speculative loads */ msr SSBS, xzr - isb /* Get the CPU revision and stash it in x18. */ bl cpu_get_rev_var mov x18, x0 +#if ERRATA_DSU_2313941 + bl errata_dsu_2313941_wa +#endif + #if ERRATA_X2_2002765 mov x0, x18 bl errata_cortex_x2_2002765_wa @@ -367,7 +371,7 @@ func cortex_x2_reset_func #endif /* IMAGE_BL31 && WORKAROUND_CVE_2022_23960 */ isb - ret x19 + ret x19 endfunc cortex_x2_reset_func /* --------------------------------------------- diff --git a/lib/cpus/aarch64/dsu_helpers.S b/lib/cpus/aarch64/dsu_helpers.S index da052d5c9..419b6ea47 100644 --- a/lib/cpus/aarch64/dsu_helpers.S +++ b/lib/cpus/aarch64/dsu_helpers.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019-2020, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2019-2022, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -139,3 +139,57 @@ func errata_dsu_936184_wa 1: ret x17 endfunc errata_dsu_936184_wa + + /* ----------------------------------------------------------------------- + * DSU erratum 2313941 check function + * Checks the DSU variant, revision and configuration to determine if + * the erratum applies. Erratum applies on all configurations of the + * DSU and if revision-variant is r0p0, r1p0, r2p0, r2p1, r3p0, r3p1. + * + * The erratum is still open. + * + * This function is called from both assembly and C environment. So it + * follows AAPCS. + * + * Clobbers: x0-x3 + * ----------------------------------------------------------------------- + */ + .globl check_errata_dsu_2313941 + .globl errata_dsu_2313941_wa + +func check_errata_dsu_2313941 + mov x2, #ERRATA_APPLIES + mov x3, #ERRATA_NOT_APPLIES + + /* Check if DSU version is less than or equal to r3p1 */ + mrs x1, CLUSTERIDR_EL1 + + /* DSU variant and revision bitfields in CLUSTERIDR are adjacent */ + ubfx x0, x1, #CLUSTERIDR_REV_SHIFT,\ + #(CLUSTERIDR_REV_BITS + CLUSTERIDR_VAR_BITS) + mov x1, #(0x31 << CLUSTERIDR_REV_SHIFT) + cmp x0, x1 + csel x0, x2, x3, LS + ret +endfunc check_errata_dsu_2313941 + + /* -------------------------------------------------- + * Errata Workaround for DSU erratum #2313941. + * + * Can clobber only: x0-x17 + * -------------------------------------------------- + */ +func errata_dsu_2313941_wa + mov x17, x30 + bl check_errata_dsu_2313941 + cbz x0, 1f + + /* If erratum applies, disable high-level clock gating */ + mrs x0, CLUSTERACTLR_EL1 + orr x0, x0, #CLUSTERACTLR_EL1_DISABLE_SCLK_GATING + msr CLUSTERACTLR_EL1, x0 + isb +1: + ret x17 +endfunc errata_dsu_2313941_wa + diff --git a/lib/cpus/aarch64/neoverse_n2.S b/lib/cpus/aarch64/neoverse_n2.S index b93f2a6f4..5b796dc07 100644 --- a/lib/cpus/aarch64/neoverse_n2.S +++ b/lib/cpus/aarch64/neoverse_n2.S @@ -367,6 +367,10 @@ func neoverse_n2_reset_func orr x0, x0, #NEOVERSE_N2_CPUACTLR2_EL1_BIT_2 msr NEOVERSE_N2_CPUACTLR2_EL1, x0 +#if ERRATA_DSU_2313941 + bl errata_dsu_2313941_wa +#endif + #if ERRATA_N2_2067956 mov x0, x18 bl errata_n2_2067956_wa @@ -493,6 +497,7 @@ func neoverse_n2_errata_report report_errata ERRATA_N2_2242400, neoverse_n2, 2242400 report_errata ERRATA_N2_2280757, neoverse_n2, 2280757 report_errata WORKAROUND_CVE_2022_23960, neoverse_n2, cve_2022_23960 + report_errata ERRATA_DSU_2313941, neoverse_n2, dsu_2313941 ldp x8, x30, [sp], #16 ret diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk index eb17dfd36..e14bb24f5 100644 --- a/lib/cpus/cpu-ops.mk +++ b/lib/cpus/cpu-ops.mk @@ -1,5 +1,5 @@ # -# Copyright (c) 2014-2022, ARM Limited and Contributors. All rights reserved. +# Copyright (c) 2014-2022, Arm Limited and Contributors. All rights reserved. # Copyright (c) 2020-2022, NVIDIA Corporation. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause @@ -614,6 +614,11 @@ ERRATA_DSU_798953 ?=0 # higher DSU power consumption on idle. ERRATA_DSU_936184 ?=0 +# Flag to apply DSU erratum 2313941. This erratum applies to DSUs revisions +# r0p0, r1p0, r2p0, r2p1, r3p0, r3p1 and is still open. Applying the workaround +# results in higher DSU power consumption on idle. +ERRATA_DSU_2313941 ?=0 + # Process ERRATA_A9_794073 flag $(eval $(call assert_boolean,ERRATA_A9_794073)) $(eval $(call add_define,ERRATA_A9_794073)) @@ -1138,6 +1143,10 @@ $(eval $(call add_define,ERRATA_DSU_798953)) $(eval $(call assert_boolean,ERRATA_DSU_936184)) $(eval $(call add_define,ERRATA_DSU_936184)) +# Process ERRATA_DSU_2313941 flag +$(eval $(call assert_boolean,ERRATA_DSU_2313941)) +$(eval $(call add_define,ERRATA_DSU_2313941)) + # Errata build flags ifneq (${ERRATA_A53_843419},0) TF_LDFLAGS_aarch64 += --fix-cortex-a53-843419