Tegra194: memctrl: update TZDRAM base at 1MB granularity
The Memory controller expects the TZDRAM base value at 1MB granularity and the current driver does not respect that limitation. This patch fixes that anomaly. Change-Id: I6b72270f331ba5081e19811df4a78623e457341a Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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@ -447,6 +447,8 @@ tegra_mc_settings_t *tegra_get_mc_settings(void)
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void plat_memctrl_tzdram_setup(uint64_t phys_base, uint64_t size_in_bytes)
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void plat_memctrl_tzdram_setup(uint64_t phys_base, uint64_t size_in_bytes)
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{
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{
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uint32_t sec_reg_ctrl = tegra_mc_read_32(MC_SECURITY_CFG_REG_CTRL_0);
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uint32_t sec_reg_ctrl = tegra_mc_read_32(MC_SECURITY_CFG_REG_CTRL_0);
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uint32_t phys_base_lo = (uint32_t)phys_base & 0xFFF00000;
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uint32_t phys_base_hi = (uint32_t)(phys_base >> 32);
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/*
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/*
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* Check TZDRAM carveout register access status. Setup TZDRAM fence
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* Check TZDRAM carveout register access status. Setup TZDRAM fence
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@ -461,8 +463,8 @@ void plat_memctrl_tzdram_setup(uint64_t phys_base, uint64_t size_in_bytes)
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*/
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*/
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INFO("Configuring TrustZone DRAM Memory Carveout\n");
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INFO("Configuring TrustZone DRAM Memory Carveout\n");
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tegra_mc_write_32(MC_SECURITY_CFG0_0, (uint32_t)phys_base);
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tegra_mc_write_32(MC_SECURITY_CFG0_0, phys_base_lo);
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tegra_mc_write_32(MC_SECURITY_CFG3_0, (uint32_t)(phys_base >> 32));
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tegra_mc_write_32(MC_SECURITY_CFG3_0, phys_base_hi);
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tegra_mc_write_32(MC_SECURITY_CFG1_0, (uint32_t)(size_in_bytes >> 20));
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tegra_mc_write_32(MC_SECURITY_CFG1_0, (uint32_t)(size_in_bytes >> 20));
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/*
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/*
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