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feat(plat/mdeiatek/mt8195): add display port control in SiP service 

MTK display port mute/unmute control registers need to be
set in secure world.

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: Iec73650e937bd20e25c18fa28d55ae29e68b10d3
This commit is contained in:
Rex-BC Chen 2021-04-12 11:10:31 +08:00 committed by Rex-BC Chen
parent 0fd12b9e11
commit 7eb4223757
7 changed files with 124 additions and 1 deletions
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4
plat/mediatek/mt8195/aarch64/platform_common.c
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@ -17,6 +17,10 @@ const mmap_region_t plat_mmap[] = {
MT_DEVICE | MT_RW | MT_SECURE),
MAP_REGION_FLAT(MTK_DEV_RNG2_BASE, MTK_DEV_RNG2_SIZE,
MT_DEVICE | MT_RW | MT_SECURE),
MAP_REGION_FLAT(DP_SEC_BASE, DP_SEC_SIZE,
MT_DEVICE | MT_RW | MT_SECURE),
MAP_REGION_FLAT(eDP_SEC_BASE, eDP_SEC_SIZE,
MT_DEVICE | MT_RW | MT_SECURE),
{ 0 }
};

66
plat/mediatek/mt8195/drivers/dp/mt_dp.c Normal file
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@ -0,0 +1,66 @@
/*
* Copyright (c) 2020, MediaTek Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <common/debug.h>
#include <lib/mmio.h>
#include <mt_dp.h>
#include <mtk_sip_svc.h>
#include <platform_def.h>
static uint32_t dp_write_sec_reg(uint32_t is_edp, uint32_t offset,
uint32_t value, uint32_t mask)
{
uint32_t reg = (is_edp != 0U) ? eDP_SEC_BASE : DP_SEC_BASE;
mmio_clrsetbits_32(reg + offset, mask, value);
return mmio_read_32(reg + offset);
}
int32_t dp_secure_handler(uint64_t cmd, uint64_t para, uint32_t *val)
{
int32_t ret = 0L;
uint32_t is_edp = 0UL;
uint32_t regval = 0UL;
uint32_t regmsk = 0UL;
uint32_t fldmask = 0UL;
if ((cmd > DP_ATF_CMD_COUNT) || (val == NULL)) {
INFO("dp_secure_handler error cmd 0x%llx\n", cmd);
return MTK_SIP_E_INVALID_PARAM;
}
switch (cmd) {
case DP_ATF_DP_VIDEO_UNMUTE:
INFO("[%s] DP_ATF_DP_VIDEO_UNMUTE\n", __func__);
is_edp = DP_ATF_TYPE_DP;
ret = MTK_SIP_E_SUCCESS;
break;
case DP_ATF_EDP_VIDEO_UNMUTE:
INFO("[%s] DP_ATF_EDP_VIDEO_UNMUTE\n", __func__);
is_edp = DP_ATF_TYPE_EDP;
ret = MTK_SIP_E_SUCCESS;
break;
default:
ret = MTK_SIP_E_INVALID_PARAM;
break;
}
if (ret == MTK_SIP_E_SUCCESS) {
regmsk = (VIDEO_MUTE_SEL_SECURE_FLDMASK |
VIDEO_MUTE_SW_SECURE_FLDMASK);
if (para > 0U) {
fldmask = VIDEO_MUTE_SW_SECURE_FLDMASK;
} else {
fldmask = 0;
}
regval = (VIDEO_MUTE_SEL_SECURE_FLDMASK | fldmask);
*val = dp_write_sec_reg(is_edp, DP_TX_SECURE_REG11,
regval, regmsk);
}
return ret;
}

28
plat/mediatek/mt8195/drivers/dp/mt_dp.h Normal file
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@ -0,0 +1,28 @@
/*
* Copyright (c) 2020, MediaTek Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef MT_DP_H
#define MT_DP_H
#define DP_TX_SECURE_REG11 (0x2c)
#define VIDEO_MUTE_SEL_SECURE_FLDMASK (0x10)
#define VIDEO_MUTE_SW_SECURE_FLDMASK (0x8)
enum DP_ATF_HW_TYPE {
DP_ATF_TYPE_DP = 0,
DP_ATF_TYPE_EDP = 1
};
enum DP_ATF_CMD {
DP_ATF_DP_VIDEO_UNMUTE = 0x20,
DP_ATF_EDP_VIDEO_UNMUTE,
DP_ATF_CMD_COUNT
};
int32_t dp_secure_handler(uint64_t cmd, uint64_t para, uint32_t *val);
#endif

6
plat/mediatek/mt8195/include/plat_sip_calls.h
View File

@ -10,6 +10,10 @@
/*******************************************************************************
* Plat SiP function constants
******************************************************************************/
#define MTK_PLAT_SIP_NUM_CALLS 0
#define MTK_PLAT_SIP_NUM_CALLS 2
/* DP/eDP */
#define MTK_SIP_DP_CONTROL_AARCH32 0x82000523
#define MTK_SIP_DP_CONTROL_AARCH64 0xC2000523
#endif /* PLAT_SIP_CALLS_H */

8
plat/mediatek/mt8195/include/platform_def.h
View File

@ -25,6 +25,14 @@
#define SPM_BASE (IO_PHYS + 0x00006000)
/*******************************************************************************
* DP/eDP related constants
******************************************************************************/
#define eDP_SEC_BASE (IO_PHYS + 0x0C504000)
#define DP_SEC_BASE (IO_PHYS + 0x0C604000)
#define eDP_SEC_SIZE 0x1000
#define DP_SEC_SIZE 0x1000
/*******************************************************************************
* GPIO related constants
******************************************************************************/

11
plat/mediatek/mt8195/plat_sip_calls.c
View File

@ -6,6 +6,9 @@
#include <common/debug.h>
#include <common/runtime_svc.h>
#include <mt_dp.h>
#include <mtk_sip_svc.h>
#include "plat_sip_calls.h"
uintptr_t mediatek_plat_sip_handler(uint32_t smc_fid,
u_register_t x1,
@ -16,7 +19,15 @@ uintptr_t mediatek_plat_sip_handler(uint32_t smc_fid,
void *handle,
u_register_t flags)
{
int32_t ret;
uint32_t ret_val;
switch (smc_fid) {
case MTK_SIP_DP_CONTROL_AARCH32:
case MTK_SIP_DP_CONTROL_AARCH64:
ret = dp_secure_handler(x1, x2, &ret_val);
SMC_RET2(handle, ret, ret_val);
break;
default:
ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid);
break;

2
plat/mediatek/mt8195/platform.mk
View File

@ -12,6 +12,7 @@ PLAT_INCLUDES := -I${MTK_PLAT}/common/ \
-I${MTK_PLAT}/common/drivers/gpio/ \
-I${MTK_PLAT}/common/drivers/rtc/ \
-I${MTK_PLAT}/common/drivers/timer/ \
-I${MTK_PLAT_SOC}/drivers/dp/ \
-I${MTK_PLAT_SOC}/drivers/gpio/ \
-I${MTK_PLAT_SOC}/drivers/mcdi/ \
-I${MTK_PLAT_SOC}/drivers/pmic/ \
@ -50,6 +51,7 @@ BL31_SOURCES += common/desc_image_load.c \
${MTK_PLAT_SOC}/aarch64/platform_common.c \
${MTK_PLAT_SOC}/aarch64/plat_helpers.S \
${MTK_PLAT_SOC}/bl31_plat_setup.c \
${MTK_PLAT_SOC}/drivers/dp/mt_dp.c \
${MTK_PLAT_SOC}/drivers/gpio/mtgpio.c \
${MTK_PLAT_SOC}/drivers/mcdi/mt_cpu_pm.c \
${MTK_PLAT_SOC}/drivers/mcdi/mt_cpu_pm_cpc.c \