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rockchip: really use base+size for secure ddr regions 

The calls to secure ddr regions on rk3288 and rk3399 use parameters of
base and size - as it custom for specifying memory regions, but the
functions themself expect start and endpoints of the area.

This only works by chance for the TZRAM, as it starts a 0x0 and therefore
its end location is the same as its size.

To not fall into a trap later on adapt the functions to really take
base+size parameters.

Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
Change-Id: Idb9fab38aa081f3335a4eca971e7b7f6757fbbab
This commit is contained in:
Heiko Stuebner 2019-10-09 14:39:44 +02:00
parent c6ee020ea2
commit 7f0b2e78e0
2 changed files with 12 additions and 6 deletions
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11
plat/rockchip/rk3288/drivers/secure/secure.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -38,15 +38,18 @@ static void sgrf_ddr_rgn_global_bypass(uint32_t bypass)
* SGRF_SOC_CON21 - end address of the RGN_7 + RGN_X control
*
* @rgn - the DDR regions 0 ~ 7 which are can be configured.
* The @st and @ed indicate the start and end addresses for which to set
* the security, and the unit is byte. When the st_mb == 0, ed_mb == 0, the
* @st - start address to set as secure
* @sz - length of area to set as secure
* The @st_mb and @ed_mb indicate the start and end addresses for which to set
* the security, and the unit is megabyte. When the st_mb == 0, ed_mb == 0, the
* address range 0x0 ~ 0xfffff is secure.
*
* For example, if we would like to set the range [0, 32MB) is security via
* DDR_RGN0, then rgn == 0, st_mb == 0, ed_mb == 31.
*/
static void sgrf_ddr_rgn_config(uint32_t rgn, uintptr_t st, uintptr_t ed)
static void sgrf_ddr_rgn_config(uint32_t rgn, uintptr_t st, size_t sz)
{
uintptr_t ed = st + sz;
uintptr_t st_mb, ed_mb;
assert(rgn <= 7);

7
plat/rockchip/rk3399/drivers/secure/secure.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -45,6 +45,8 @@ static void sgrf_ddr_rgn_global_bypass(uint32_t bypass)
* bypass, 1: enable bypass
*
* @rgn - the DDR regions 0 ~ 7 which are can be configured.
* @st - start address to set as secure
* @sz - length of area to set as secure
* The @st_mb and @ed_mb indicate the start and end addresses for which to set
* the security, and the unit is megabyte. When the st_mb == 0, ed_mb == 0, the
* address range 0x0 ~ 0xfffff is secure.
@ -53,8 +55,9 @@ static void sgrf_ddr_rgn_global_bypass(uint32_t bypass)
* DDR_RGN0, then rgn == 0, st_mb == 0, ed_mb == 31.
*/
static void sgrf_ddr_rgn_config(uint32_t rgn,
uintptr_t st, uintptr_t ed)
uintptr_t st, size_t sz)
{
uintptr_t ed = st + sz;
uintptr_t st_mb, ed_mb;
assert(rgn <= 7);