Merge "fix(rk3399/suspend): correct LPDDR4 resume sequence" into integration
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commit
7fb82d8286
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2016-2021, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -49,6 +49,7 @@
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__pmusramdata uint32_t dpll_data[PLL_CON_COUNT];
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__pmusramdata uint32_t cru_clksel_con6;
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__pmusramdata uint8_t pmu_enable_watchdog0;
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/*
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* Copy @num registers from @src to @dst
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@ -562,8 +563,14 @@ static __pmusramfunc int dram_switch_to_next_index(
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/* LPDDR4 f2 cann't do training, all training will fail */
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for (ch = 0; ch < ch_count; ch++) {
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/*
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* Without this disabled for LPDDR4 we end up writing 0's
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* in place of real data in an interesting pattern.
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*/
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if (sdram_params->dramtype != LPDDR4) {
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mmio_clrsetbits_32(PHY_REG(ch, 896), (0x3 << 8) | 1,
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fn << 8);
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}
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/* data_training failed */
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if (data_training(ch, sdram_params, PI_FULL_TRAINING))
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@ -748,13 +755,44 @@ void dmc_suspend(void)
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phy_regs->phy896[0] &= ~(0x3 << 8);
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}
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__pmusramfunc void phy_dll_bypass_set(uint32_t ch, uint32_t freq)
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{
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if (freq <= (125 * 1000 * 1000)) {
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/* Set master mode to SW for slices*/
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mmio_setbits_32(PHY_REG(ch, 86), 3 << 10);
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mmio_setbits_32(PHY_REG(ch, 214), 3 << 10);
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mmio_setbits_32(PHY_REG(ch, 342), 3 << 10);
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mmio_setbits_32(PHY_REG(ch, 470), 3 << 10);
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/* Set master mode to SW for address slices*/
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mmio_setbits_32(PHY_REG(ch, 547), 3 << 18);
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mmio_setbits_32(PHY_REG(ch, 675), 3 << 18);
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mmio_setbits_32(PHY_REG(ch, 803), 3 << 18);
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} else {
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/* Clear SW master mode for slices*/
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mmio_clrbits_32(PHY_REG(ch, 86), 3 << 10);
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mmio_clrbits_32(PHY_REG(ch, 214), 3 << 10);
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mmio_clrbits_32(PHY_REG(ch, 342), 3 << 10);
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mmio_clrbits_32(PHY_REG(ch, 470), 3 << 10);
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/* Clear SW master mode for address slices*/
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mmio_clrbits_32(PHY_REG(ch, 547), 3 << 18);
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mmio_clrbits_32(PHY_REG(ch, 675), 3 << 18);
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mmio_clrbits_32(PHY_REG(ch, 803), 3 << 18);
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}
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}
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__pmusramfunc void dmc_resume(void)
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{
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struct rk3399_sdram_params *sdram_params = &sdram_config;
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uint32_t channel_mask = 0;
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uint32_t channel;
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/*
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* We can't turn off the watchdog, so if we have not turned it on before
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* we should not turn it on here.
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*/
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if ((pmu_enable_watchdog0 & 0x1) == 0x1) {
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pmusram_enable_watchdog();
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}
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pmu_sgrf_rst_hld_release();
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restore_pmu_rsthold();
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sram_secure_timer_init();
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@ -772,6 +810,13 @@ __pmusramfunc void dmc_resume(void)
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retry:
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for (channel = 0; channel < sdram_params->num_channels; channel++) {
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phy_pctrl_reset(channel);
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/*
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* Without this, LPDDR4 will write 0's in place of real data
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* in a strange pattern.
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*/
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if (sdram_params->dramtype == LPDDR4) {
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phy_dll_bypass_set(channel, sdram_params->ddr_freq);
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}
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pctl_cfg(channel, sdram_params);
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}
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@ -788,8 +833,12 @@ retry:
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if (sdram_params->dramtype == LPDDR3)
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sram_udelay(10);
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/* If traning fail, retry to do it again. */
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if (data_training(channel, sdram_params, PI_FULL_TRAINING))
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/*
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* Training here will always fail for LPDDR4, so skip it
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* If traning fail, retry to do it again.
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*/
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if (sdram_params->dramtype != LPDDR4 &&
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data_training(channel, sdram_params, PI_FULL_TRAINING))
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goto retry;
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set_ddrconfig(sdram_params, channel,
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2016-2021, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -7,6 +7,7 @@
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#ifndef SUSPEND_H
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#define SUSPEND_H
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#include <stdint.h>
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#include <dram.h>
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#define KHz (1000)
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@ -22,5 +23,6 @@
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void dmc_suspend(void);
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__pmusramfunc void dmc_resume(void);
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extern __pmusramdata uint8_t pmu_enable_watchdog0;
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#endif /* SUSPEND_H */
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2016-2021, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -1324,6 +1324,7 @@ void wdt_register_save(void)
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store_wdt0[i] = mmio_read_32(WDT0_BASE + i * 4);
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store_wdt1[i] = mmio_read_32(WDT1_BASE + i * 4);
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}
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pmu_enable_watchdog0 = (uint8_t) store_wdt0[0] & 0x1;
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}
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void wdt_register_restore(void)
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