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Tegra: Introduce config for enabling NS access to L2/CPUECTRL regs 

A new config, ENABLE_NS_L2_CPUECTRL_RW_ACCESS, allows Tegra platforms to
enable read/write access to the L2 and CPUECTRL registers. T210 is the
only platform that needs to enable this config for now.

Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
This commit is contained in:
Varun Wadekar 2015-07-16 09:46:28 +05:30
parent e5b0664ce7
commit 8061a973ec
2 changed files with 10 additions and 4 deletions
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2
plat/nvidia/tegra/common/aarch64/tegra_helpers.S
View File

@ -57,6 +57,7 @@
*/
.macro cpu_init_common
#if ENABLE_NS_L2_CPUECTRL_RW_ACCESS
/* -------------------------------------------------------
* Enable L2 and CPU ECTLR RW access from non-secure world
* -------------------------------------------------------
@ -65,6 +66,7 @@
msr actlr_el3, x0
msr actlr_el2, x0
isb
#endif
/* --------------------------------
* Enable the cycle count register

12
plat/nvidia/tegra/soc/t210/platform_t210.mk
View File

@ -28,19 +28,22 @@
# POSSIBILITY OF SUCH DAMAGE.
#
TEGRA_BOOT_UART_BASE := 0x70006000
TEGRA_BOOT_UART_BASE := 0x70006000
$(eval $(call add_define,TEGRA_BOOT_UART_BASE))
TZDRAM_BASE := 0xFDC00000
TZDRAM_BASE := 0xFDC00000
$(eval $(call add_define,TZDRAM_BASE))
ERRATA_TEGRA_INVALIDATE_BTB_AT_BOOT := 1
$(eval $(call add_define,ERRATA_TEGRA_INVALIDATE_BTB_AT_BOOT))
PLATFORM_CLUSTER_COUNT := 2
ENABLE_NS_L2_CPUECTRL_RW_ACCESS := 1
$(eval $(call add_define,ENABLE_NS_L2_CPUECTRL_RW_ACCESS))
PLATFORM_CLUSTER_COUNT := 2
$(eval $(call add_define,PLATFORM_CLUSTER_COUNT))
PLATFORM_MAX_CPUS_PER_CLUSTER := 4
PLATFORM_MAX_CPUS_PER_CLUSTER := 4
$(eval $(call add_define,PLATFORM_MAX_CPUS_PER_CLUSTER))
BL31_SOURCES += ${SOC_DIR}/plat_psci_handlers.c \
@ -49,3 +52,4 @@ BL31_SOURCES += ${SOC_DIR}/plat_psci_handlers.c \
# Enable workarounds for selected Cortex-A53 erratas.
ERRATA_A53_826319 := 1