Neoverse N1 Errata Workaround 1542419
Coherent I-cache is causing a prefetch violation where when the core executes an instruction that has recently been modified, the core might fetch a stale instruction which violates the ordering of instruction fetches. The workaround includes an instruction sequence to implementation defined registers to trap all EL0 IC IVAU instructions to EL3 and a trap handler to execute a TLB inner-shareable invalidation to an arbitrary address followed by a DSB. Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com> Change-Id: Ic3b7cbb11cf2eaf9005523ef5578a372593ae4d6
This commit is contained in:
parent
5f38b5362c
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80942622fe
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@ -11,7 +11,8 @@
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#include <bl31/ea_handle.h>
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#include <bl31/ea_handle.h>
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#include <context.h>
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#include <context.h>
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#include <lib/extensions/ras_arch.h>
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#include <lib/extensions/ras_arch.h>
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#include <cpu_macros.S>
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#include <context.h>
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.globl handle_lower_el_ea_esb
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.globl handle_lower_el_ea_esb
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.globl enter_lower_el_sync_ea
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.globl enter_lower_el_sync_ea
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@ -35,9 +36,9 @@ endfunc handle_lower_el_ea_esb
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/*
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/*
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* This function forms the tail end of Synchronous Exception entry from lower
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* This function forms the tail end of Synchronous Exception entry from lower
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* EL, and expects to handle only Synchronous External Aborts from lower EL. If
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* EL, and expects to handle Synchronous External Aborts from lower EL and CPU
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* any other kind of exception is detected, then this function reports unhandled
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* Implementation Defined Exceptions. If any other kind of exception is detected,
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* exception.
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* then this function reports unhandled exception.
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*
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*
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* Since it's part of exception vector, this function doesn't expect any GP
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* Since it's part of exception vector, this function doesn't expect any GP
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* registers to have been saved. It delegates the handling of the EA to platform
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* registers to have been saved. It delegates the handling of the EA to platform
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@ -58,12 +59,33 @@ func enter_lower_el_sync_ea
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b.eq 1f
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b.eq 1f
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cmp x30, #EC_DABORT_LOWER_EL
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cmp x30, #EC_DABORT_LOWER_EL
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b.ne 2f
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b.eq 1f
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/* Save GP registers */
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stp x0, x1, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X0]
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stp x2, x3, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X2]
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stp x4, x5, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X4]
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/* Get the cpu_ops pointer */
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bl get_cpu_ops_ptr
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/* Get the cpu_ops exception handler */
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ldr x0, [x0, #CPU_E_HANDLER_FUNC]
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/*
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* If the reserved function pointer is NULL, this CPU does not have an
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* implementation defined exception handler function
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*/
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cbz x0, 2f
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mrs x1, esr_el3
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ubfx x1, x1, #ESR_EC_SHIFT, #ESR_EC_LENGTH
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blr x0
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b 2f
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1:
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1:
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/* Test for EA bit in the instruction syndrome */
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/* Test for EA bit in the instruction syndrome */
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mrs x30, esr_el3
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mrs x30, esr_el3
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tbz x30, #ESR_ISS_EABORT_EA_BIT, 2f
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tbz x30, #ESR_ISS_EABORT_EA_BIT, 3f
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/*
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/*
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* Save general purpose and ARMv8.3-PAuth registers (if enabled).
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* Save general purpose and ARMv8.3-PAuth registers (if enabled).
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@ -84,6 +106,11 @@ func enter_lower_el_sync_ea
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b delegate_sync_ea
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b delegate_sync_ea
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2:
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2:
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ldp x0, x1, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X0]
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ldp x2, x3, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X2]
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ldp x4, x5, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X4]
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3:
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/* Synchronous exceptions other than the above are assumed to be EA */
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/* Synchronous exceptions other than the above are assumed to be EA */
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ldr x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR]
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ldr x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR]
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no_ret report_unhandled_exception
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no_ret report_unhandled_exception
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@ -258,6 +258,9 @@ For Neoverse N1, the following errata build flags are defined :
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- ``ERRATA_N1_1315703``: This applies errata 1315703 workaround to Neoverse-N1
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- ``ERRATA_N1_1315703``: This applies errata 1315703 workaround to Neoverse-N1
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CPU. This needs to be enabled only for revision <= r3p0 of the CPU.
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CPU. This needs to be enabled only for revision <= r3p0 of the CPU.
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- ``ERRATA_N1_1542419``: This applies errata 1542419 workaround to Neoverse-N1
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CPU. This needs to be enabled only for revisions r3p0 - r4p0 of the CPU.
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DSU Errata Workarounds
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DSU Errata Workarounds
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----------------------
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----------------------
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@ -43,6 +43,7 @@
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.equ CPU_MIDR_SIZE, CPU_WORD_SIZE
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.equ CPU_MIDR_SIZE, CPU_WORD_SIZE
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.equ CPU_EXTRA1_FUNC_SIZE, CPU_WORD_SIZE
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.equ CPU_EXTRA1_FUNC_SIZE, CPU_WORD_SIZE
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.equ CPU_EXTRA2_FUNC_SIZE, CPU_WORD_SIZE
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.equ CPU_EXTRA2_FUNC_SIZE, CPU_WORD_SIZE
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.equ CPU_E_HANDLER_FUNC_SIZE, CPU_WORD_SIZE
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.equ CPU_RESET_FUNC_SIZE, CPU_WORD_SIZE
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.equ CPU_RESET_FUNC_SIZE, CPU_WORD_SIZE
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.equ CPU_PWR_DWN_OPS_SIZE, CPU_WORD_SIZE * CPU_MAX_PWR_DWN_OPS
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.equ CPU_PWR_DWN_OPS_SIZE, CPU_WORD_SIZE * CPU_MAX_PWR_DWN_OPS
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.equ CPU_ERRATA_FUNC_SIZE, CPU_WORD_SIZE
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.equ CPU_ERRATA_FUNC_SIZE, CPU_WORD_SIZE
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@ -83,7 +84,8 @@
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.equ CPU_RESET_FUNC, CPU_MIDR + CPU_MIDR_SIZE
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.equ CPU_RESET_FUNC, CPU_MIDR + CPU_MIDR_SIZE
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.equ CPU_EXTRA1_FUNC, CPU_RESET_FUNC + CPU_RESET_FUNC_SIZE
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.equ CPU_EXTRA1_FUNC, CPU_RESET_FUNC + CPU_RESET_FUNC_SIZE
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.equ CPU_EXTRA2_FUNC, CPU_EXTRA1_FUNC + CPU_EXTRA1_FUNC_SIZE
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.equ CPU_EXTRA2_FUNC, CPU_EXTRA1_FUNC + CPU_EXTRA1_FUNC_SIZE
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.equ CPU_PWR_DWN_OPS, CPU_EXTRA2_FUNC + CPU_EXTRA2_FUNC_SIZE
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.equ CPU_E_HANDLER_FUNC, CPU_EXTRA2_FUNC + CPU_EXTRA2_FUNC_SIZE
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.equ CPU_PWR_DWN_OPS, CPU_E_HANDLER_FUNC + CPU_E_HANDLER_FUNC_SIZE
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.equ CPU_ERRATA_FUNC, CPU_PWR_DWN_OPS + CPU_PWR_DWN_OPS_SIZE
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.equ CPU_ERRATA_FUNC, CPU_PWR_DWN_OPS + CPU_PWR_DWN_OPS_SIZE
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.equ CPU_ERRATA_LOCK, CPU_ERRATA_FUNC + CPU_ERRATA_FUNC_SIZE
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.equ CPU_ERRATA_LOCK, CPU_ERRATA_FUNC + CPU_ERRATA_FUNC_SIZE
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.equ CPU_ERRATA_PRINTED, CPU_ERRATA_LOCK + CPU_ERRATA_LOCK_SIZE
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.equ CPU_ERRATA_PRINTED, CPU_ERRATA_LOCK + CPU_ERRATA_LOCK_SIZE
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@ -139,6 +141,8 @@
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* This is a placeholder for future per CPU operations. Currently
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* This is a placeholder for future per CPU operations. Currently
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* some CPUs use this entry to set a function to disable the
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* some CPUs use this entry to set a function to disable the
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* workaround for CVE-2018-3639.
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* workaround for CVE-2018-3639.
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* _e_handler:
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* This is a placeholder for future per CPU exception handlers.
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* _power_down_ops:
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* _power_down_ops:
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* Comma-separated list of functions to perform power-down
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* Comma-separated list of functions to perform power-down
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* operatios on the CPU. At least one, and up to
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* operatios on the CPU. At least one, and up to
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@ -149,7 +153,7 @@
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* used to handle power down at subsequent levels
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* used to handle power down at subsequent levels
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*/
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*/
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.macro declare_cpu_ops_base _name:req, _midr:req, _resetfunc:req, \
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.macro declare_cpu_ops_base _name:req, _midr:req, _resetfunc:req, \
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_extra1:req, _extra2:req, _power_down_ops:vararg
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_extra1:req, _extra2:req, _e_handler:req, _power_down_ops:vararg
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.section cpu_ops, "a"
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.section cpu_ops, "a"
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.align 3
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.align 3
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.type cpu_ops_\_name, %object
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.type cpu_ops_\_name, %object
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#endif
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#endif
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.quad \_extra1
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.quad \_extra1
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.quad \_extra2
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.quad \_extra2
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.quad \_e_handler
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#ifdef IMAGE_BL31
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#ifdef IMAGE_BL31
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/* Insert list of functions */
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/* Insert list of functions */
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fill_constants CPU_MAX_PWR_DWN_OPS, \_power_down_ops
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fill_constants CPU_MAX_PWR_DWN_OPS, \_power_down_ops
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@ -203,15 +208,21 @@
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.macro declare_cpu_ops _name:req, _midr:req, _resetfunc:req, \
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.macro declare_cpu_ops _name:req, _midr:req, _resetfunc:req, \
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_power_down_ops:vararg
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_power_down_ops:vararg
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declare_cpu_ops_base \_name, \_midr, \_resetfunc, 0, 0, \
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declare_cpu_ops_base \_name, \_midr, \_resetfunc, 0, 0, 0, \
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\_power_down_ops
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\_power_down_ops
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.endm
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.endm
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.macro declare_cpu_ops_eh _name:req, _midr:req, _resetfunc:req, \
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_e_handler:req, _power_down_ops:vararg
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declare_cpu_ops_base \_name, \_midr, \_resetfunc, \
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0, 0, \_e_handler, \_power_down_ops
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.endm
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.macro declare_cpu_ops_wa _name:req, _midr:req, \
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.macro declare_cpu_ops_wa _name:req, _midr:req, \
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_resetfunc:req, _extra1:req, _extra2:req, \
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_resetfunc:req, _extra1:req, _extra2:req, \
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_power_down_ops:vararg
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_power_down_ops:vararg
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declare_cpu_ops_base \_name, \_midr, \_resetfunc, \
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declare_cpu_ops_base \_name, \_midr, \_resetfunc, \
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\_extra1, \_extra2, \_power_down_ops
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\_extra1, \_extra2, 0, \_power_down_ops
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.endm
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.endm
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#if REPORT_ERRATA
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#if REPORT_ERRATA
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@ -12,6 +12,9 @@
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/* Neoverse N1 MIDR for revision 0 */
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/* Neoverse N1 MIDR for revision 0 */
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#define NEOVERSE_N1_MIDR U(0x410fd0c0)
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#define NEOVERSE_N1_MIDR U(0x410fd0c0)
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/* Exception Syndrome register EC code for IC Trap */
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#define NEOVERSE_N1_EC_IC_TRAP U(0x1f)
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/*******************************************************************************
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/*******************************************************************************
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* CPU Power Control register specific definitions.
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* CPU Power Control register specific definitions.
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******************************************************************************/
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******************************************************************************/
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@ -227,6 +227,27 @@ func cpu_rev_var_hs
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ret
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ret
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endfunc cpu_rev_var_hs
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endfunc cpu_rev_var_hs
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/*
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* Compare the CPU's revision-variant (x0) with a given range (x1 - x2), for errata
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* application purposes. If the revision-variant is between or includes the given
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* values, this indicates that errata applies; otherwise not.
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*
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* Shall clobber: x0-x4
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*/
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.globl cpu_rev_var_range
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func cpu_rev_var_range
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mov x3, #ERRATA_APPLIES
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mov x4, #ERRATA_NOT_APPLIES
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cmp x0, x1
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csel x1, x3, x4, hs
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cbz x1, 1f
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cmp x0, x2
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csel x1, x3, x4, ls
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1:
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mov x0, x1
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ret
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endfunc cpu_rev_var_range
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#if REPORT_ERRATA
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#if REPORT_ERRATA
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/*
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/*
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* void print_errata_status(void);
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* void print_errata_status(void);
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@ -9,6 +9,7 @@
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#include <neoverse_n1.h>
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#include <neoverse_n1.h>
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#include <cpuamu.h>
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#include <cpuamu.h>
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#include <cpu_macros.S>
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#include <cpu_macros.S>
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#include <context.h>
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/* Hardware handled coherency */
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/* Hardware handled coherency */
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#if HW_ASSISTED_COHERENCY == 0
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#if HW_ASSISTED_COHERENCY == 0
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@ -20,6 +21,10 @@
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#error "Neoverse-N1 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
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#error "Neoverse-N1 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
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#endif
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#endif
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#if ERRATA_N1_IC_TRAP
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.global neoverse_n1_errata_ic_trap_handler
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#endif
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/* --------------------------------------------------
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/* --------------------------------------------------
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* Errata Workaround for Neoverse N1 Erratum 1043202.
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* Errata Workaround for Neoverse N1 Erratum 1043202.
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* This applies to revision r0p0 and r1p0 of Neoverse N1.
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* This applies to revision r0p0 and r1p0 of Neoverse N1.
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@ -337,6 +342,41 @@ func check_errata_1315703
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b cpu_rev_var_ls
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b cpu_rev_var_ls
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endfunc check_errata_1315703
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endfunc check_errata_1315703
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/* --------------------------------------------------
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* Errata Workaround for Neoverse N1 Erratum 1542419.
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* This applies to revisions r3p0 - r4p0 of Neoverse N1
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* Inputs:
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* x0: variant[4:7] and revision[0:3] of current cpu.
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* Shall clobber: x0-x17
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* --------------------------------------------------
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*/
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func errata_n1_1542419_wa
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/* Compare x0 against revision r3p0 and r4p0 */
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mov x17, x30
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bl check_errata_1542419
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cbz x0, 1f
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/* Apply instruction patching sequence */
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ldr x0, =0x0
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msr CPUPSELR_EL3, x0
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ldr x0, =0xEE670D35
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msr CPUPOR_EL3, x0
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ldr x0, =0xFFFF0FFF
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msr CPUPMR_EL3, x0
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ldr x0, =0x08000020007D
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msr CPUPCR_EL3, x0
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isb
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1:
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ret x17
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endfunc errata_n1_1542419_wa
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func check_errata_1542419
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/* Applies to everything r3p0 - r4p0. */
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mov x1, #0x30
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mov x2, #0x40
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b cpu_rev_var_range
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endfunc check_errata_1542419
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func neoverse_n1_reset_func
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func neoverse_n1_reset_func
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mov x19, x30
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mov x19, x30
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@ -406,6 +446,11 @@ func neoverse_n1_reset_func
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bl errata_n1_1315703_wa
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bl errata_n1_1315703_wa
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#endif
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#endif
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#if ERRATA_N1_1542419
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mov x0, x18
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bl errata_n1_1542419_wa
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#endif
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#if ENABLE_AMU
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#if ENABLE_AMU
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/* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */
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/* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */
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mrs x0, actlr_el3
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mrs x0, actlr_el3
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@ -471,6 +516,7 @@ func neoverse_n1_errata_report
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report_errata ERRATA_N1_1262888, neoverse_n1, 1262888
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report_errata ERRATA_N1_1262888, neoverse_n1, 1262888
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report_errata ERRATA_N1_1275112, neoverse_n1, 1275112
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report_errata ERRATA_N1_1275112, neoverse_n1, 1275112
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report_errata ERRATA_N1_1315703, neoverse_n1, 1315703
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report_errata ERRATA_N1_1315703, neoverse_n1, 1315703
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report_errata ERRATA_N1_1542419, neoverse_n1, 1542419
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report_errata ERRATA_DSU_936184, neoverse_n1, dsu_936184
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report_errata ERRATA_DSU_936184, neoverse_n1, dsu_936184
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ldp x8, x30, [sp], #16
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ldp x8, x30, [sp], #16
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@ -478,6 +524,42 @@ func neoverse_n1_errata_report
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endfunc neoverse_n1_errata_report
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endfunc neoverse_n1_errata_report
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#endif
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#endif
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/*
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* Handle trap of EL0 IC IVAU instructions to EL3 by executing a TLB
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* inner-shareable invalidation to an arbitrary address followed by a DSB.
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*
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* x1: Exception Syndrome
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*/
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func neoverse_n1_errata_ic_trap_handler
|
||||||
|
cmp x1, #NEOVERSE_N1_EC_IC_TRAP
|
||||||
|
b.ne 1f
|
||||||
|
tlbi vae3is, xzr
|
||||||
|
dsb sy
|
||||||
|
|
||||||
|
# Skip the IC instruction itself
|
||||||
|
mrs x3, elr_el3
|
||||||
|
add x3, x3, #4
|
||||||
|
msr elr_el3, x3
|
||||||
|
|
||||||
|
ldp x0, x1, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X0]
|
||||||
|
ldp x2, x3, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X2]
|
||||||
|
ldp x4, x5, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X4]
|
||||||
|
ldr x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR]
|
||||||
|
|
||||||
|
#if IMAGE_BL31 && RAS_EXTENSION
|
||||||
|
/*
|
||||||
|
* Issue Error Synchronization Barrier to synchronize SErrors before
|
||||||
|
* exiting EL3. We're running with EAs unmasked, so any synchronized
|
||||||
|
* errors would be taken immediately; therefore no need to inspect
|
||||||
|
* DISR_EL1 register.
|
||||||
|
*/
|
||||||
|
esb
|
||||||
|
#endif
|
||||||
|
eret
|
||||||
|
1:
|
||||||
|
ret
|
||||||
|
endfunc neoverse_n1_errata_ic_trap_handler
|
||||||
|
|
||||||
/* ---------------------------------------------
|
/* ---------------------------------------------
|
||||||
* This function provides neoverse_n1 specific
|
* This function provides neoverse_n1 specific
|
||||||
* register information for crash reporting.
|
* register information for crash reporting.
|
||||||
|
@ -497,6 +579,7 @@ func neoverse_n1_cpu_reg_dump
|
||||||
ret
|
ret
|
||||||
endfunc neoverse_n1_cpu_reg_dump
|
endfunc neoverse_n1_cpu_reg_dump
|
||||||
|
|
||||||
declare_cpu_ops neoverse_n1, NEOVERSE_N1_MIDR, \
|
declare_cpu_ops_eh neoverse_n1, NEOVERSE_N1_MIDR, \
|
||||||
neoverse_n1_reset_func, \
|
neoverse_n1_reset_func, \
|
||||||
|
neoverse_n1_errata_ic_trap_handler, \
|
||||||
neoverse_n1_core_pwr_dwn
|
neoverse_n1_core_pwr_dwn
|
||||||
|
|
|
@ -278,6 +278,10 @@ ERRATA_N1_1275112 ?=0
|
||||||
# to revisions before r3p1 of the Neoverse N1 cpu.
|
# to revisions before r3p1 of the Neoverse N1 cpu.
|
||||||
ERRATA_N1_1315703 ?=1
|
ERRATA_N1_1315703 ?=1
|
||||||
|
|
||||||
|
# Flag to apply erratum 1542419 workaround during reset. This erratum applies
|
||||||
|
# to revisions r3p0 - r4p0 of the Neoverse N1 cpu.
|
||||||
|
ERRATA_N1_1542419 ?=0
|
||||||
|
|
||||||
# Flag to apply DSU erratum 798953. This erratum applies to DSUs revision r0p0.
|
# Flag to apply DSU erratum 798953. This erratum applies to DSUs revision r0p0.
|
||||||
# Applying the workaround results in higher DSU power consumption on idle.
|
# Applying the workaround results in higher DSU power consumption on idle.
|
||||||
ERRATA_DSU_798953 ?=0
|
ERRATA_DSU_798953 ?=0
|
||||||
|
@ -507,6 +511,10 @@ $(eval $(call add_define,ERRATA_N1_1275112))
|
||||||
$(eval $(call assert_boolean,ERRATA_N1_1315703))
|
$(eval $(call assert_boolean,ERRATA_N1_1315703))
|
||||||
$(eval $(call add_define,ERRATA_N1_1315703))
|
$(eval $(call add_define,ERRATA_N1_1315703))
|
||||||
|
|
||||||
|
# Process ERRATA_N1_1542419 flag
|
||||||
|
$(eval $(call assert_boolean,ERRATA_N1_1542419))
|
||||||
|
$(eval $(call add_define,ERRATA_N1_1542419))
|
||||||
|
|
||||||
# Process ERRATA_DSU_798953 flag
|
# Process ERRATA_DSU_798953 flag
|
||||||
$(eval $(call assert_boolean,ERRATA_DSU_798953))
|
$(eval $(call assert_boolean,ERRATA_DSU_798953))
|
||||||
$(eval $(call add_define,ERRATA_DSU_798953))
|
$(eval $(call add_define,ERRATA_DSU_798953))
|
||||||
|
|
Loading…
Reference in New Issue