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Merge changes from topic "stm32mp1_plat_updates" into integration 

* changes:
  docs: update STM32MP1 with versions details
  stm32mp1: get peripheral base address from a define
  stm32mp1: add finished good variant in board identifier
This commit is contained in:
Madhukar Pappireddy 2020-10-13 15:46:35 +00:00 committed by TrustedFirmware Code Review
parent 113e8fdab4 6354401276
commit 80d9cf7808
10 changed files with 67 additions and 267 deletions
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18
docs/plat/stm32mp1.rst
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@ -8,6 +8,23 @@ The STM32MP1 chip also embeds a Cortex-M4.
More information can be found on `STM32MP1 Series`_ page.
STM32MP1 Versions
-----------------
The STM32MP1 series is available in 3 different lines which are pin-to-pin compatible:
- STM32MP157: Dual Cortex-A7 cores, Cortex-M4 core @ 209 MHz, 3D GPU, DSI display interface and CAN FD
- STM32MP153: Dual Cortex-A7 cores, Cortex-M4 core @ 209 MHz and CAN FD
- STM32MP151: Single Cortex-A7 core, Cortex-M4 core @ 209 MHz
Each line comes with a security option (cryptography & secure boot) and a Cortex-A frequency option:
- A Basic + Cortex-A7 @ 650 MHz
- C Secure Boot + HW Crypto + Cortex-A7 @ 650 MHz
- D Basic + Cortex-A7 @ 800 MHz
- F Secure Boot + HW Crypto + Cortex-A7 @ 800 MHz
The `STM32MP1 part number codification`_ page gives more information about part numbers.
Design
------
The STM32MP1 resets in the ROM code of the Cortex-A7.
@ -129,3 +146,4 @@ OP-TEE artifacts go into separate partitions as follows:
.. _STM32MP1 Series: https://www.st.com/en/microcontrollers-microprocessors/stm32mp1-series.html
.. _STM32MP1 part number codification: https://wiki.st.com/stm32mpu/wiki/STM32MP15_microprocessor#Part_number_codification

37
drivers/st/clk/stm32mp1_clk.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (C) 2018-2019, STMicroelectronics - All Rights Reserved
* Copyright (C) 2018-2020, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
*/
@ -1664,28 +1664,26 @@ static void stm32mp1_set_rtcsrc(unsigned int clksrc, bool lse_css)
static void stm32mp1_stgen_config(void)
{
uintptr_t stgen;
uint32_t cntfid0;
unsigned long rate;
unsigned long long counter;
stgen = fdt_get_stgen_base();
cntfid0 = mmio_read_32(stgen + CNTFID_OFF);
cntfid0 = mmio_read_32(STGEN_BASE + CNTFID_OFF);
rate = get_clock_rate(stm32mp1_clk_get_parent(STGEN_K));
if (cntfid0 == rate) {
return;
}
mmio_clrbits_32(stgen + CNTCR_OFF, CNTCR_EN);
counter = (unsigned long long)mmio_read_32(stgen + CNTCVL_OFF);
counter |= ((unsigned long long)mmio_read_32(stgen + CNTCVU_OFF)) << 32;
mmio_clrbits_32(STGEN_BASE + CNTCR_OFF, CNTCR_EN);
counter = (unsigned long long)mmio_read_32(STGEN_BASE + CNTCVL_OFF);
counter |= ((unsigned long long)mmio_read_32(STGEN_BASE + CNTCVU_OFF)) << 32;
counter = (counter * rate / cntfid0);
mmio_write_32(stgen + CNTCVL_OFF, (uint32_t)counter);
mmio_write_32(stgen + CNTCVU_OFF, (uint32_t)(counter >> 32));
mmio_write_32(stgen + CNTFID_OFF, rate);
mmio_setbits_32(stgen + CNTCR_OFF, CNTCR_EN);
mmio_write_32(STGEN_BASE + CNTCVL_OFF, (uint32_t)counter);
mmio_write_32(STGEN_BASE + CNTCVU_OFF, (uint32_t)(counter >> 32));
mmio_write_32(STGEN_BASE + CNTFID_OFF, rate);
mmio_setbits_32(STGEN_BASE + CNTCR_OFF, CNTCR_EN);
write_cntfrq((u_register_t)rate);
@ -1695,20 +1693,17 @@ static void stm32mp1_stgen_config(void)
void stm32mp1_stgen_increment(unsigned long long offset_in_ms)
{
uintptr_t stgen;
unsigned long long cnt;
stgen = fdt_get_stgen_base();
cnt = ((unsigned long long)mmio_read_32(STGEN_BASE + CNTCVU_OFF) << 32) |
mmio_read_32(STGEN_BASE + CNTCVL_OFF);
cnt = ((unsigned long long)mmio_read_32(stgen + CNTCVU_OFF) << 32) |
mmio_read_32(stgen + CNTCVL_OFF);
cnt += (offset_in_ms * mmio_read_32(STGEN_BASE + CNTFID_OFF)) / 1000U;
cnt += (offset_in_ms * mmio_read_32(stgen + CNTFID_OFF)) / 1000U;
mmio_clrbits_32(stgen + CNTCR_OFF, CNTCR_EN);
mmio_write_32(stgen + CNTCVL_OFF, (uint32_t)cnt);
mmio_write_32(stgen + CNTCVU_OFF, (uint32_t)(cnt >> 32));
mmio_setbits_32(stgen + CNTCR_OFF, CNTCR_EN);
mmio_clrbits_32(STGEN_BASE + CNTCR_OFF, CNTCR_EN);
mmio_write_32(STGEN_BASE + CNTCVL_OFF, (uint32_t)cnt);
mmio_write_32(STGEN_BASE + CNTCVU_OFF, (uint32_t)(cnt >> 32));
mmio_setbits_32(STGEN_BASE + CNTCR_OFF, CNTCR_EN);
}
static void stm32mp1_pkcs_config(uint32_t pkcs)

58
drivers/st/clk/stm32mp_clkfunc.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2017-2019, STMicroelectronics - All Rights Reserved
* Copyright (c) 2017-2020, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -14,8 +14,6 @@
#include <drivers/st/stm32_gpio.h>
#include <drivers/st/stm32mp_clkfunc.h>
#define DT_STGEN_COMPAT "st,stm32-stgen"
/*
* Get the frequency of an oscillator from its name in device tree.
* @param name: oscillator name
@ -168,33 +166,6 @@ int fdt_get_rcc_node(void *fdt)
return fdt_node_offset_by_compatible(fdt, -1, DT_RCC_CLK_COMPAT);
}
/*
* Get the RCC base address from the device tree
* @return: RCC address or 0 on error
*/
uint32_t fdt_rcc_read_addr(void)
{
int node;
void *fdt;
const fdt32_t *cuint;
if (fdt_get_address(&fdt) == 0) {
return 0;
}
node = fdt_get_rcc_node(fdt);
if (node < 0) {
return 0;
}
cuint = fdt_getprop(fdt, node, "reg", NULL);
if (cuint == NULL) {
return 0;
}
return fdt32_to_cpu(*cuint);
}
/*
* Read a series of parameters in rcc-clk section in device tree
* @param prop_name: Name of the RCC property to be read
@ -298,33 +269,6 @@ bool fdt_get_rcc_secure_status(void)
return !!(fdt_get_status(node) & DT_SECURE);
}
/*
* Get the stgen base address.
* @return: address of stgen on success, and NULL value on failure.
*/
uintptr_t fdt_get_stgen_base(void)
{
int node;
const fdt32_t *cuint;
void *fdt;
if (fdt_get_address(&fdt) == 0) {
return 0;
}
node = fdt_node_offset_by_compatible(fdt, -1, DT_STGEN_COMPAT);
if (node < 0) {
return 0;
}
cuint = fdt_getprop(fdt, node, "reg", NULL);
if (cuint == NULL) {
return 0;
}
return fdt32_to_cpu(*cuint);
}
/*
* Get the clock ID of the given node in device tree.
* @param node: node offset

4
include/drivers/st/stm32mp_clkfunc.h
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2017-2019, STMicroelectronics - All Rights Reserved
* Copyright (c) 2017-2020, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -20,14 +20,12 @@ uint32_t fdt_osc_read_uint32_default(enum stm32mp_osc_id osc_id,
uint32_t dflt_value);
int fdt_get_rcc_node(void *fdt);
uint32_t fdt_rcc_read_addr(void);
int fdt_rcc_read_uint32_array(const char *prop_name, uint32_t count,
uint32_t *array);
int fdt_rcc_subnode_offset(const char *name);
const fdt32_t *fdt_rcc_read_prop(const char *prop_name, int *lenp);
bool fdt_get_rcc_secure_status(void);
uintptr_t fdt_get_stgen_base(void);
int fdt_get_clock_id(int node);
#endif /* STM32MP_CLKFUNC_H */

4
plat/st/common/include/stm32mp_dt.h
View File

@ -34,11 +34,7 @@ void dt_fill_device_info(struct dt_node_info *info, int node);
int dt_get_node(struct dt_node_info *info, int offset, const char *compat);
int dt_get_stdout_uart_info(struct dt_node_info *info);
uint32_t dt_get_ddr_size(void);
uintptr_t dt_get_ddrctrl_base(void);
uintptr_t dt_get_ddrphyc_base(void);
uintptr_t dt_get_pwr_base(void);
uint32_t dt_get_pwr_vdd_voltage(void);
uintptr_t dt_get_syscfg_base(void);
const char *dt_get_board_model(void);
int fdt_get_gpio_bank_pin_count(unsigned int bank);

40
plat/st/common/stm32mp_common.c
View File

@ -39,54 +39,22 @@ uintptr_t stm32mp_get_boot_ctx_address(void)
uintptr_t stm32mp_ddrctrl_base(void)
{
static uintptr_t ddrctrl_base;
if (ddrctrl_base == 0) {
ddrctrl_base = dt_get_ddrctrl_base();
assert(ddrctrl_base == DDRCTRL_BASE);
}
return ddrctrl_base;
return DDRCTRL_BASE;
}
uintptr_t stm32mp_ddrphyc_base(void)
{
static uintptr_t ddrphyc_base;
if (ddrphyc_base == 0) {
ddrphyc_base = dt_get_ddrphyc_base();
assert(ddrphyc_base == DDRPHYC_BASE);
}
return ddrphyc_base;
return DDRPHYC_BASE;
}
uintptr_t stm32mp_pwr_base(void)
{
static uintptr_t pwr_base;
if (pwr_base == 0) {
pwr_base = dt_get_pwr_base();
assert(pwr_base == PWR_BASE);
}
return pwr_base;
return PWR_BASE;
}
uintptr_t stm32mp_rcc_base(void)
{
static uintptr_t rcc_base;
if (rcc_base == 0) {
rcc_base = fdt_rcc_read_addr();
assert(rcc_base == RCC_BASE);
}
return rcc_base;
return RCC_BASE;
}
bool stm32mp_lock_available(void)

120
plat/st/common/stm32mp_dt.c
View File

@ -113,26 +113,6 @@ static int fdt_get_node_parent_address_cells(int node)
return fdt_address_cells(fdt, parent);
}
/*******************************************************************************
* This function returns the size cells from the node parent.
* Returns:
* - #size-cells value if success.
* - invalid value if error.
* - a default value if undefined #size-cells property as per libfdt
* implementation.
******************************************************************************/
static int fdt_get_node_parent_size_cells(int node)
{
int parent;
parent = fdt_parent_offset(fdt, node);
if (parent < 0) {
return -FDT_ERR_NOTFOUND;
}
return fdt_size_cells(fdt, parent);
}
#endif
/*******************************************************************************
@ -240,81 +220,6 @@ uint32_t dt_get_ddr_size(void)
return fdt_read_uint32_default(fdt, node, "st,mem-size", 0);
}
/*******************************************************************************
* This function gets DDRCTRL base address information from the DT.
* Returns value on success, and 0 on failure.
******************************************************************************/
uintptr_t dt_get_ddrctrl_base(void)
{
int node;
uint32_t array[4];
node = fdt_node_offset_by_compatible(fdt, -1, DT_DDR_COMPAT);
if (node < 0) {
INFO("%s: Cannot read DDR node in DT\n", __func__);
return 0;
}
assert((fdt_get_node_parent_address_cells(node) == 1) &&
(fdt_get_node_parent_size_cells(node) == 1));
if (fdt_read_uint32_array(fdt, node, "reg", 4, array) < 0) {
return 0;
}
return array[0];
}
/*******************************************************************************
* This function gets DDRPHYC base address information from the DT.
* Returns value on success, and 0 on failure.
******************************************************************************/
uintptr_t dt_get_ddrphyc_base(void)
{
int node;
uint32_t array[4];
node = fdt_node_offset_by_compatible(fdt, -1, DT_DDR_COMPAT);
if (node < 0) {
INFO("%s: Cannot read DDR node in DT\n", __func__);
return 0;
}
assert((fdt_get_node_parent_address_cells(node) == 1) &&
(fdt_get_node_parent_size_cells(node) == 1));
if (fdt_read_uint32_array(fdt, node, "reg", 4, array) < 0) {
return 0;
}
return array[2];
}
/*******************************************************************************
* This function gets PWR base address information from the DT.
* Returns value on success, and 0 on failure.
******************************************************************************/
uintptr_t dt_get_pwr_base(void)
{
int node;
const fdt32_t *cuint;
node = fdt_node_offset_by_compatible(fdt, -1, DT_PWR_COMPAT);
if (node < 0) {
INFO("%s: Cannot read PWR node in DT\n", __func__);
return 0;
}
assert(fdt_get_node_parent_address_cells(node) == 1);
cuint = fdt_getprop(fdt, node, "reg", NULL);
if (cuint == NULL) {
return 0;
}
return fdt32_to_cpu(*cuint);
}
/*******************************************************************************
* This function gets PWR VDD regulator voltage information from the DT.
* Returns value in microvolts on success, and 0 on failure.
@ -354,31 +259,6 @@ uint32_t dt_get_pwr_vdd_voltage(void)
return fdt32_to_cpu(*cuint);
}
/*******************************************************************************
* This function gets SYSCFG base address information from the DT.
* Returns value on success, and 0 on failure.
******************************************************************************/
uintptr_t dt_get_syscfg_base(void)
{
int node;
const fdt32_t *cuint;
node = fdt_node_offset_by_compatible(fdt, -1, DT_SYSCFG_COMPAT);
if (node < 0) {
INFO("%s: Cannot read SYSCFG node in DT\n", __func__);
return 0;
}
assert(fdt_get_node_parent_address_cells(node) == 1);
cuint = fdt_getprop(fdt, node, "reg", NULL);
if (cuint == NULL) {
return 0;
}
return fdt32_to_cpu(*cuint);
}
/*******************************************************************************
* This function retrieves board model from DT
* Returns string taken from model node, NULL otherwise

4
plat/st/stm32mp1/stm32mp1_def.h
View File

@ -506,6 +506,7 @@ static inline uint32_t tamp_bkpr(uint32_t idx)
/*******************************************************************************
* Miscellaneous STM32MP1 peripherals base address
******************************************************************************/
#define BSEC_BASE U(0x5C005000)
#define CRYP1_BASE U(0x54001000)
#define DBGMCU_BASE U(0x50081000)
#define HASH1_BASE U(0x54002000)
@ -514,6 +515,8 @@ static inline uint32_t tamp_bkpr(uint32_t idx)
#define RNG1_BASE U(0x54003000)
#define RTC_BASE U(0x5c004000)
#define SPI6_BASE U(0x5c001000)
#define STGEN_BASE U(0x5c008000)
#define SYSCFG_BASE U(0x50020000)
/*******************************************************************************
* Device Tree defines
@ -522,6 +525,5 @@ static inline uint32_t tamp_bkpr(uint32_t idx)
#define DT_IWDG_COMPAT "st,stm32mp1-iwdg"
#define DT_PWR_COMPAT "st,stm32mp1,pwr-reg"
#define DT_RCC_CLK_COMPAT "st,stm32mp1-rcc"
#define DT_SYSCFG_COMPAT "st,stm32mp157-syscfg"
#endif /* STM32MP1_DEF_H */

17
plat/st/stm32mp1/stm32mp1_private.c
View File

@ -16,18 +16,22 @@
/* Internal layout of the 32bit OTP word board_id */
#define BOARD_ID_BOARD_NB_MASK GENMASK(31, 16)
#define BOARD_ID_BOARD_NB_SHIFT 16
#define BOARD_ID_VARIANT_MASK GENMASK(15, 12)
#define BOARD_ID_VARIANT_SHIFT 12
#define BOARD_ID_VARCPN_MASK GENMASK(15, 12)
#define BOARD_ID_VARCPN_SHIFT 12
#define BOARD_ID_REVISION_MASK GENMASK(11, 8)
#define BOARD_ID_REVISION_SHIFT 8
#define BOARD_ID_VARFG_MASK GENMASK(7, 4)
#define BOARD_ID_VARFG_SHIFT 4
#define BOARD_ID_BOM_MASK GENMASK(3, 0)
#define BOARD_ID2NB(_id) (((_id) & BOARD_ID_BOARD_NB_MASK) >> \
BOARD_ID_BOARD_NB_SHIFT)
#define BOARD_ID2VAR(_id) (((_id) & BOARD_ID_VARIANT_MASK) >> \
BOARD_ID_VARIANT_SHIFT)
#define BOARD_ID2VARCPN(_id) (((_id) & BOARD_ID_VARCPN_MASK) >> \
BOARD_ID_VARCPN_SHIFT)
#define BOARD_ID2REV(_id) (((_id) & BOARD_ID_REVISION_MASK) >> \
BOARD_ID_REVISION_SHIFT)
#define BOARD_ID2VARFG(_id) (((_id) & BOARD_ID_VARFG_MASK) >> \
BOARD_ID_VARFG_SHIFT)
#define BOARD_ID2BOM(_id) ((_id) & BOARD_ID_BOM_MASK)
#if defined(IMAGE_BL2)
@ -333,9 +337,10 @@ void stm32mp_print_boardinfo(void)
rev[0] = BOARD_ID2REV(board_id) - 1 + 'A';
rev[1] = '\0';
NOTICE("Board: MB%04x Var%d Rev.%s-%02d\n",
NOTICE("Board: MB%04x Var%d.%d Rev.%s-%02d\n",
BOARD_ID2NB(board_id),
BOARD_ID2VAR(board_id),
BOARD_ID2VARCPN(board_id),
BOARD_ID2VARFG(board_id),
rev,
BOARD_ID2BOM(board_id));
}

32
plat/st/stm32mp1/stm32mp1_syscfg.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2019, STMicroelectronics - All Rights Reserved
* Copyright (c) 2019-2020, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -63,18 +63,17 @@ void stm32mp1_syscfg_init(void)
uint32_t bootr;
uint32_t otp = 0;
uint32_t vdd_voltage;
uintptr_t syscfg_base = dt_get_syscfg_base();
/*
* Interconnect update : select master using the port 1.
* LTDC = AXI_M9.
*/
mmio_write_32(syscfg_base + SYSCFG_ICNR, SYSCFG_ICNR_AXI_M9);
mmio_write_32(SYSCFG_BASE + SYSCFG_ICNR, SYSCFG_ICNR_AXI_M9);
/* Disable Pull-Down for boot pin connected to VDD */
bootr = mmio_read_32(syscfg_base + SYSCFG_BOOTR) &
bootr = mmio_read_32(SYSCFG_BASE + SYSCFG_BOOTR) &
SYSCFG_BOOTR_BOOT_MASK;
mmio_clrsetbits_32(syscfg_base + SYSCFG_BOOTR, SYSCFG_BOOTR_BOOTPD_MASK,
mmio_clrsetbits_32(SYSCFG_BASE + SYSCFG_BOOTR, SYSCFG_BOOTR_BOOTPD_MASK,
bootr << SYSCFG_BOOTR_BOOTPD_SHIFT);
/*
@ -105,7 +104,7 @@ void stm32mp1_syscfg_init(void)
if (vdd_voltage == 0U) {
WARN("VDD unknown");
} else if (vdd_voltage < 2700000U) {
mmio_write_32(syscfg_base + SYSCFG_IOCTRLSETR,
mmio_write_32(SYSCFG_BASE + SYSCFG_IOCTRLSETR,
SYSCFG_IOCTRLSETR_HSLVEN_TRACE |
SYSCFG_IOCTRLSETR_HSLVEN_QUADSPI |
SYSCFG_IOCTRLSETR_HSLVEN_ETH |
@ -129,8 +128,6 @@ void stm32mp1_syscfg_init(void)
void stm32mp1_syscfg_enable_io_compensation(void)
{
uintptr_t syscfg_base = dt_get_syscfg_base();
/*
* Activate automatic I/O compensation.
* Warning: need to ensure CSI enabled and ready in clock driver.
@ -138,20 +135,19 @@ void stm32mp1_syscfg_enable_io_compensation(void)
*/
stm32mp1_clk_enable_non_secure(SYSCFG);
mmio_setbits_32(syscfg_base + SYSCFG_CMPENSETR,
mmio_setbits_32(SYSCFG_BASE + SYSCFG_CMPENSETR,
SYSCFG_CMPENSETR_MPU_EN);
while ((mmio_read_32(syscfg_base + SYSCFG_CMPCR) &
while ((mmio_read_32(SYSCFG_BASE + SYSCFG_CMPCR) &
SYSCFG_CMPCR_READY) == 0U) {
;
}
mmio_clrbits_32(syscfg_base + SYSCFG_CMPCR, SYSCFG_CMPCR_SW_CTRL);
mmio_clrbits_32(SYSCFG_BASE + SYSCFG_CMPCR, SYSCFG_CMPCR_SW_CTRL);
}
void stm32mp1_syscfg_disable_io_compensation(void)
{
uintptr_t syscfg_base = dt_get_syscfg_base();
uint32_t value;
/*
@ -160,20 +156,18 @@ void stm32mp1_syscfg_disable_io_compensation(void)
* requested for other usages and always OFF in STANDBY.
* Disable non-secure SYSCFG clock, we assume non-secure is suspended.
*/
value = mmio_read_32(syscfg_base + SYSCFG_CMPCR) >>
value = mmio_read_32(SYSCFG_BASE + SYSCFG_CMPCR) >>
SYSCFG_CMPCR_ANSRC_SHIFT;
mmio_clrbits_32(syscfg_base + SYSCFG_CMPCR,
mmio_clrbits_32(SYSCFG_BASE + SYSCFG_CMPCR,
SYSCFG_CMPCR_RANSRC | SYSCFG_CMPCR_RAPSRC);
value = mmio_read_32(syscfg_base + SYSCFG_CMPCR) |
value = mmio_read_32(SYSCFG_BASE + SYSCFG_CMPCR) |
(value << SYSCFG_CMPCR_RANSRC_SHIFT);
mmio_write_32(syscfg_base + SYSCFG_CMPCR, value);
mmio_write_32(SYSCFG_BASE + SYSCFG_CMPCR, value | SYSCFG_CMPCR_SW_CTRL);
mmio_setbits_32(syscfg_base + SYSCFG_CMPCR, SYSCFG_CMPCR_SW_CTRL);
mmio_clrbits_32(syscfg_base + SYSCFG_CMPENSETR,
mmio_clrbits_32(SYSCFG_BASE + SYSCFG_CMPENSETR,
SYSCFG_CMPENSETR_MPU_EN);
stm32mp1_clk_disable_non_secure(SYSCFG);