Merge changes I36e45c0a,I69c21293 into integration
* changes: plat/qemu: add "max" cpu support Add support for QEMU "max" CPU
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/*
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* Copyright (c) 2014-2021, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef QEMU_MAX_H
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#define QEMU_MAX_H
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#include <lib/utils_def.h>
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/*
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* QEMU MAX midr for revision 0
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* 00 - Reserved for software use
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* 0 - Variant
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* F - Architectural features identified in ID_* registers
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* 051 - 'Q', in a 12-bit field.
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* 0 - Revision
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*/
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#define QEMU_MAX_MIDR U(0x000F0510)
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#endif /* QEMU_MAX_H */
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/*
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* Copyright (c) 2014-2021, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <cpu_macros.S>
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#include <qemu_max.h>
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func qemu_max_core_pwr_dwn
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/* ---------------------------------------------
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* Disable the Data Cache.
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* ---------------------------------------------
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*/
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mrs x1, sctlr_el3
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bic x1, x1, #SCTLR_C_BIT
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msr sctlr_el3, x1
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isb
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/* ---------------------------------------------
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* Flush L1 cache to L2.
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* ---------------------------------------------
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*/
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mov x18, lr
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mov x0, #DCCISW
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bl dcsw_op_level1
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mov lr, x18
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ret
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endfunc qemu_max_core_pwr_dwn
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func qemu_max_cluster_pwr_dwn
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/* ---------------------------------------------
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* Disable the Data Cache.
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* ---------------------------------------------
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*/
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mrs x1, sctlr_el3
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bic x1, x1, #SCTLR_C_BIT
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msr sctlr_el3, x1
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isb
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/* ---------------------------------------------
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* Flush all caches to PoC.
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* ---------------------------------------------
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*/
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mov x0, #DCCISW
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b dcsw_op_all
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endfunc qemu_max_cluster_pwr_dwn
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#if REPORT_ERRATA
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/*
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* Errata printing function for QEMU "max". Must follow AAPCS.
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*/
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func qemu_max_errata_report
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ret
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endfunc qemu_max_errata_report
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#endif
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/* ---------------------------------------------
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* This function provides cpu specific
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* register information for crash reporting.
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* It needs to return with x6 pointing to
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* a list of register names in ascii and
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* x8 - x15 having values of registers to be
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* reported.
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* ---------------------------------------------
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*/
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.section .rodata.qemu_max_regs, "aS"
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qemu_max_regs: /* The ascii list of register names to be reported */
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.asciz "" /* no registers to report */
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func qemu_max_cpu_reg_dump
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adr x6, qemu_max_regs
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ret
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endfunc qemu_max_cpu_reg_dump
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/* cpu_ops for QEMU MAX */
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declare_cpu_ops qemu_max, QEMU_MAX_MIDR, CPU_NO_RESET_FUNC, \
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qemu_max_core_pwr_dwn, \
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qemu_max_cluster_pwr_dwn
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@ -109,6 +109,7 @@ BL1_SOURCES += lib/cpus/aarch64/aem_generic.S \
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lib/cpus/aarch64/cortex_a53.S \
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lib/cpus/aarch64/cortex_a57.S \
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lib/cpus/aarch64/cortex_a72.S \
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lib/cpus/aarch64/qemu_max.S \
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else
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BL1_SOURCES += lib/cpus/${ARCH}/cortex_a15.S
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@ -163,6 +164,7 @@ BL31_SOURCES += lib/cpus/aarch64/aem_generic.S \
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lib/cpus/aarch64/cortex_a53.S \
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lib/cpus/aarch64/cortex_a57.S \
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lib/cpus/aarch64/cortex_a72.S \
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lib/cpus/aarch64/qemu_max.S \
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lib/semihosting/semihosting.c \
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lib/semihosting/${ARCH}/semihosting_call.S \
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plat/common/plat_psci_common.c \
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@ -48,7 +48,8 @@ BL1_SOURCES += drivers/io/io_semihosting.c \
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${PLAT_QEMU_COMMON_PATH}/qemu_bl1_setup.c
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BL1_SOURCES += lib/cpus/aarch64/cortex_a57.S \
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lib/cpus/aarch64/cortex_a72.S
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lib/cpus/aarch64/cortex_a72.S \
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lib/cpus/aarch64/qemu_max.S \
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BL2_SOURCES += drivers/io/io_semihosting.c \
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drivers/io/io_storage.c \
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@ -76,6 +77,7 @@ QEMU_GIC_SOURCES := ${GICV3_SOURCES} \
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BL31_SOURCES += lib/cpus/aarch64/cortex_a57.S \
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lib/cpus/aarch64/cortex_a72.S \
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lib/cpus/aarch64/qemu_max.S \
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lib/semihosting/semihosting.c \
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lib/semihosting/${ARCH}/semihosting_call.S \
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plat/common/plat_psci_common.c \
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