mediatek: mt8192: Add CPU hotplug and MCDI support
Implement PSCI platform OPs to support CPU hotplug and MCDI. Change-Id: I31abfc752b69ac40e70bc9e7a55163eb39776c44 Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
This commit is contained in:
James Liao
Manish Pandey
parent
271d9497dc
commit
82c00c2ff5
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@ -70,11 +70,12 @@
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******************************************************************************/
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#define PLATFORM_STACK_SIZE 0x800
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#define PLAT_MAX_PWR_LVL U(2)
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#define PLAT_MAX_PWR_LVL U(3)
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#define PLAT_MAX_RET_STATE U(1)
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#define PLAT_MAX_OFF_STATE U(2)
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#define PLAT_MAX_OFF_STATE U(9)
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#define PLATFORM_SYSTEM_COUNT U(1)
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#define PLATFORM_MCUSYS_COUNT U(1)
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#define PLATFORM_CLUSTER_COUNT U(1)
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#define PLATFORM_CLUSTER0_CORE_COUNT U(8)
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#define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER0_CORE_COUNT)
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@ -5,17 +5,335 @@
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*/
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/* common headers */
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#include <assert.h>
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#include <arch_helpers.h>
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#include <common/debug.h>
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#include <drivers/gpio.h>
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#include <lib/psci/psci.h>
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/* mediatek platform specific headers */
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/* platform specific headers */
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#include <mt_gic_v3.h>
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#include <mtspmc.h>
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#include <plat/common/platform.h>
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#include <plat_mtk_lpm.h>
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#include <plat_params.h>
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#include <plat_pm.h>
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/*
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* Cluster state request:
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* [0] : The CPU requires cluster power down
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* [1] : The CPU requires cluster power on
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*/
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#define coordinate_cluster(onoff) write_clusterpwrdn_el1(onoff)
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#define coordinate_cluster_pwron() coordinate_cluster(1)
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#define coordinate_cluster_pwroff() coordinate_cluster(0)
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/* platform secure entry point */
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static uintptr_t secure_entrypoint;
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/* per-CPU power state */
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static unsigned int plat_power_state[PLATFORM_CORE_COUNT];
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/* platform CPU power domain - ops */
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static const struct mt_lpm_tz *plat_mt_pm;
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#define plat_mt_pm_invoke(_name, _cpu, _state) ({ \
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int ret = -1; \
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if (plat_mt_pm != NULL && plat_mt_pm->_name != NULL) { \
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ret = plat_mt_pm->_name(_cpu, _state); \
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} \
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ret; })
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#define plat_mt_pm_invoke_no_check(_name, _cpu, _state) ({ \
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if (plat_mt_pm != NULL && plat_mt_pm->_name != NULL) { \
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(void) plat_mt_pm->_name(_cpu, _state); \
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} \
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})
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/*
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* Common MTK_platform operations to power on/off a
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* CPU in response to a CPU_ON, CPU_OFF or CPU_SUSPEND request.
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*/
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static void plat_cpu_pwrdwn_common(unsigned int cpu,
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const psci_power_state_t *state, unsigned int req_pstate)
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{
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assert(cpu == plat_my_core_pos());
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plat_mt_pm_invoke_no_check(pwr_cpu_dwn, cpu, state);
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if ((psci_get_pstate_pwrlvl(req_pstate) >= MTK_AFFLVL_CLUSTER) ||
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(req_pstate == 0U)) { /* hotplug off */
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coordinate_cluster_pwroff();
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}
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/* Prevent interrupts from spuriously waking up this CPU */
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mt_gic_rdistif_save();
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gicv3_cpuif_disable(cpu);
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gicv3_rdistif_off(cpu);
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}
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static void plat_cpu_pwron_common(unsigned int cpu,
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const psci_power_state_t *state, unsigned int req_pstate)
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{
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assert(cpu == plat_my_core_pos());
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plat_mt_pm_invoke_no_check(pwr_cpu_on, cpu, state);
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coordinate_cluster_pwron();
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/* Enable the GIC CPU interface */
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gicv3_rdistif_on(cpu);
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gicv3_cpuif_enable(cpu);
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mt_gic_rdistif_init();
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/*
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* If mcusys does power down before then restore
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* all CPUs' GIC Redistributors
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*/
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if (IS_MCUSYS_OFF_STATE(state)) {
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mt_gic_rdistif_restore_all();
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} else {
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mt_gic_rdistif_restore();
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}
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}
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/*
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* Common MTK_platform operations to power on/off a
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* cluster in response to a CPU_ON, CPU_OFF or CPU_SUSPEND request.
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*/
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static void plat_cluster_pwrdwn_common(unsigned int cpu,
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const psci_power_state_t *state, unsigned int req_pstate)
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{
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assert(cpu == plat_my_core_pos());
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if (plat_mt_pm_invoke(pwr_cluster_dwn, cpu, state) != 0) {
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coordinate_cluster_pwron();
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/* TODO: return on fail.
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* Add a 'return' here before adding any code following
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* the if-block.
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*/
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}
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}
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static void plat_cluster_pwron_common(unsigned int cpu,
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const psci_power_state_t *state, unsigned int req_pstate)
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{
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assert(cpu == plat_my_core_pos());
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if (plat_mt_pm_invoke(pwr_cluster_on, cpu, state) != 0) {
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/* TODO: return on fail.
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* Add a 'return' here before adding any code following
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* the if-block.
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*/
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}
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}
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/*
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* Common MTK_platform operations to power on/off a
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* mcusys in response to a CPU_ON, CPU_OFF or CPU_SUSPEND request.
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*/
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static void plat_mcusys_pwrdwn_common(unsigned int cpu,
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const psci_power_state_t *state, unsigned int req_pstate)
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{
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assert(cpu == plat_my_core_pos());
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if (plat_mt_pm_invoke(pwr_mcusys_dwn, cpu, state) != 0) {
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return; /* return on fail */
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}
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mt_gic_distif_save();
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gic_sgi_save_all();
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}
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static void plat_mcusys_pwron_common(unsigned int cpu,
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const psci_power_state_t *state, unsigned int req_pstate)
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{
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assert(cpu == plat_my_core_pos());
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if (plat_mt_pm_invoke(pwr_mcusys_on, cpu, state) != 0) {
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return; /* return on fail */
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}
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mt_gic_init();
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mt_gic_distif_restore();
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gic_sgi_restore_all();
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plat_mt_pm_invoke_no_check(pwr_mcusys_on_finished, cpu, state);
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}
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/*
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* plat_psci_ops implementation
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*/
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static void plat_cpu_standby(plat_local_state_t cpu_state)
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{
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uint64_t scr;
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scr = read_scr_el3();
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write_scr_el3(scr | SCR_IRQ_BIT | SCR_FIQ_BIT);
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isb();
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dsb();
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wfi();
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write_scr_el3(scr);
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}
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static int plat_power_domain_on(u_register_t mpidr)
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{
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unsigned int cpu = (unsigned int)plat_core_pos_by_mpidr(mpidr);
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unsigned int cluster = 0U;
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if (cpu >= PLATFORM_CORE_COUNT) {
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return PSCI_E_INVALID_PARAMS;
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}
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if (!spm_get_cluster_powerstate(cluster)) {
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spm_poweron_cluster(cluster);
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}
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/* init CPU reset arch as AARCH64 */
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mcucfg_init_archstate(cluster, cpu, true);
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mcucfg_set_bootaddr(cluster, cpu, secure_entrypoint);
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spm_poweron_cpu(cluster, cpu);
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return PSCI_E_SUCCESS;
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}
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static void plat_power_domain_on_finish(const psci_power_state_t *state)
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{
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unsigned long mpidr = read_mpidr_el1();
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unsigned int cpu = (unsigned int)plat_core_pos_by_mpidr(mpidr);
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assert(cpu < PLATFORM_CORE_COUNT);
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/* Allow IRQs to wakeup this core in IDLE flow */
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mcucfg_enable_gic_wakeup(0U, cpu);
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if (IS_CLUSTER_OFF_STATE(state)) {
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plat_cluster_pwron_common(cpu, state, 0U);
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}
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plat_cpu_pwron_common(cpu, state, 0U);
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}
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static void plat_power_domain_off(const psci_power_state_t *state)
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{
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unsigned long mpidr = read_mpidr_el1();
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unsigned int cpu = (unsigned int)plat_core_pos_by_mpidr(mpidr);
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assert(cpu < PLATFORM_CORE_COUNT);
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plat_cpu_pwrdwn_common(cpu, state, 0U);
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spm_poweroff_cpu(0U, cpu);
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/* prevent unintended IRQs from waking up the hot-unplugged core */
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mcucfg_disable_gic_wakeup(0U, cpu);
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if (IS_CLUSTER_OFF_STATE(state)) {
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plat_cluster_pwrdwn_common(cpu, state, 0U);
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}
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}
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static void plat_power_domain_suspend(const psci_power_state_t *state)
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{
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unsigned int cpu = plat_my_core_pos();
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assert(cpu < PLATFORM_CORE_COUNT);
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plat_mt_pm_invoke_no_check(pwr_prompt, cpu, state);
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/* Perform the common CPU specific operations */
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plat_cpu_pwrdwn_common(cpu, state, plat_power_state[cpu]);
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if (IS_CLUSTER_OFF_STATE(state)) {
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/* Perform the common cluster specific operations */
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plat_cluster_pwrdwn_common(cpu, state, plat_power_state[cpu]);
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}
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if (IS_MCUSYS_OFF_STATE(state)) {
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/* Perform the common mcusys specific operations */
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plat_mcusys_pwrdwn_common(cpu, state, plat_power_state[cpu]);
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}
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}
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static void plat_power_domain_suspend_finish(const psci_power_state_t *state)
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{
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unsigned int cpu = plat_my_core_pos();
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assert(cpu < PLATFORM_CORE_COUNT);
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if (IS_MCUSYS_OFF_STATE(state)) {
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/* Perform the common mcusys specific operations */
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plat_mcusys_pwron_common(cpu, state, plat_power_state[cpu]);
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}
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if (IS_CLUSTER_OFF_STATE(state)) {
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/* Perform the common cluster specific operations */
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plat_cluster_pwron_common(cpu, state, plat_power_state[cpu]);
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}
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/* Perform the common CPU specific operations */
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plat_cpu_pwron_common(cpu, state, plat_power_state[cpu]);
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plat_mt_pm_invoke_no_check(pwr_reflect, cpu, state);
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}
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static int plat_validate_power_state(unsigned int power_state,
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psci_power_state_t *req_state)
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{
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unsigned int pstate = psci_get_pstate_type(power_state);
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unsigned int aff_lvl = psci_get_pstate_pwrlvl(power_state);
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unsigned int cpu = plat_my_core_pos();
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if (aff_lvl > PLAT_MAX_PWR_LVL) {
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return PSCI_E_INVALID_PARAMS;
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}
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if (pstate == PSTATE_TYPE_STANDBY) {
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req_state->pwr_domain_state[0] = PLAT_MAX_RET_STATE;
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} else {
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unsigned int i;
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unsigned int pstate_id = psci_get_pstate_id(power_state);
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plat_local_state_t s = MTK_LOCAL_STATE_OFF;
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/* Use pstate_id to be power domain state */
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if (pstate_id > s) {
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s = (plat_local_state_t)pstate_id;
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}
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for (i = 0U; i <= aff_lvl; i++) {
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req_state->pwr_domain_state[i] = s;
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}
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}
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plat_power_state[cpu] = power_state;
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return PSCI_E_SUCCESS;
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}
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static void plat_get_sys_suspend_power_state(psci_power_state_t *req_state)
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{
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unsigned int lv;
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unsigned int cpu = plat_my_core_pos();
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for (lv = PSCI_CPU_PWR_LVL; lv <= PLAT_MAX_PWR_LVL; lv++) {
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req_state->pwr_domain_state[lv] = PLAT_MAX_OFF_STATE;
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}
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plat_power_state[cpu] =
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psci_make_powerstate(
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MT_PLAT_PWR_STATE_SYSTEM_SUSPEND,
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PSTATE_TYPE_POWERDOWN, PLAT_MAX_PWR_LVL);
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flush_dcache_range((uintptr_t)
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&plat_power_state[cpu],
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sizeof(plat_power_state[cpu]));
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}
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/*******************************************************************************
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* MTK handlers to shutdown/reboot the system
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******************************************************************************/
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static void __dead2 plat_mtk_system_reset(void)
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{
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struct bl_aux_gpio_info *gpio_reset = plat_get_mtk_gpio_reset();
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@ -29,18 +347,34 @@ static void __dead2 plat_mtk_system_reset(void)
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panic();
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}
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/*******************************************************************************
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* MTK_platform handler called when an affinity instance is about to be turned
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* on. The level and mpidr determine the affinity instance.
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******************************************************************************/
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static const plat_psci_ops_t plat_plat_pm_ops = {
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.system_reset = plat_mtk_system_reset,
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static const plat_psci_ops_t plat_psci_ops = {
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.system_reset = plat_mtk_system_reset,
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.cpu_standby = plat_cpu_standby,
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.pwr_domain_on = plat_power_domain_on,
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.pwr_domain_on_finish = plat_power_domain_on_finish,
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.pwr_domain_off = plat_power_domain_off,
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.pwr_domain_suspend = plat_power_domain_suspend,
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.pwr_domain_suspend_finish = plat_power_domain_suspend_finish,
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.validate_power_state = plat_validate_power_state,
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.get_sys_suspend_power_state = plat_get_sys_suspend_power_state
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};
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int plat_setup_psci_ops(uintptr_t sec_entrypoint,
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const plat_psci_ops_t **psci_ops)
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{
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*psci_ops = &plat_plat_pm_ops;
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*psci_ops = &plat_psci_ops;
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secure_entrypoint = sec_entrypoint;
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/*
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* init the warm reset config for boot CPU
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* reset arch as AARCH64
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* reset addr as function bl31_warm_entrypoint()
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*/
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mcucfg_init_archstate(0U, 0U, true);
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mcucfg_set_bootaddr(0U, 0U, secure_entrypoint);
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spmc_init();
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plat_mt_pm = mt_plat_cpu_pm_init();
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return 0;
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}
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@ -17,6 +17,8 @@ const unsigned char mtk_power_domain_tree_desc[] = {
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/* Number of root nodes */
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PLATFORM_SYSTEM_COUNT,
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/* Number of children for the root node */
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PLATFORM_MCUSYS_COUNT,
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/* Number of children for the mcusys node */
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PLATFORM_CLUSTER_COUNT,
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/* Number of children for the first cluster node */
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PLATFORM_CLUSTER0_CORE_COUNT,
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