poplar: Migrate to new interfaces
- Remove support for LOAD_IMAGE_V2=0. - Replace deprecated bl1_init_bl2_mem_layout(). - Migrate to bl2_early_platform_setup2(). - Migrate to bl31_early_platform_setup2(). - Use PLAT_VIRT_ADDR_SPACE_SIZE and PLAT_PHY_ADDR_SPACE_SIZE. - Remove references to removed build options. - Update Makefile paths. Change-Id: I52e02633365b3db4244f7ff0f99a6446eae619f0 Tested-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
This commit is contained in:
parent
8cff97d1b4
commit
82fbaa33e8
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@ -5,7 +5,6 @@
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*/
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*/
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#include <arch_helpers.h>
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#include <arch_helpers.h>
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#include <arm_gic.h>
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#include <assert.h>
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#include <assert.h>
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#include <bl_common.h>
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#include <bl_common.h>
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#include <debug.h>
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#include <debug.h>
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@ -29,23 +28,19 @@
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TSP_SEC_MEM_SIZE, \
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TSP_SEC_MEM_SIZE, \
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MT_MEMORY | MT_RW | MT_SECURE)
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MT_MEMORY | MT_RW | MT_SECURE)
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#if LOAD_IMAGE_V2
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#ifdef SPD_opteed
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#ifdef SPD_opteed
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#define MAP_OPTEE_PAGEABLE MAP_REGION_FLAT( \
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#define MAP_OPTEE_PAGEABLE MAP_REGION_FLAT( \
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POPLAR_OPTEE_PAGEABLE_LOAD_BASE, \
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POPLAR_OPTEE_PAGEABLE_LOAD_BASE, \
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POPLAR_OPTEE_PAGEABLE_LOAD_SIZE, \
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POPLAR_OPTEE_PAGEABLE_LOAD_SIZE, \
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MT_MEMORY | MT_RW | MT_SECURE)
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MT_MEMORY | MT_RW | MT_SECURE)
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#endif
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#endif
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#endif
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static const mmap_region_t poplar_mmap[] = {
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static const mmap_region_t poplar_mmap[] = {
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MAP_DDR,
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MAP_DDR,
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MAP_DEVICE,
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MAP_DEVICE,
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MAP_TSP_MEM,
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MAP_TSP_MEM,
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#if LOAD_IMAGE_V2
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#ifdef SPD_opteed
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#ifdef SPD_opteed
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MAP_OPTEE_PAGEABLE,
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MAP_OPTEE_PAGEABLE,
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#endif
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#endif
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#endif
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{0}
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{0}
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};
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};
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@ -25,36 +25,40 @@
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/* Data structure which holds the extents of the trusted RAM for BL1 */
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/* Data structure which holds the extents of the trusted RAM for BL1 */
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static meminfo_t bl1_tzram_layout;
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static meminfo_t bl1_tzram_layout;
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static meminfo_t bl2_tzram_layout;
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meminfo_t *bl1_plat_sec_mem_layout(void)
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/*
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* Cannot use default weak implementation in bl1_main.c because BL1 RW data is
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* not at the top of the secure memory.
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*/
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int bl1_plat_handle_post_image_load(unsigned int image_id)
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{
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{
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return &bl1_tzram_layout;
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image_desc_t *image_desc;
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entry_point_info_t *ep_info;
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if (image_id != BL2_IMAGE_ID)
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return 0;
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/* Get the image descriptor */
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image_desc = bl1_plat_get_image_desc(BL2_IMAGE_ID);
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assert(image_desc != NULL);
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/* Get the entry point info */
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ep_info = &image_desc->ep_info;
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bl2_tzram_layout.total_base = BL2_BASE;
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bl2_tzram_layout.total_size = BL32_LIMIT - BL2_BASE;
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flush_dcache_range((uintptr_t)&bl2_tzram_layout, sizeof(meminfo_t));
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ep_info->args.arg1 = (uintptr_t)&bl2_tzram_layout;
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VERBOSE("BL1: BL2 memory layout address = %p\n",
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(void *)&bl2_tzram_layout);
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return 0;
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}
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}
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#if LOAD_IMAGE_V2
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/*******************************************************************************
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* Function that takes a memory layout into which BL2 has been loaded and
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* populates a new memory layout for BL2 that ensures that BL1's data sections
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* resident in secure RAM are not visible to BL2.
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******************************************************************************/
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void bl1_init_bl2_mem_layout(const meminfo_t *bl1_mem_layout,
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meminfo_t *bl2_mem_layout)
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{
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assert(bl1_mem_layout != NULL);
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assert(bl2_mem_layout != NULL);
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/*
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* Cannot use default weak implementation in bl1main.c because
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* BL1 RW data is not at the top of bl1_mem_layout
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*/
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bl2_mem_layout->total_base = BL2_BASE;
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bl2_mem_layout->total_size = BL32_LIMIT - BL2_BASE;
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flush_dcache_range((unsigned long)bl2_mem_layout, sizeof(meminfo_t));
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}
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#endif /* LOAD_IMAGE_V2 */
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void bl1_early_platform_setup(void)
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void bl1_early_platform_setup(void)
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{
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{
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/* Initialize the console to provide early debug support */
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/* Initialize the console to provide early debug support */
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@ -64,17 +68,6 @@ void bl1_early_platform_setup(void)
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bl1_tzram_layout.total_base = BL1_RW_BASE;
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bl1_tzram_layout.total_base = BL1_RW_BASE;
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bl1_tzram_layout.total_size = BL1_RW_SIZE;
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bl1_tzram_layout.total_size = BL1_RW_SIZE;
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#if !LOAD_IMAGE_V2
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/* Calculate how much RAM BL1 is using and how much remains free */
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bl1_tzram_layout.free_base = BL1_RW_BASE;
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bl1_tzram_layout.free_size = BL1_RW_SIZE;
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reserve_mem(&bl1_tzram_layout.free_base,
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&bl1_tzram_layout.free_size,
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BL1_RAM_BASE,
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BL1_RAM_LIMIT - BL1_RAM_BASE);
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#endif
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INFO("BL1: 0x%lx - 0x%lx [size = %zu]\n", BL1_RAM_BASE, BL1_RAM_LIMIT,
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INFO("BL1: 0x%lx - 0x%lx [size = %zu]\n", BL1_RAM_BASE, BL1_RAM_LIMIT,
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BL1_RAM_LIMIT - BL1_RAM_BASE);
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BL1_RAM_LIMIT - BL1_RAM_BASE);
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}
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}
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static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE);
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static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE);
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#if !LOAD_IMAGE_V2
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/*******************************************************************************
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* This structure represents the superset of information that is passed to
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* BL31, e.g. while passing control to it from BL2, bl31_params
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* and other platform specific params
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******************************************************************************/
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typedef struct bl2_to_bl31_params_mem {
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bl31_params_t bl31_params;
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image_info_t bl31_image_info;
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image_info_t bl32_image_info;
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image_info_t bl33_image_info;
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entry_point_info_t bl33_ep_info;
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entry_point_info_t bl32_ep_info;
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entry_point_info_t bl31_ep_info;
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} bl2_to_bl31_params_mem_t;
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static bl2_to_bl31_params_mem_t bl31_params_mem;
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meminfo_t *bl2_plat_sec_mem_layout(void)
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{
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return &bl2_tzram_layout;
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}
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#ifdef SCP_BL2_BASE
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void bl2_plat_get_scp_bl2_meminfo(meminfo_t *scp_bl2_meminfo)
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{
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/*
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* This platform has no SCP_BL2 yet
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*/
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}
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#endif
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#endif /* LOAD_IMAGE_V2 */
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/*******************************************************************************
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/*******************************************************************************
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* Transfer SCP_BL2 from Trusted RAM using the SCP Download protocol.
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* Transfer SCP_BL2 from Trusted RAM using the SCP Download protocol.
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* Return 0 on success, -1 otherwise.
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* Return 0 on success, -1 otherwise.
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******************************************************************************/
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******************************************************************************/
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#if LOAD_IMAGE_V2
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int plat_poplar_bl2_handle_scp_bl2(image_info_t *scp_bl2_image_info)
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int plat_poplar_bl2_handle_scp_bl2(image_info_t *scp_bl2_image_info)
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#else
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int bl2_plat_handle_scp_bl2(struct image_info *scp_bl2_image_info)
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#endif
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{
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{
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/*
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/*
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* This platform has no SCP_BL2 yet
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* This platform has no SCP_BL2 yet
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@ -138,7 +100,6 @@ uint32_t poplar_get_spsr_for_bl33_entry(void)
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}
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}
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#endif /* AARCH32 */
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#endif /* AARCH32 */
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#if LOAD_IMAGE_V2
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int poplar_bl2_handle_post_image_load(unsigned int image_id)
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int poplar_bl2_handle_post_image_load(unsigned int image_id)
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{
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{
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int err = 0;
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int err = 0;
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return poplar_bl2_handle_post_image_load(image_id);
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return poplar_bl2_handle_post_image_load(image_id);
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}
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}
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#else /* LOAD_IMAGE_V2 */
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void bl2_early_platform_setup2(u_register_t arg0, u_register_t arg1,
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u_register_t arg2, u_register_t arg3)
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bl31_params_t *bl2_plat_get_bl31_params(void)
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{
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bl31_params_t *bl2_to_bl31_params = NULL;
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/*
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* Initialise the memory for all the arguments that needs to
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* be passed to BL3-1
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*/
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memset(&bl31_params_mem, 0, sizeof(bl2_to_bl31_params_mem_t));
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/* Assign memory for TF related information */
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bl2_to_bl31_params = &bl31_params_mem.bl31_params;
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SET_PARAM_HEAD(bl2_to_bl31_params, PARAM_BL31, VERSION_1, 0);
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/* Fill BL3-1 related information */
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bl2_to_bl31_params->bl31_image_info = &bl31_params_mem.bl31_image_info;
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SET_PARAM_HEAD(bl2_to_bl31_params->bl31_image_info,
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PARAM_IMAGE_BINARY, VERSION_1, 0);
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/* Fill BL3-2 related information if it exists */
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#ifdef BL32_BASE
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bl2_to_bl31_params->bl32_ep_info = &bl31_params_mem.bl32_ep_info;
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SET_PARAM_HEAD(bl2_to_bl31_params->bl32_ep_info, PARAM_EP,
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VERSION_1, 0);
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bl2_to_bl31_params->bl32_image_info = &bl31_params_mem.bl32_image_info;
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SET_PARAM_HEAD(bl2_to_bl31_params->bl32_image_info, PARAM_IMAGE_BINARY,
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VERSION_1, 0);
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#endif
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/* Fill BL3-3 related information */
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bl2_to_bl31_params->bl33_ep_info = &bl31_params_mem.bl33_ep_info;
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SET_PARAM_HEAD(bl2_to_bl31_params->bl33_ep_info,
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PARAM_EP, VERSION_1, 0);
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/* BL3-3 expects to receive the primary CPU MPID (through x0) */
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bl2_to_bl31_params->bl33_ep_info->args.arg0 = 0xffff & read_mpidr();
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bl2_to_bl31_params->bl33_image_info = &bl31_params_mem.bl33_image_info;
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SET_PARAM_HEAD(bl2_to_bl31_params->bl33_image_info,
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PARAM_IMAGE_BINARY, VERSION_1, 0);
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return bl2_to_bl31_params;
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}
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struct entry_point_info *bl2_plat_get_bl31_ep_info(void)
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{
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#if DEBUG
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bl31_params_mem.bl31_ep_info.args.arg1 = POPLAR_BL31_PLAT_PARAM_VAL;
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#endif
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return &bl31_params_mem.bl31_ep_info;
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}
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void bl2_plat_set_bl31_ep_info(image_info_t *image,
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entry_point_info_t *bl31_ep_info)
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{
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SET_SECURITY_STATE(bl31_ep_info->h.attr, SECURE);
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bl31_ep_info->spsr = SPSR_64(MODE_EL3, MODE_SP_ELX,
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DISABLE_ALL_EXCEPTIONS);
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}
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/*******************************************************************************
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* Before calling this function BL32 is loaded in memory and its entrypoint
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* is set by load_image. This is a placeholder for the platform to change
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* the entrypoint of BL32 and set SPSR and security state.
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* On Poplar we only set the security state of the entrypoint
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******************************************************************************/
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#ifdef BL32_BASE
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void bl2_plat_set_bl32_ep_info(image_info_t *bl32_image_info,
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entry_point_info_t *bl32_ep_info)
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{
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SET_SECURITY_STATE(bl32_ep_info->h.attr, SECURE);
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/*
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* The Secure Payload Dispatcher service is responsible for
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* setting the SPSR prior to entry into the BL32 image.
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*/
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bl32_ep_info->spsr = 0;
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}
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/*******************************************************************************
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* Populate the extents of memory available for loading BL32
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******************************************************************************/
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void bl2_plat_get_bl32_meminfo(meminfo_t *bl32_meminfo)
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{
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/*
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* Populate the extents of memory available for loading BL32.
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*/
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bl32_meminfo->total_base = BL32_BASE;
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bl32_meminfo->free_base = BL32_BASE;
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bl32_meminfo->total_size =
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(TSP_SEC_MEM_BASE + TSP_SEC_MEM_SIZE) - BL32_BASE;
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bl32_meminfo->free_size =
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(TSP_SEC_MEM_BASE + TSP_SEC_MEM_SIZE) - BL32_BASE;
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}
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#endif /* BL32_BASE */
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void bl2_plat_set_bl33_ep_info(image_info_t *image,
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entry_point_info_t *bl33_ep_info)
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{
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SET_SECURITY_STATE(bl33_ep_info->h.attr, NON_SECURE);
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bl33_ep_info->spsr = poplar_get_spsr_for_bl33_entry();
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bl33_ep_info->args.arg2 = image->image_size;
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}
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void bl2_plat_flush_bl31_params(void)
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{
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flush_dcache_range((unsigned long)&bl31_params_mem,
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sizeof(bl2_to_bl31_params_mem_t));
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}
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void bl2_plat_get_bl33_meminfo(meminfo_t *bl33_meminfo)
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{
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bl33_meminfo->total_base = DDR_BASE;
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bl33_meminfo->total_size = DDR_SIZE;
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bl33_meminfo->free_base = DDR_BASE;
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bl33_meminfo->free_size = DDR_SIZE;
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}
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#endif /* LOAD_IMAGE_V2 */
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void bl2_early_platform_setup(meminfo_t *mem_layout)
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{
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{
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struct meminfo *mem_layout = (struct meminfo *)arg1;
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#if !POPLAR_RECOVERY
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#if !POPLAR_RECOVERY
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struct mmc_device_info info;
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struct mmc_device_info info;
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@ -6,7 +6,6 @@
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#include <arch.h>
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#include <arch.h>
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#include <arch_helpers.h>
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#include <arch_helpers.h>
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#include <arm_gic.h>
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#include <assert.h>
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#include <assert.h>
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#include <bl31.h>
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#include <bl31.h>
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#include <bl_common.h>
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#include <bl_common.h>
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@ -67,65 +66,45 @@ entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type)
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* while creating page tables. BL2 has flushed this information to memory, so
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* while creating page tables. BL2 has flushed this information to memory, so
|
||||||
* we are guaranteed to pick up good data.
|
* we are guaranteed to pick up good data.
|
||||||
******************************************************************************/
|
******************************************************************************/
|
||||||
#if LOAD_IMAGE_V2
|
void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
|
||||||
void bl31_early_platform_setup(void *from_bl2,
|
u_register_t arg2, u_register_t arg3)
|
||||||
void *plat_params_from_bl2)
|
|
||||||
#else
|
|
||||||
void bl31_early_platform_setup(bl31_params_t *from_bl2,
|
|
||||||
void *plat_params_from_bl2)
|
|
||||||
#endif
|
|
||||||
{
|
{
|
||||||
|
void *from_bl2;
|
||||||
|
|
||||||
|
from_bl2 = (void *) arg0;
|
||||||
|
|
||||||
console_init(PL011_UART0_BASE, PL011_UART0_CLK_IN_HZ, PL011_BAUDRATE);
|
console_init(PL011_UART0_BASE, PL011_UART0_CLK_IN_HZ, PL011_BAUDRATE);
|
||||||
|
|
||||||
/* Init console for crash report */
|
/* Init console for crash report */
|
||||||
plat_crash_console_init();
|
plat_crash_console_init();
|
||||||
|
|
||||||
#if LOAD_IMAGE_V2
|
|
||||||
/*
|
|
||||||
* Check params passed from BL2 should not be NULL,
|
|
||||||
*/
|
|
||||||
bl_params_t *params_from_bl2 = (bl_params_t *)from_bl2;
|
|
||||||
|
|
||||||
assert(params_from_bl2 != NULL);
|
|
||||||
assert(params_from_bl2->h.type == PARAM_BL_PARAMS);
|
|
||||||
assert(params_from_bl2->h.version >= VERSION_2);
|
|
||||||
|
|
||||||
bl_params_node_t *bl_params = params_from_bl2->head;
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Copy BL33 and BL32 (if present), entry point information.
|
|
||||||
* They are stored in Secure RAM, in BL2's address space.
|
|
||||||
*/
|
|
||||||
while (bl_params) {
|
|
||||||
if (bl_params->image_id == BL32_IMAGE_ID)
|
|
||||||
bl32_image_ep_info = *bl_params->ep_info;
|
|
||||||
|
|
||||||
if (bl_params->image_id == BL33_IMAGE_ID)
|
|
||||||
bl33_image_ep_info = *bl_params->ep_info;
|
|
||||||
|
|
||||||
bl_params = bl_params->next_params_info;
|
|
||||||
}
|
|
||||||
|
|
||||||
if (bl33_image_ep_info.pc == 0)
|
|
||||||
panic();
|
|
||||||
|
|
||||||
#else /* LOAD_IMAGE_V2 */
|
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Check params passed from BL2 should not be NULL,
|
* Check params passed from BL2 should not be NULL,
|
||||||
*/
|
*/
|
||||||
|
bl_params_t *params_from_bl2 = (bl_params_t *)from_bl2;
|
||||||
|
|
||||||
assert(params_from_bl2 != NULL);
|
assert(params_from_bl2 != NULL);
|
||||||
assert(params_from_bl2->h.type == PARAM_BL31);
|
assert(params_from_bl2->h.type == PARAM_BL_PARAMS);
|
||||||
assert(params_from_bl2->h.version >= VERSION_1);
|
assert(params_from_bl2->h.version >= VERSION_2);
|
||||||
|
|
||||||
|
bl_params_node_t *bl_params = params_from_bl2->head;
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Copy BL32 (if populated by BL2) and BL33 entry point information.
|
* Copy BL33 and BL32 (if present), entry point information.
|
||||||
* They are stored in Secure RAM, in BL2's address space.
|
* They are stored in Secure RAM, in BL2's address space.
|
||||||
*/
|
*/
|
||||||
if (from_bl2->bl32_ep_info)
|
while (bl_params) {
|
||||||
bl32_image_ep_info = *from_bl2->bl32_ep_info;
|
if (bl_params->image_id == BL32_IMAGE_ID)
|
||||||
bl33_image_ep_info = *from_bl2->bl33_ep_info;
|
bl32_image_ep_info = *bl_params->ep_info;
|
||||||
#endif /* LOAD_IMAGE_V2 */
|
|
||||||
|
if (bl_params->image_id == BL33_IMAGE_ID)
|
||||||
|
bl33_image_ep_info = *bl_params->ep_info;
|
||||||
|
|
||||||
|
bl_params = bl_params->next_params_info;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (bl33_image_ep_info.pc == 0)
|
||||||
|
panic();
|
||||||
}
|
}
|
||||||
|
|
||||||
void bl31_platform_setup(void)
|
void bl31_platform_setup(void)
|
||||||
|
|
|
@ -88,13 +88,11 @@
|
||||||
#define BL32_DRAM_BASE 0x03000000
|
#define BL32_DRAM_BASE 0x03000000
|
||||||
#define BL32_DRAM_LIMIT 0x04000000
|
#define BL32_DRAM_LIMIT 0x04000000
|
||||||
|
|
||||||
#if LOAD_IMAGE_V2
|
|
||||||
#ifdef SPD_opteed
|
#ifdef SPD_opteed
|
||||||
/* Load pageable part of OP-TEE at end of allocated DRAM space for BL32 */
|
/* Load pageable part of OP-TEE at end of allocated DRAM space for BL32 */
|
||||||
#define POPLAR_OPTEE_PAGEABLE_LOAD_SIZE 0x400000 /* 4MB */
|
#define POPLAR_OPTEE_PAGEABLE_LOAD_SIZE 0x400000 /* 4MB */
|
||||||
#define POPLAR_OPTEE_PAGEABLE_LOAD_BASE (BL32_DRAM_LIMIT - POPLAR_OPTEE_PAGEABLE_LOAD_SIZE) /* 0x03C0_0000 */
|
#define POPLAR_OPTEE_PAGEABLE_LOAD_BASE (BL32_DRAM_LIMIT - POPLAR_OPTEE_PAGEABLE_LOAD_SIZE) /* 0x03C0_0000 */
|
||||||
#endif
|
#endif
|
||||||
#endif
|
|
||||||
|
|
||||||
#if (POPLAR_TSP_RAM_LOCATION_ID == POPLAR_DRAM_ID)
|
#if (POPLAR_TSP_RAM_LOCATION_ID == POPLAR_DRAM_ID)
|
||||||
#define TSP_SEC_MEM_BASE BL32_DRAM_BASE
|
#define TSP_SEC_MEM_BASE BL32_DRAM_BASE
|
||||||
|
@ -122,7 +120,8 @@
|
||||||
#define PLAT_POPLAR_NS_IMAGE_OFFSET 0x37000000
|
#define PLAT_POPLAR_NS_IMAGE_OFFSET 0x37000000
|
||||||
|
|
||||||
/* Page table and MMU setup constants */
|
/* Page table and MMU setup constants */
|
||||||
#define ADDR_SPACE_SIZE (1ULL << 32)
|
#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32)
|
||||||
|
#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32)
|
||||||
#define MAX_XLAT_TABLES (4)
|
#define MAX_XLAT_TABLES (4)
|
||||||
#define MAX_MMAP_REGIONS (16)
|
#define MAX_MMAP_REGIONS (16)
|
||||||
|
|
||||||
|
|
|
@ -5,7 +5,6 @@
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#include <arch_helpers.h>
|
#include <arch_helpers.h>
|
||||||
#include <arm_gic.h>
|
|
||||||
#include <assert.h>
|
#include <assert.h>
|
||||||
#include <bl_common.h>
|
#include <bl_common.h>
|
||||||
#include <console.h>
|
#include <console.h>
|
||||||
|
|
|
@ -4,9 +4,6 @@
|
||||||
# SPDX-License-Identifier: BSD-3-Clause
|
# SPDX-License-Identifier: BSD-3-Clause
|
||||||
#
|
#
|
||||||
|
|
||||||
# Enable version2 of image loading
|
|
||||||
LOAD_IMAGE_V2 := 1
|
|
||||||
|
|
||||||
# On Poplar, the TSP can execute from TZC secure area in DRAM.
|
# On Poplar, the TSP can execute from TZC secure area in DRAM.
|
||||||
POPLAR_TSP_RAM_LOCATION ?= dram
|
POPLAR_TSP_RAM_LOCATION ?= dram
|
||||||
ifeq (${POPLAR_TSP_RAM_LOCATION}, dram)
|
ifeq (${POPLAR_TSP_RAM_LOCATION}, dram)
|
||||||
|
@ -45,7 +42,6 @@ NEED_BL33 := yes
|
||||||
COLD_BOOT_SINGLE_CPU := 1
|
COLD_BOOT_SINGLE_CPU := 1
|
||||||
PROGRAMMABLE_RESET_ADDRESS := 1
|
PROGRAMMABLE_RESET_ADDRESS := 1
|
||||||
CTX_INCLUDE_FPREGS := 1
|
CTX_INCLUDE_FPREGS := 1
|
||||||
ENABLE_PLAT_COMPAT := 0
|
|
||||||
ERRATA_A53_855873 := 1
|
ERRATA_A53_855873 := 1
|
||||||
ERRATA_A53_835769 := 1
|
ERRATA_A53_835769 := 1
|
||||||
ERRATA_A53_843419 := 1
|
ERRATA_A53_843419 := 1
|
||||||
|
@ -53,9 +49,6 @@ ENABLE_SVE_FOR_NS := 0
|
||||||
|
|
||||||
WORKAROUND_CVE_2017_5715 := 0
|
WORKAROUND_CVE_2017_5715 := 0
|
||||||
|
|
||||||
ARM_GIC_ARCH := 2
|
|
||||||
$(eval $(call add_define,ARM_GIC_ARCH))
|
|
||||||
|
|
||||||
PLAT_PL061_MAX_GPIOS := 104
|
PLAT_PL061_MAX_GPIOS := 104
|
||||||
$(eval $(call add_define,PLAT_PL061_MAX_GPIOS))
|
$(eval $(call add_define,PLAT_PL061_MAX_GPIOS))
|
||||||
|
|
||||||
|
@ -67,12 +60,13 @@ PLAT_INCLUDES := -Iplat/hisilicon/poplar/include \
|
||||||
-Iinclude/drivers/io
|
-Iinclude/drivers/io
|
||||||
|
|
||||||
PLAT_BL_COMMON_SOURCES := \
|
PLAT_BL_COMMON_SOURCES := \
|
||||||
lib/aarch64/xlat_tables.c \
|
lib/xlat_tables/aarch64/xlat_tables.c \
|
||||||
|
lib/xlat_tables/xlat_tables_common.c \
|
||||||
drivers/delay_timer/generic_delay_timer.c \
|
drivers/delay_timer/generic_delay_timer.c \
|
||||||
drivers/arm/gic/common/gic_common.c \
|
drivers/arm/gic/common/gic_common.c \
|
||||||
drivers/arm/gic/v2/gicv2_helpers.c \
|
drivers/arm/gic/v2/gicv2_helpers.c \
|
||||||
drivers/delay_timer/delay_timer.c \
|
drivers/delay_timer/delay_timer.c \
|
||||||
drivers/arm/pl011/pl011_console.S \
|
drivers/arm/pl011/aarch64/pl011_console.S \
|
||||||
drivers/arm/gic/v2/gicv2_main.c \
|
drivers/arm/gic/v2/gicv2_main.c \
|
||||||
plat/arm/common/aarch64/arm_helpers.S \
|
plat/arm/common/aarch64/arm_helpers.S \
|
||||||
plat/arm/common/arm_gicv2.c \
|
plat/arm/common/arm_gicv2.c \
|
||||||
|
@ -104,7 +98,6 @@ BL2_SOURCES += \
|
||||||
plat/hisilicon/poplar/bl2_plat_setup.c \
|
plat/hisilicon/poplar/bl2_plat_setup.c \
|
||||||
plat/hisilicon/poplar/plat_storage.c
|
plat/hisilicon/poplar/plat_storage.c
|
||||||
|
|
||||||
ifeq (${LOAD_IMAGE_V2},1)
|
|
||||||
BL2_SOURCES += \
|
BL2_SOURCES += \
|
||||||
plat/hisilicon/poplar/bl2_plat_mem_params_desc.c \
|
plat/hisilicon/poplar/bl2_plat_mem_params_desc.c \
|
||||||
plat/hisilicon/poplar/poplar_image_load.c \
|
plat/hisilicon/poplar/poplar_image_load.c \
|
||||||
|
@ -114,12 +107,11 @@ ifeq (${SPD},opteed)
|
||||||
BL2_SOURCES += \
|
BL2_SOURCES += \
|
||||||
lib/optee/optee_utils.c
|
lib/optee/optee_utils.c
|
||||||
endif
|
endif
|
||||||
endif
|
|
||||||
|
|
||||||
BL31_SOURCES += \
|
BL31_SOURCES += \
|
||||||
lib/cpus/aarch64/aem_generic.S \
|
lib/cpus/aarch64/aem_generic.S \
|
||||||
lib/cpus/aarch64/cortex_a53.S \
|
lib/cpus/aarch64/cortex_a53.S \
|
||||||
plat/common/aarch64/plat_psci_common.c \
|
plat/common/plat_psci_common.c \
|
||||||
plat/hisilicon/poplar/bl31_plat_setup.c \
|
plat/hisilicon/poplar/bl31_plat_setup.c \
|
||||||
plat/hisilicon/poplar/plat_topology.c \
|
plat/hisilicon/poplar/plat_topology.c \
|
||||||
plat/hisilicon/poplar/plat_pm.c
|
plat/hisilicon/poplar/plat_pm.c
|
||||||
|
|
Loading…
Reference in New Issue