Tegra186: disable PROGRAMMABLE_RESET_ADDRESS
This patch disables the code to program reset vector for secondary CPUs to a different entry point, than cold boot. The cold boot entry point has the ability to differentiate between a cold boot and a warm boot, that is controlled by the PROGRAMMABLE_RESET_ADDRESS macro. By reusing the same entry point, we can lock the CPU reset vector during cold boot. Change-Id: Iad400841d57c139469e1d29b5d467197e11958c4 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
This commit is contained in:
Varun Wadekar
parent
35aa1c1e51
commit
8336c94dc4
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@ -11,6 +11,5 @@ void tegra186_cpu_reset_handler(void);
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uint64_t tegra186_get_cpu_reset_handler_base(void);
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uint64_t tegra186_get_cpu_reset_handler_size(void);
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uint64_t tegra186_get_mc_ctx_offset(void);
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void tegra186_set_system_suspend_entry(void);
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#endif /* TEGRA186_PRIVATE_H */
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@ -158,9 +158,6 @@ int32_t tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state)
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(void)mce_command_handler((uint64_t)MCE_CMD_ENTER_CSTATE,
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(uint64_t)TEGRA_ARI_CORE_C7, MCE_CORE_SLEEP_TIME_INFINITE, 0U);
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/* set system suspend state for house-keeping */
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tegra186_set_system_suspend_entry();
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} else {
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; /* do nothing */
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}
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@ -1,5 +1,6 @@
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/*
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* Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -15,9 +16,6 @@
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#include <tegra_def.h>
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#include <tegra_private.h>
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#define MISCREG_AA64_RST_LOW 0x2004U
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#define MISCREG_AA64_RST_HIGH 0x2008U
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#define SCRATCH_SECURE_RSV1_SCRATCH_0 0x658U
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#define SCRATCH_SECURE_RSV1_SCRATCH_1 0x65CU
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@ -51,16 +49,9 @@ void plat_secondary_setup(void)
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addr_low = (uint32_t)params_from_bl2->tzdram_base | CPU_RESET_MODE_AA64;
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addr_high = (uint32_t)((params_from_bl2->tzdram_base >> 32U) & 0x7ffU);
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/* write lower 32 bits first, then the upper 11 bits */
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mmio_write_32(TEGRA_MISC_BASE + MISCREG_AA64_RST_LOW, addr_low);
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mmio_write_32(TEGRA_MISC_BASE + MISCREG_AA64_RST_HIGH, addr_high);
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/* save reset vector to be used during SYSTEM_SUSPEND exit */
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mmio_write_32(TEGRA_SCRATCH_BASE + SCRATCH_RESET_VECTOR_LO,
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addr_low);
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mmio_write_32(TEGRA_SCRATCH_BASE + SCRATCH_RESET_VECTOR_HI,
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addr_high);
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/* update reset vector address to the CCPLEX */
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(void)mce_update_reset_vector();
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}
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@ -12,31 +12,12 @@
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#include <plat/common/common_def.h>
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#include <tegra_def.h>
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#define TEGRA186_STATE_SYSTEM_SUSPEND 0x5C7
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#define TEGRA186_STATE_SYSTEM_RESUME 0x600D
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#define TEGRA186_MC_CTX_SIZE 0x93
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.globl tegra186_cpu_reset_handler
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/* CPU reset handler routine */
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func tegra186_cpu_reset_handler _align=4
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/* check if we are exiting system suspend state */
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adr x0, __tegra186_system_suspend_state
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ldr x1, [x0]
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mov x2, #TEGRA186_STATE_SYSTEM_SUSPEND
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lsl x2, x2, #16
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add x2, x2, #TEGRA186_STATE_SYSTEM_SUSPEND
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cmp x1, x2
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bne boot_cpu
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/* set system resume state */
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mov x1, #TEGRA186_STATE_SYSTEM_RESUME
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lsl x1, x1, #16
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mov x2, #TEGRA186_STATE_SYSTEM_RESUME
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add x1, x1, x2
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str x1, [x0]
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dsb sy
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/* prepare to relocate to TZSRAM */
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mov x0, #BL31_BASE
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adr x1, __tegra186_cpu_reset_handler_end
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@ -101,7 +82,6 @@ __tegra186_cpu_reset_handler_end:
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.globl tegra186_get_cpu_reset_handler_size
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.globl tegra186_get_cpu_reset_handler_base
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.globl tegra186_get_mc_ctx_offset
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.globl tegra186_set_system_suspend_entry
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/* return size of the CPU reset handler */
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func tegra186_get_cpu_reset_handler_size
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@ -124,23 +104,3 @@ func tegra186_get_mc_ctx_offset
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sub x0, x0, x1
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ret
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endfunc tegra186_get_mc_ctx_offset
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/* set system suspend state before SC7 entry */
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func tegra186_set_system_suspend_entry
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mov x0, #TEGRA_MC_BASE
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mov x3, #MC_SECURITY_CFG3_0
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ldr w1, [x0, x3]
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lsl x1, x1, #32
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mov x3, #MC_SECURITY_CFG0_0
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ldr w2, [x0, x3]
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orr x3, x1, x2 /* TZDRAM base */
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adr x0, __tegra186_system_suspend_state
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adr x1, tegra186_cpu_reset_handler
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sub x2, x0, x1 /* offset in TZDRAM */
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mov x0, #TEGRA186_STATE_SYSTEM_SUSPEND
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lsl x0, x0, #16
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add x0, x0, #TEGRA186_STATE_SYSTEM_SUSPEND
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str x0, [x3, x2] /* set value in TZDRAM */
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dsb sy
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ret
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endfunc tegra186_set_system_suspend_entry
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@ -14,7 +14,7 @@ $(eval $(call add_define,ENABLE_CHIP_VERIFICATION_HARNESS))
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RESET_TO_BL31 := 1
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PROGRAMMABLE_RESET_ADDRESS := 1
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PROGRAMMABLE_RESET_ADDRESS := 0
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COLD_BOOT_SINGLE_CPU := 1
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