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style(plat/arm/corstone1000): resolve checkpatch warnings 

Change-Id: Ic8cb9b0834806675c792018e809d7ba77fbe856f
Signed-off-by: David Vincze <david.vincze@arm.com>
This commit is contained in:
David Vincze 2022-03-03 14:35:51 +01:00
parent f78cb61a11
commit 83b3ed260b
5 changed files with 204 additions and 245 deletions
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4
plat/arm/board/corstone1000/common/corstone1000_bl2_mem_params_desc.c
View File

@ -57,8 +57,8 @@ static bl_mem_params_node_t bl2_mem_params_descs[] = {
{
.image_id = TOS_FW_CONFIG_ID,
.image_info.image_base = CORSTONE1000_TOS_FW_CONFIG_BASE,
.image_info.image_max_size = CORSTONE1000_TOS_FW_CONFIG_LIMIT - \
CORSTONE1000_TOS_FW_CONFIG_BASE,
.image_info.image_max_size = (CORSTONE1000_TOS_FW_CONFIG_LIMIT -
CORSTONE1000_TOS_FW_CONFIG_BASE),
SET_STATIC_PARAM_HEAD(ep_info, PARAM_IMAGE_BINARY,
VERSION_2, entry_point_info_t, SECURE | NON_EXECUTABLE),
SET_STATIC_PARAM_HEAD(image_info, PARAM_IMAGE_BINARY,

5
plat/arm/board/corstone1000/common/corstone1000_plat.c
View File

@ -36,10 +36,11 @@ static void set_fip_image_source(void)
/*
* metadata for firmware update is written at 0x0000 offset of the flash.
* PLAT_ARM_BOOT_BANK_FLAG contains the boot bank that TF-M is booted.
* As per firmware update spec, at a given point of time, only one bank is active.
* This means, TF-A should boot from the same bank as TF-M.
* As per firmware update spec, at a given point of time, only one bank
* is active. This means, TF-A should boot from the same bank as TF-M.
*/
volatile uint32_t *boot_bank_flag = (uint32_t *)(PLAT_ARM_BOOT_BANK_FLAG);
if (*boot_bank_flag > 1) {
VERBOSE("Boot_bank is set higher than possible values");
}

102
plat/arm/board/corstone1000/common/include/platform_def.h
View File

@ -60,77 +60,45 @@
/* SRAM (CVM) memory layout
*
* <ARM_TRUSTED_SRAM_BASE>
*
* partition size: sizeof(meminfo_t) = 16 bytes
*
* content: memory info area used by the next BL
*
* <ARM_FW_CONFIG_BASE>
*
* partition size: 4080 bytes
*
* <ARM_BL2_MEM_DESC_BASE>
*
* partition size: 4 KB
*
* content:
*
* Area where BL2 copies the images descriptors
* content: Area where BL2 copies the images descriptors
*
* <ARM_BL_RAM_BASE> = <BL32_BASE>
*
* partition size: 688 KB
*
* content:
*
* BL32 (optee-os)
* content: BL32 (optee-os)
*
* <CORSTONE1000_TOS_FW_CONFIG_BASE> = 0x20ae000
*
* partition size: 8 KB
*
* content:
*
* BL32 config (TOS_FW_CONFIG)
* content: BL32 config (TOS_FW_CONFIG)
*
* <BL31_BASE>
*
* partition size: 140 KB
*
* content:
*
* BL31
* content: BL31
*
* <BL2_SIGNATURE_BASE>
*
* partition size: 4 KB
*
* content:
*
* MCUBOOT data needed to verify TF-A BL2
* content: MCUBOOT data needed to verify TF-A BL2
*
* <BL2_BASE>
*
* partition size: 176 KB
*
* content:
*
* BL2
* content: BL2
*
* <ARM_NS_SHARED_RAM_BASE> = <ARM_TRUSTED_SRAM_BASE> + 1 MB
*
* partition size: 512 KB
*
* content:
*
* BL33 (u-boot)
* content: BL33 (u-boot)
*/
/* DDR memory */
#define ARM_DRAM1_BASE UL(0x80000000)
#define ARM_DRAM1_SIZE (SZ_2G) /* 2GB*/
#define ARM_DRAM1_END (ARM_DRAM1_BASE + \
ARM_DRAM1_SIZE - 1)
#define ARM_DRAM1_END (ARM_DRAM1_BASE + ARM_DRAM1_SIZE - 1)
/* DRAM1 and DRAM2 are the same for corstone1000 */
#define ARM_DRAM2_BASE ARM_DRAM1_BASE
@ -139,8 +107,7 @@
#define ARM_NS_DRAM1_BASE ARM_DRAM1_BASE
#define ARM_NS_DRAM1_SIZE ARM_DRAM1_SIZE
#define ARM_NS_DRAM1_END (ARM_NS_DRAM1_BASE +\
ARM_NS_DRAM1_SIZE - 1)
#define ARM_NS_DRAM1_END (ARM_NS_DRAM1_BASE + ARM_NS_DRAM1_SIZE - 1)
/* The first 8 KB of Trusted SRAM are used as shared memory */
#define ARM_TRUSTED_SRAM_BASE UL(0x02000000)
@ -150,8 +117,7 @@
/* The remaining Trusted SRAM is used to load the BL images */
#define TOTAL_SRAM_SIZE (SZ_4M) /* 4 MB */
/* Last 512KB of CVM is allocated for shared RAM
* as an example openAMP */
/* Last 512KB of CVM is allocated for shared RAM as an example openAMP */
#define ARM_NS_SHARED_RAM_SIZE (512 * SZ_1K)
#define PLAT_ARM_TRUSTED_SRAM_SIZE (TOTAL_SRAM_SIZE - \
@ -162,23 +128,19 @@
#define PLAT_ARM_MAX_BL31_SIZE (140 * SZ_1K) /* 140 KB */
#define ARM_BL_RAM_BASE (ARM_SHARED_RAM_BASE + \
ARM_SHARED_RAM_SIZE)
#define ARM_BL_RAM_BASE (ARM_SHARED_RAM_BASE + ARM_SHARED_RAM_SIZE)
#define ARM_BL_RAM_SIZE (PLAT_ARM_TRUSTED_SRAM_SIZE - \
ARM_SHARED_RAM_SIZE)
#define BL2_SIGNATURE_SIZE (SZ_4K) /* 4 KB */
#define BL2_SIGNATURE_BASE (BL2_LIMIT - \
PLAT_ARM_MAX_BL2_SIZE)
#define BL2_SIGNATURE_BASE (BL2_LIMIT - PLAT_ARM_MAX_BL2_SIZE)
#define BL2_BASE (BL2_LIMIT - \
PLAT_ARM_MAX_BL2_SIZE + \
BL2_SIGNATURE_SIZE)
#define BL2_LIMIT (ARM_BL_RAM_BASE + \
ARM_BL_RAM_SIZE)
#define BL2_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE)
#define BL31_BASE (BL2_SIGNATURE_BASE - \
PLAT_ARM_MAX_BL31_SIZE)
#define BL31_BASE (BL2_SIGNATURE_BASE - PLAT_ARM_MAX_BL31_SIZE)
#define BL31_LIMIT BL2_SIGNATURE_BASE
#define CORSTONE1000_TOS_FW_CONFIG_BASE (BL31_BASE - \
@ -187,11 +149,9 @@
#define CORSTONE1000_TOS_FW_CONFIG_LIMIT BL31_BASE
#define BL32_BASE ARM_BL_RAM_BASE
#define PLAT_ARM_MAX_BL32_SIZE (CORSTONE1000_TOS_FW_CONFIG_BASE - \
BL32_BASE)
#define PLAT_ARM_MAX_BL32_SIZE (CORSTONE1000_TOS_FW_CONFIG_BASE - BL32_BASE)
#define BL32_LIMIT (BL32_BASE + \
PLAT_ARM_MAX_BL32_SIZE)
#define BL32_LIMIT (BL32_BASE + PLAT_ARM_MAX_BL32_SIZE)
/* SPD_spmd settings */
@ -237,10 +197,9 @@
* FW_CONFIG is intended to host the device tree. Currently, This area is not
* used because corstone1000 platform doesn't use a device tree at TF-A level.
*/
#define ARM_FW_CONFIG_BASE (ARM_SHARED_RAM_BASE \
+ sizeof(meminfo_t))
#define ARM_FW_CONFIG_LIMIT (ARM_SHARED_RAM_BASE \
+ (ARM_SHARED_RAM_SIZE >> 1))
#define ARM_FW_CONFIG_BASE (ARM_SHARED_RAM_BASE + sizeof(meminfo_t))
#define ARM_FW_CONFIG_LIMIT (ARM_SHARED_RAM_BASE + \
(ARM_SHARED_RAM_SIZE >> 1))
/*
* Boot parameters passed from BL2 to BL31/BL32 are stored here
@ -255,8 +214,7 @@
#define ARM_BL_REGIONS 3
#define PLAT_ARM_MMAP_ENTRIES 8
#define MAX_XLAT_TABLES 5
#define MAX_MMAP_REGIONS (PLAT_ARM_MMAP_ENTRIES + \
ARM_BL_REGIONS)
#define MAX_MMAP_REGIONS (PLAT_ARM_MMAP_ENTRIES + ARM_BL_REGIONS)
#define MAX_IO_DEVICES 2
#define MAX_IO_HANDLES 3
#define MAX_IO_BLOCK_DEVICES 1
@ -350,19 +308,17 @@
#define ARM_MAP_BL_RO MAP_REGION_FLAT( \
BL_CODE_BASE, \
BL_CODE_END \
- BL_CODE_BASE, \
(BL_CODE_END - BL_CODE_BASE), \
MT_CODE | MT_SECURE), \
MAP_REGION_FLAT( \
BL_RO_DATA_BASE, \
BL_RO_DATA_END \
- BL_RO_DATA_BASE, \
(BL_RO_DATA_END - BL_RO_DATA_BASE), \
MT_RO_DATA | MT_SECURE)
#if USE_COHERENT_MEM
#define ARM_MAP_BL_COHERENT_RAM MAP_REGION_FLAT( \
BL_COHERENT_RAM_BASE, \
BL_COHERENT_RAM_END \
- BL_COHERENT_RAM_BASE, \
(BL_COHERENT_RAM_END \
- BL_COHERENT_RAM_BASE), \
MT_DEVICE | MT_RW | MT_SECURE)
#endif
@ -372,8 +328,8 @@
*/
#define ARM_MAP_BL_CONFIG_REGION MAP_REGION_FLAT( \
ARM_FW_CONFIG_BASE, \
(ARM_FW_CONFIG_LIMIT- \
ARM_FW_CONFIG_BASE), \
(ARM_FW_CONFIG_LIMIT \
- ARM_FW_CONFIG_BASE), \
MT_MEMORY | MT_RW | MT_SECURE)
#define CORSTONE1000_DEVICE_BASE (0x1A000000)
@ -426,10 +382,12 @@
*/
#define PLAT_ARM_G1S_IRQ_PROPS(grp) \
ARM_G1S_IRQ_PROPS(grp), \
INTR_PROP_DESC(CORSTONE1000_IRQ_TZ_WDOG, GIC_HIGHEST_SEC_PRIORITY, \
INTR_PROP_DESC(CORSTONE1000_IRQ_TZ_WDOG, \
GIC_HIGHEST_SEC_PRIORITY, \
(grp), GIC_INTR_CFG_LEVEL), \
INTR_PROP_DESC(CORSTONE1000_IRQ_SEC_SYS_TIMER, \
GIC_HIGHEST_SEC_PRIORITY, (grp), GIC_INTR_CFG_LEVEL)
GIC_HIGHEST_SEC_PRIORITY, \
(grp), GIC_INTR_CFG_LEVEL)
#define PLAT_ARM_G0_IRQ_PROPS(grp) ARM_G0_IRQ_PROPS(grp)