Merge pull request #1187 from antonio-nino-diaz-arm/an/spm-xlat-dram
SPM: Move S-EL1/S-EL0 xlat tables to TZC DRAM
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83df7ce38d
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@ -168,21 +168,28 @@ typedef struct xlat_ctx xlat_ctx_t;
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_xlat_tables_count, \
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_virt_addr_space_size, \
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_phy_addr_space_size, \
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IMAGE_XLAT_DEFAULT_REGIME)
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IMAGE_XLAT_DEFAULT_REGIME, \
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"xlat_table")
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/*
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* Same as REGISTER_XLAT_CONTEXT plus the additional parameter _xlat_regime to
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* specify the translation regime managed by this xlat_ctx_t instance. The
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* values are the one from xlat_regime_t enumeration.
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* Same as REGISTER_XLAT_CONTEXT plus the additional parameters:
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*
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* _xlat_regime:
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* Specify the translation regime managed by this xlat_ctx_t instance. The
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* values are the one from xlat_regime_t enumeration.
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*
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* _section_name:
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* Specify the name of the section where the translation tables have to be
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* placed by the linker.
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*/
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#define REGISTER_XLAT_CONTEXT2(_ctx_name, _mmap_count, _xlat_tables_count, \
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_virt_addr_space_size, _phy_addr_space_size, \
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_xlat_regime) \
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_xlat_regime, _section_name) \
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_REGISTER_XLAT_CONTEXT_FULL_SPEC(_ctx_name, _mmap_count, \
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_xlat_tables_count, \
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_virt_addr_space_size, \
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_phy_addr_space_size, \
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_xlat_regime)
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_xlat_regime, _section_name)
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/******************************************************************************
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* Generic translation table APIs.
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@ -123,7 +123,7 @@ struct xlat_ctx {
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#define _REGISTER_XLAT_CONTEXT_FULL_SPEC(_ctx_name, _mmap_count, _xlat_tables_count, \
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_virt_addr_space_size, _phy_addr_space_size, \
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_xlat_regime) \
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_xlat_regime, _section_name) \
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CASSERT(CHECK_VIRT_ADDR_SPACE_SIZE(_virt_addr_space_size), \
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assert_invalid_virtual_addr_space_size_for_##_ctx_name); \
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\
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@ -134,7 +134,7 @@ struct xlat_ctx {
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\
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static uint64_t _ctx_name##_xlat_tables[_xlat_tables_count] \
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[XLAT_TABLE_ENTRIES] \
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__aligned(XLAT_TABLE_SIZE) __section("xlat_table"); \
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__aligned(XLAT_TABLE_SIZE) __section(_section_name); \
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\
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static uint64_t _ctx_name##_base_xlat_table \
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[GET_NUM_BASE_LEVEL_ENTRIES(_virt_addr_space_size)] \
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@ -90,11 +90,7 @@
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* PLAT_ARM_MAX_BL31_SIZE is calculated using the current BL31 debug size plus a
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* little space for growth.
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*/
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#if ENABLE_SPM
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#define PLAT_ARM_MAX_BL31_SIZE 0x28000
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#else
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#define PLAT_ARM_MAX_BL31_SIZE 0x1D000
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#endif
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#ifdef AARCH32
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/*
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@ -98,6 +98,12 @@
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/* Total number of memory regions with distinct properties */
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#define ARM_SP_IMAGE_NUM_MEM_REGIONS 6
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/*
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* Name of the section to put the translation tables used by the S-EL1/S-EL0
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* context of a Secure Partition.
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*/
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#define PLAT_SP_IMAGE_XLAT_SECTION_NAME "arm_el3_tzc_dram"
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/* Cookies passed to the Secure Partition at boot. Not used by ARM platforms. */
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#define PLAT_SPM_COOKIE_0 ULL(0)
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#define PLAT_SPM_COOKIE_1 ULL(0)
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@ -21,12 +21,17 @@
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#include "spm_private.h"
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#include "spm_shim_private.h"
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/* Place translation tables by default along with the ones used by BL31. */
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#ifndef PLAT_SP_IMAGE_XLAT_SECTION_NAME
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#define PLAT_SP_IMAGE_XLAT_SECTION_NAME "xlat_table"
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#endif
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/* Allocate and initialise the translation context for the secure partition. */
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REGISTER_XLAT_CONTEXT2(secure_partition,
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PLAT_SP_IMAGE_MMAP_REGIONS,
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PLAT_SP_IMAGE_MAX_XLAT_TABLES,
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PLAT_VIRT_ADDR_SPACE_SIZE, PLAT_PHY_ADDR_SPACE_SIZE,
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EL1_EL0_REGIME);
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EL1_EL0_REGIME, PLAT_SP_IMAGE_XLAT_SECTION_NAME);
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/* Export a handle on the secure partition translation context */
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xlat_ctx_t *secure_partition_xlat_ctx_handle = &secure_partition_xlat_ctx;
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