Workaround for Hercules erratum 1688305
Erratum 1688305 is a Cat B erratum present in r0p0, r0p1 versions of Hercules core. The erratum can be avoided by setting bit 1 of the implementation defined register CPUACTLR2_EL1 to 1 to prevent store- release from being dispatched before it is the oldest. Change-Id: I2ac04f5d9423868b6cdd4ceb3d0ffa46e570efed Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
This commit is contained in:
Madhukar Pappireddy
parent
86ed8953b5
commit
83e955241a
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@ -227,6 +227,12 @@ For Cortex-A76, the following errata build flags are defined :
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- ``ERRATA_A76_1275112``: This applies errata 1275112 workaround to Cortex-A76
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CPU. This needs to be enabled only for revision <= r3p0 of the CPU.
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For Hercules, the following errata build flags are defined :
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- ``ERRATA_HERCULES_1688305``: This applies errata 1688305 workaround to
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Hercules CPU. This needs to be enabled only for revision r0p0 - r1p0 of
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the CPU.
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For Neoverse N1, the following errata build flags are defined :
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- ``ERRATA_N1_1073348``: This applies errata 1073348 workaround to Neoverse-N1
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@ -27,6 +27,9 @@
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******************************************************************************/
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#define CORTEX_HERCULES_ACTLR_TAM_BIT (ULL(1) << 30)
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#define CORTEX_HERCULES_ACTLR2_EL1 S3_0_C15_C1_1
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#define CORTEX_HERCULES_ACTLR2_EL1_BIT_1 (ULL(1) << 1)
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/*******************************************************************************
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* CPU Activity Monitor Unit register specific definitions.
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******************************************************************************/
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@ -16,12 +16,49 @@
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#error "cortex_hercules must be compiled with HW_ASSISTED_COHERENCY enabled"
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#endif
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/* --------------------------------------------------
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* Errata Workaround for Hercules Erratum 1688305.
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* This applies to revision r0p0 and r1p0 of Hercules.
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* Inputs:
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* x0: variant[4:7] and revision[0:3] of current cpu.
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* Shall clobber: x0-x17
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* --------------------------------------------------
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*/
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func errata_hercules_1688305_wa
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/* Compare x0 against revision r1p0 */
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mov x17, x30
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bl check_errata_1688305
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cbz x0, 1f
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mrs x1, CORTEX_HERCULES_ACTLR2_EL1
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orr x1, x1, CORTEX_HERCULES_ACTLR2_EL1_BIT_1
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msr CORTEX_HERCULES_ACTLR2_EL1, x1
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isb
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1:
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ret x17
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endfunc errata_hercules_1688305_wa
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func check_errata_1688305
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/* Applies to r0p0 and r1p0 */
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mov x1, #0x10
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b cpu_rev_var_ls
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endfunc check_errata_1688305
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/* -------------------------------------------------
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* The CPU Ops reset function for Cortex-Hercules
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* -------------------------------------------------
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*/
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#if ENABLE_AMU
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func cortex_hercules_reset_func
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mov x19, x30
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bl cpu_get_rev_var
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mov x18, x0
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#if ERRATA_HERCULES_1688305
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mov x0, x18
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bl errata_hercules_1688305_wa
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#endif
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#if ENABLE_AMU
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/* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */
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mrs x0, actlr_el3
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bic x0, x0, #CORTEX_HERCULES_ACTLR_TAM_BIT
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@ -39,12 +76,12 @@ func cortex_hercules_reset_func
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/* Enable group1 counters */
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mov x0, #CORTEX_HERCULES_AMU_GROUP1_MASK
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msr CPUAMCNTENSET1_EL0, x0
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isb
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ret
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endfunc cortex_hercules_reset_func
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#endif
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isb
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ret x19
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endfunc cortex_hercules_reset_func
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/* ---------------------------------------------
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* HW will do the cache maintenance while powering down
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* ---------------------------------------------
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@ -66,6 +103,18 @@ endfunc cortex_hercules_core_pwr_dwn
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*/
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#if REPORT_ERRATA
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func cortex_hercules_errata_report
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stp x8, x30, [sp, #-16]!
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bl cpu_get_rev_var
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mov x8, x0
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/*
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* Report all errata. The revision-variant information is passed to
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* checking functions of each errata.
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*/
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report_errata ERRATA_HERCULES_1688305, cortex_hercules, 1688305
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ldp x8, x30, [sp], #16
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ret
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endfunc cortex_hercules_errata_report
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#endif
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@ -89,12 +138,6 @@ func cortex_hercules_cpu_reg_dump
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ret
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endfunc cortex_hercules_cpu_reg_dump
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#if ENABLE_AMU
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#define HERCULES_RESET_FUNC cortex_hercules_reset_func
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#else
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#define HERCULES_RESET_FUNC CPU_NO_RESET_FUNC
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#endif
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declare_cpu_ops cortex_hercules, CORTEX_HERCULES_MIDR, \
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HERCULES_RESET_FUNC, \
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cortex_hercules_reset_func, \
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cortex_hercules_core_pwr_dwn
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@ -234,6 +234,10 @@ ERRATA_A76_1275112 ?=0
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# only to revision <= r3p0 of the Cortex A76 cpu.
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ERRATA_A76_1286807 ?=0
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# Flag to apply erratum 1688305 workaround during reset. This erratum applies
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# to revisions r0p0 - r1p0 of the Hercules cpu.
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ERRATA_HERCULES_1688305 ?=0
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# Flag to apply T32 CLREX workaround during reset. This erratum applies
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# only to r0p0 and r1p0 of the Neoverse N1 cpu.
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ERRATA_N1_1043202 ?=1
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@ -467,6 +471,10 @@ $(eval $(call add_define,ERRATA_A76_1275112))
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$(eval $(call assert_boolean,ERRATA_A76_1286807))
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$(eval $(call add_define,ERRATA_A76_1286807))
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# Process ERRATA_HERCULES_1688305 flag
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$(eval $(call assert_boolean,ERRATA_HERCULES_1688305))
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$(eval $(call add_define,ERRATA_HERCULES_1688305))
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# Process ERRATA_N1_1043202 flag
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$(eval $(call assert_boolean,ERRATA_N1_1043202))
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$(eval $(call add_define,ERRATA_N1_1043202))
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