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Tegra: fix offset used to dump GICD registers from crash handler 

The GICD registers are 32-bits wide whereas the crash handler was reading
them as 64-bit ones. This patch fixes the code to read the GICD registers,
32-bits at a time, from the paltform's crash handler.

Change-Id: If3d6608529684ecc02be6a1b715012310813b2a4
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
This commit is contained in:
Varun Wadekar 2018-01-02 14:10:18 -08:00
parent 0887026ec1
commit 8510376c26
1 changed files with 2 additions and 2 deletions
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4
plat/nvidia/tegra/include/plat_macros.S
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -50,7 +50,7 @@ spacer:
bl asm_print_hex
adr x4, spacer
bl asm_print_str
ldr x4, [x7], #8
ldr w4, [x7], #4
bl asm_print_hex
adr x4, newline
bl asm_print_str