Tegra: fix offset used to dump GICD registers from crash handler
The GICD registers are 32-bits wide whereas the crash handler was reading them as 64-bit ones. This patch fixes the code to read the GICD registers, 32-bits at a time, from the paltform's crash handler. Change-Id: If3d6608529684ecc02be6a1b715012310813b2a4 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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@ -1,5 +1,5 @@
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/*
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/*
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* Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
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*
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*
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* SPDX-License-Identifier: BSD-3-Clause
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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*/
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@ -50,7 +50,7 @@ spacer:
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bl asm_print_hex
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bl asm_print_hex
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adr x4, spacer
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adr x4, spacer
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bl asm_print_str
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bl asm_print_str
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ldr x4, [x7], #8
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ldr w4, [x7], #4
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bl asm_print_hex
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bl asm_print_hex
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adr x4, newline
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adr x4, newline
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bl asm_print_str
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bl asm_print_str
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