Merge "Add compile-time errors for HW_ASSISTED_COHERENCY flag" into integration
This commit is contained in:
Soby Mathew
TrustedFirmware Code Review
commit
854ca7daf9
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@ -534,13 +534,21 @@ Common build options
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- ``HW_ASSISTED_COHERENCY``: On most Arm systems to-date, platform-specific
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software operations are required for CPUs to enter and exit coherency.
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However, there exists newer systems where CPUs' entry to and exit from
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coherency is managed in hardware. Such systems require software to only
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initiate the operations, and the rest is managed in hardware, minimizing
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active software management. In such systems, this boolean option enables
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TF-A to carry out build and run-time optimizations during boot and power
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management operations. This option defaults to 0 and if it is enabled,
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then it implies ``WARMBOOT_ENABLE_DCACHE_EARLY`` is also enabled.
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However, newer systems exist where CPUs' entry to and exit from coherency
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is managed in hardware. Such systems require software to only initiate these
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operations, and the rest is managed in hardware, minimizing active software
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management. In such systems, this boolean option enables TF-A to carry out
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build and run-time optimizations during boot and power management operations.
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This option defaults to 0 and if it is enabled, then it implies
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``WARMBOOT_ENABLE_DCACHE_EARLY`` is also enabled.
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If this flag is disabled while the platform which TF-A is compiled for
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includes cores that manage coherency in hardware, then a compilation error is
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generated. This is based on the fact that a system cannot have, at the same
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time, cores that manage coherency in hardware and cores that don't. In other
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words, a platform cannot have, at the same time, cores that require
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``HW_ASSISTED_COHERENCY=1`` and cores that require
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``HW_ASSISTED_COHERENCY=0``.
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Note that, when ``HW_ASSISTED_COHERENCY`` is enabled, version 2 of
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translation library (xlat tables v2) must be used; version 1 of translation
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@ -11,6 +11,11 @@
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#include <cpu_macros.S>
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#include <plat_macros.S>
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/* Hardware handled coherency */
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#if HW_ASSISTED_COHERENCY == 0
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#error "Cortex-A55 must be compiled with HW_ASSISTED_COHERENCY enabled"
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#endif
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/* --------------------------------------------------
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* Errata Workaround for Cortex A55 Errata #768277.
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* This applies only to revision r0p0 of Cortex A55.
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@ -10,6 +10,11 @@
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#include <cpuamu.h>
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#include <cpu_macros.S>
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/* Hardware handled coherency */
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#if HW_ASSISTED_COHERENCY == 0
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#error "Cortex-A75 must be compiled with HW_ASSISTED_COHERENCY enabled"
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#endif
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/* --------------------------------------------------
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* Errata Workaround for Cortex A75 Errata #764081.
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* This applies only to revision r0p0 of Cortex A75.
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@ -13,6 +13,11 @@
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#include <plat_macros.S>
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#include <services/arm_arch_svc.h>
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/* Hardware handled coherency */
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#if HW_ASSISTED_COHERENCY == 0
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#error "Cortex-A76 must be compiled with HW_ASSISTED_COHERENCY enabled"
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#endif
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#define ESR_EL3_A64_SMC0 0x5e000000
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#define ESR_EL3_A32_SMC0 0x4e000000
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@ -8,6 +8,11 @@
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#include <cortex_a76ae.h>
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#include <cpu_macros.S>
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/* Hardware handled coherency */
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#if HW_ASSISTED_COHERENCY == 0
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#error "Cortex-A76AE must be compiled with HW_ASSISTED_COHERENCY enabled"
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#endif
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/* ---------------------------------------------
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* HW will do the cache maintenance while powering down
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* ---------------------------------------------
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -11,6 +11,11 @@
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#include <cpu_macros.S>
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#include <plat_macros.S>
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/* Hardware handled coherency */
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#if HW_ASSISTED_COHERENCY == 0
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#error "Deimos must be compiled with HW_ASSISTED_COHERENCY enabled"
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#endif
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/* ---------------------------------------------
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* HW will do the cache maintenance while powering down
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* ---------------------------------------------
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@ -11,6 +11,11 @@
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#include <cpu_macros.S>
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#include <plat_macros.S>
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/* Hardware handled coherency */
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#if HW_ASSISTED_COHERENCY == 0
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#error "Neoverse E1 must be compiled with HW_ASSISTED_COHERENCY enabled"
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#endif
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func neoverse_e1_cpu_pwr_dwn
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mrs x0, NEOVERSE_E1_CPUPWRCTLR_EL1
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orr x0, x0, #NEOVERSE_E1_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
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@ -10,6 +10,11 @@
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#include <cpuamu.h>
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#include <cpu_macros.S>
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/* Hardware handled coherency */
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#if HW_ASSISTED_COHERENCY == 0
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#error "Neoverse N1 must be compiled with HW_ASSISTED_COHERENCY enabled"
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#endif
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/* --------------------------------------------------
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* Errata Workaround for Neoverse N1 Errata
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* This applies to revision r0p0 and r1p0 of Neoverse N1.
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@ -11,6 +11,11 @@
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#include <cpu_macros.S>
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#include <plat_macros.S>
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/* Hardware handled coherency */
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#if HW_ASSISTED_COHERENCY == 0
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#error "Neoverse Zeus must be compiled with HW_ASSISTED_COHERENCY enabled"
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#endif
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/* ---------------------------------------------
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* HW will do the cache maintenance while powering down
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* ---------------------------------------------
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@ -95,18 +95,25 @@ PLAT_BL_COMMON_SOURCES := plat/arm/board/fvp/fvp_common.c
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FVP_CPU_LIBS := lib/cpus/${ARCH}/aem_generic.S
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ifeq (${ARCH}, aarch64)
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FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a35.S \
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# select a different set of CPU files, depending on whether we compile with
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# hardware assisted coherency configurations or not
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ifeq (${HW_ASSISTED_COHERENCY}, 0)
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FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a35.S \
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lib/cpus/aarch64/cortex_a53.S \
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lib/cpus/aarch64/cortex_a55.S \
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lib/cpus/aarch64/cortex_a57.S \
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lib/cpus/aarch64/cortex_a72.S \
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lib/cpus/aarch64/cortex_a73.S \
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lib/cpus/aarch64/cortex_a73.S
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else
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FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a55.S \
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lib/cpus/aarch64/cortex_a75.S \
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lib/cpus/aarch64/cortex_a76.S \
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lib/cpus/aarch64/cortex_a76ae.S \
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lib/cpus/aarch64/neoverse_n1.S \
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lib/cpus/aarch64/neoverse_e1.S \
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lib/cpus/aarch64/cortex_deimos.S \
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lib/cpus/aarch64/neoverse_zeus.S
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endif
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else
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FVP_CPU_LIBS += lib/cpus/aarch32/cortex_a32.S
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@ -217,10 +224,13 @@ ENABLE_PIE := 1
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endif
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ifeq (${ENABLE_AMU},1)
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BL31_SOURCES += lib/cpus/aarch64/cortex_a75_pubsub.c \
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lib/cpus/aarch64/neoverse_n1_pubsub.c \
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lib/cpus/aarch64/cpuamu.c \
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BL31_SOURCES += lib/cpus/aarch64/cpuamu.c \
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lib/cpus/aarch64/cpuamu_helpers.S
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ifeq (${HW_ASSISTED_COHERENCY}, 1)
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BL31_SOURCES += lib/cpus/aarch64/cortex_a75_pubsub.c \
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lib/cpus/aarch64/neoverse_n1_pubsub.c
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endif
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endif
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ifeq (${RAS_EXTENSION},1)
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